DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (claims 1-17) in the reply filed on December 8, 2025 is acknowledged.
Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on December 8, 2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US Publication No. 2020/0373331) in view of Kim et al (US Publication No. 2021/0028112).
Regarding claim 1, Kim 331 discloses a semiconductor device, comprising: a base layer Fig 1B, 110 including a silicon material ¶0015, the base layer including a first surface and a second surface opposite to the first surface in a vertical direction Fig 1B; a field effect transistor disposed on the first surface of the base layer ¶0014; a first insulating interlayer Fig 1B, 112 covering the field effect transistor; a buried vertical rail Fig 1B, 150 passing through the first insulating interlayer Fig 1B, 112 and the base layer Fig 1B, 110, the buried vertical rail Fig 1B, 150 including a first metal pattern Fig 1B, 154 having a sidewall and a first barrier pattern Fig 1B, 152 surrounding the sidewall of the first metal pattern Fig 1B, 154;a first lower insulating interlayer Fig 1B, 105 on the second surface of the base layer Fig 1B, 110; and a lower contact plug Fig 1B, 160 passing through the first lower insulating interlayer Fig 1B, 105 and directly contacting a lower surface of the buried vertical rail Fig 1B, the lower contact plug Fig 1B, 160 including a second metal pattern Fig 1B, 164 having a sidewall and a second barrier pattern Fig 1B, 162 surrounding the sidewall of the second metal pattern Fig 1B.
Kim 331 discloses all the limitation but silent on the arrangement of the buried rail relative to the contact plug.
Whereas Kim 112 discloses wherein a bottom surface of the first metal pattern and a top surface of the second metal pattern directly contact each other Fig 6-9.
Kim 331 and 112 are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim 331 because they are from the same field of endeavor.
Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the arrangement of Kim 331 and incorporate the teachings of Kim 112 to improve connectivity.
Regarding claim 2, Kim 331 discloses a second lower insulating interlayer Fig 1B, 170 on a lower surface of the first lower insulating interlayer Fig 1B, 105; and a lower wiring Fig 1B, 180 disposed in the second lower insulating interlayer Fig 1B, 170, the lower wiring is electrically connected to the lower contact plug Fig 1B.
Regarding claim 3, Kim 112 discloses a second insulating interlayer Fig 2, 175 on the first insulating interlayer Fig 2, 162; and an upper wiring Fig 2, M1 disposed in the second insulating interlayer Fig 2, 175, the upper wiring is electrically connected to a portion of the field effect transistor Fig 2.
Regarding claim 4, Kim 112 discloses wherein an interface between the buried vertical rail and the lower contact plug is not coplanar with the second surface of the base layer Fig 13C, the buried vertical rail and the lower contact plug directly contacting each other at the interface Fig 6-9 and Fig 13C.
Regarding claim 5, Kim 331 discloses wherein each of the first and second barrier patterns includes Ti, Ta, TiN, TaN or a combination thereof ¶0062 and 0089.
Regarding claim 6, Kim 331 discloses wherein each of the first and second metal patterns includes Cu, W, Mo, Ru, or Nb ¶0062 and 0089.
Regarding claim 7, Kim 112 discloses an insulation liner between the buried vertical rail and the base layer, wherein the insulation liner surrounds an outer wall of the buried vertical rail ¶0066.
Regarding claim 8, Kim 112 discloses wherein: the buried vertical rail has a sidewall slope having an inner width that gradually decreases from a top portion of the buried vertical rail to a bottom portion of the buried vertical rail and the lower contact plug has a sidewall slope having an inner width that gradually decreases from a bottom portion of the lower contact plug to a top portion of the lower contact plug ¶0035 Fig 3-6.
Regarding claim 9, Kim 331 discloses wherein the field effect transistor includes a fin field effect transistor or a multi-bridge channel field effect transistor ¶0014.
Regarding claim10, Kim 331 discloses wherein: the field effect transistor includes a gate structure and impurity regions; and a first contact plug electrically connects the buried vertical rail and the impurity regions Fig 1A-1C ¶0021-0030.
Regarding claim 11, Kim 331 discloses a semiconductor device, comprising: a base layer Fig 1B, 110 including a silicon material ¶0015, the base layer including a first surface and a second surface opposite to the first surface in a vertical direction Fig 1B; active fins Fig 1C, FA protruding from the first surface of the base layer Fig 1C, 110 in the vertical direction, the active fins Fig 1C, FA extending in a first direction; a gate structure Fig 1C, GS on the first surface of the base layer, the gate structure extending in a second direction perpendicular to the first direction and crossing the active fins Fig 1C;semiconductor patterns Fig 1B, 130 on active fins adjacent to both sides of the gate structure, the semiconductor patterns including impurity regions ¶0026 Fig 1B; a first insulating interlayer Fig 1B, 112 on the first surface of the base layer Fig 1B, the first insulating layer covering the gate structure and the semiconductor patterns Fig 1B; a buried vertical rail Fig 1B, 150 passing through the first insulating interlayer Fig 1B, 112 and the base layer Fig 1B, 110 in the vertical direction, the buried vertical rail Fig 1B, 150 including a first metal pattern Fig 1B, 154 having a sidewall and a first barrier pattern Fig 1B, 152 surrounding the sidewall of the first metal pattern Fig 1B, 154;a first lower insulating interlayer Fig 1B, 105 on the second surface of the base layer Fig 1B, 110; and a lower contact plug Fig 1B, 160 passing through the first lower insulating interlayer Fig 1B, 105 in the vertical direction and directly contacting a lower surface of the buried vertical rail Fig 1B, the lower contact plug Fig 1B, 160 including a second metal pattern Fig 1B, 164 having a sidewall and a second barrier pattern Fig 1B, 162 surrounding the sidewall of the second metal pattern Fig 1B.
Kim 331 discloses all the limitation but silent on the arrangement of the buried rail relative to the contact plug.
Whereas Kim 112 discloses wherein a bottom surface of the first metal pattern and a top surface of the second metal pattern directly contact each other Fig 6-9.
Kim 331 and 112 are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim 331 because they are from the same field of endeavor.
Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the arrangement of Kim 331 and incorporate the teachings of Kim 112 to improve connectivity.
Regarding claim 12, Kim 112 discloses a first contact plug on the first insulating interlayer, the first contact plug electrically connecting the buried vertical rail and the semiconductor patterns to each other Fig 11E.
Regarding claim 13, Kim 112 discloses wherein a bottom surface of the first metal pattern and an upper surface of the second metal pattern are aligned with each other in the vertical direction Fig 6-9 and Fig 13C.
Regarding claim 14, Kim 112 discloses wherein: the buried vertical rail has a sidewall slope having an inner width that gradually decreases from a top portion of the buried vertical rail to a bottom portion of the buried vertical rail; and decreases from a bottom portion of the first lower contact plug to a top portion of the first lower contact plug¶0035 Fig 3-6.
Regarding claim 15, Kim 331 discloses a second lower insulating interlayer Fig 1B, 170 on a lower surface of the first lower insulating interlayer Fig 1B, 105; and a lower wiring Fig 1B, 180 disposed in the second lower insulating interlayer Fig 1B, 170, the lower wiring is electrically connected to the lower contact plug Fig 1B.
Regarding claim 16, Kim 112 discloses an insulation liner between the buried vertical rail and the base layer, wherein the insulation liner surrounds an outer wall of the buried vertical rail ¶0066.
Regarding claim 17, Kim 331 and 112 discloses wherein the gate structure covers sidewalls and upper surfaces of the active fins Kim 331-Fig 1C; Kim 112 Fig 2.
Conclusion
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/CHRISTINE A ENAD/ Primary Examiner, Art Unit 2811