DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
2. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1-2, 4, 7-12, and 14-16 are rejected under 35 U.S.C. 103 as obvious over Lee et al. (US 2015/0255464 A1), hereinafter as L1, in view of Kim et al. (US 2014/0061743 A1), hereinafter as K1
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4. Regarding Claim 1, L1 discloses a semiconductor memory device (see Figs. 1-10, “Labeled Fig. 2” above, and see [0005-0006, 0022] “memory devices … cell array”) comprising:
a substrate (element 110 and substrate below, see [0025] “substrate”; and see Fig. 3 element 200, see [0029] “substrate 200”) which includes a cell region (labeled element “Cell Region”) and a connecting region (labeled element “Connecting Region”) around the cell region (defined to be around in a top view);
a cell active region (labeled element “Cell Active Region”) which is defined by a cell element isolation layer (element 112 in the labeled element “Cell Region”, [0023] “device isolation layer 112”) in the cell region;
a connecting element isolation layer (element 112 portion within element “Connecting Region”, see [0023]) which is placed in the connecting region;
a word line structure (element 114 and connection to the sub word line driver through metal line (MO) and portion of element 116 in between elements 114b, see [0022] “buried gate 114 to a sub word line driver (SWD) through a metal line (MO)”) which is buried in the cell region and the connecting region (see “Labeled Fig. 2” above) and extends in a first horizontal direction (first horizontal lateral direction in the cross sectional view of Fig. 2, horizontal direction in the top view of Fig. 1);
a bit line structure (element 118, see [0027] “bit line 118”) which is disposed on the substrate and extends in a second horizontal direction (into and out of the page in the cross sectional view of Fig. 2, vertical direction in the top view of Fig. 1) intersecting the first horizontal direction; and
a dummy active region (labeled element “Dummy Active Region”) disposed between the cell element isolation layer and the connecting element isolation layer (see “Labeled Fig. 2” above),
wherein the word line structure includes a gate electrode (element 114a,b see [0024] “gate electrode 114a … gate electrode 114b”) and a gate capping layer (portion of element 116 in between elements 114b, see [0026] “insulating layer 116”; note, the interpretation of the gate capping layer is consistent with the Applicant’s invention which has a dielectric portion abutting the gate electrode and having a coplanar upper surface), wherein the gate electrode includes:
a first portion (element 114a) that does not overlap the gate capping layer in the first horizontal direction (see Fig. 2), and
a second portion (element 114b) that is disposed on the first portion and overlaps the gate capping layer in the first horizontal direction (see Fig. 2), and
wherein the second portion overlaps the dummy active region in a vertical direction intersecting the first and second horizontal directions (see Fig. 2).
L1 does not disclose a capacitor structure disposed on the cell region and connected to the cell active region.
K1 discloses (see Figs. 1A-C) a capacitor structure (element CA, see [0052] “data storage elements may be capacitors CA”) disposed on the cell region and connected to the cell active region (see Fig. 1B-C and [0016] “bit lines provided on the substrate and connected to the first doped region; and a capacitor on the substrate and coupled to the second doped region”).
The type of memory element as taught by K1 is incorporated as the type of memory element of L1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K1 with L1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known memory element for another in a similar device to obtain predictable results (see K1 Figs. 1A-C).
5. Regarding Claim 2, L1, K1 disclose the semiconductor memory device of claim 1,
wherein at least a part of the second portion of the gate electrode is buried in the connecting region (see “Labeled Fig. 2” above).
6. Regarding Claim 4, L1, K1 disclose the semiconductor memory device of claim 1,
wherein at least a part of the dummy active region overlaps the gate capping layer in the first horizontal direction (see “Labeled Fig. 2” above).
7. Regarding Claim 7, L1, K1 disclose the semiconductor memory device of claim 1, further comprising (see “Labeled Fig. 2” above):
a word line contact (element 120, see [0025] “contact 120”) which is disposed on the connecting region and contacts the second portion of the gate electrode (see “Labeled Fig. 2” above).
8. Regarding Claim 8, L1, K1 disclose the semiconductor memory device of claim 1,
wherein a part of the second portion of the gate electrode overlaps the cell active region in the vertical direction (see “Labeled Fig. 2” above).
9. Regarding Claim 9, L1, K1 disclose the semiconductor memory device of claim 1,
wherein an upper surface of the second portion of the gate electrode is coplanar with an upper surface of the gate capping layer (see “Labeled Fig. 2” above, the gate capping layer is defined to be entirely between the elements 114b and is coplanar with the element 116 portion in between).
10. Regarding Claim 10, L1, K1 disclose the semiconductor memory device of claim 1,
wherein the first portion and the second portion are formed of different materials from each other (see K1 [0024] “The first gate electrode 114a may include a metal conductive layer such as tungsten (W), and the second gate electrode 114b may include a polysilicon layer”).
11. Regarding Claim 11, L1, K1 disclose the semiconductor memory device of claim 1,
wherein the dummy active region does not completely overlap the gate capping layer in the vertical direction (see “Labeled Fig. 2” above).
12. Regarding Claim 12, L1 discloses a semiconductor memory device (see Figs. 1-10, “Labeled Fig. 2” above, and see [0005-0006, 0022] “memory devices … cell array”) comprising:
a substrate (element 110 and substrate below, see [0025] “substrate”; and see Fig. 3 element 200, see [0029] “substrate 200”) which includes an edge region (element 110 of labeled element “Cell Region” and “Dummy Active Region”), and a center region (element 110 of labeled element “Cell Active Region”) defined by the edge region (see “Labeled Fig. 2” above);
a cell active region (labeled element “Cell Active Region”) which is disposed on the center region and defined by a cell element isolation layer (element 112 in the labeled element “Cell Region”, [0023] “device isolation layer 112”);
a plurality of word line structures (see Fig. 1) which are buried in the substrate (see “Labeled Fig. 2” above), extend in a first horizontal direction (first horizontal lateral direction in the cross sectional view of Fig. 2, horizontal direction in the top view of Fig. 1), and are spaced apart in a second horizontal direction (into and out of the page in the cross sectional view of Fig. 2, vertical direction in the top view of Fig. 1) intersecting the first horizontal direction;
a plurality of bit line structures (element 118s, see [0027] “bit line 118”) which are disposed on the substrate (see “Labeled Fig. 2” above), extend in the second horizontal direction (see Figs. 1-2), and are spaced apart in the first horizontal direction (see “Labeled Fig. 2” above);
a dummy active region (labeled element “Dummy Active Region”) disposed on the edge region (see “Labeled Fig. 2” above), wherein each word line structure of the plurality of word line structures includes:
a gate electrode (element 114a,b see [0024] “gate electrode 114a … gate electrode 114b”) including a first region disposed on the center region (see “Labeled Fig. 2” above) and a second region (element 114a) disposed on the edge region (see “Labeled Fig. 2” above), and
a gate capping layer disposed on the first region (element 114a) of the gate electrode,
wherein an upper surface of the second region of the gate electrode is coplanar with an upper surface of the gate capping layer (see “Labeled Fig. 2” above, the gate capping layer is defined to be entirely between the elements 114b and is coplanar with the element 116 portion in between), and
wherein the second region of the gate electrode overlaps the dummy active region in a vertical direction (vertical direction in the cross sectional view of Fig. 2) that intersects the first and second horizontal directions (see “Labeled Fig. 2” above).
L1 does not disclose a capacitor structure disposed on the substrate and connected to the cell active region.
K1 discloses (see Figs. 1A-C) a capacitor structure (element CA, see [0052] “data storage elements may be capacitors CA”) disposed on the substrate and connected to the cell active region (see Fig. 1B-C and [0016] “bit lines provided on the substrate and connected to the first doped region; and a capacitor on the substrate and coupled to the second doped region”).
The type of memory element as taught by K1 is incorporated as the type of memory element of L1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K1 with L1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known memory element for another in a similar device to obtain predictable results (see K1 Figs. 1A-C).
13. Regarding Claim 14, L1, K1 disclose the semiconductor memory device of claim 12,
wherein at least a part of the dummy active region overlaps the gate capping layer in the first horizontal direction (see “Labeled Fig. 2” above).
14. Regarding Claim 15, L1, K1 disclose the semiconductor memory device of claim 12,
wherein the dummy active region does not overlap the gate capping layer in the first horizontal direction (see “Labeled Fig. 2” above).
15. Regarding Claim 16, L1, K1 disclose the semiconductor memory device of claim 12,
wherein the dummy active region does not completely overlap the gate capping layer in the vertical direction (see “Labeled Fig. 2” above).
16. Claim 3 is rejected under 35 U.S.C. 103 as obvious over Lee et al. (US 2015/0255464 A1), hereinafter as L1, in view of Kim et al. (US 2014/0061743 A1), hereinafter as K1, in view of Liaw (US 10,460,794 B1), hereinafter as L2
17. Regarding Claim 3, L1, K1 disclose the semiconductor memory device of claim 1,
wherein (see “Labeled Fig. 2” above) a first height of a first upper portion of the dummy active region (top portion of element 110b of the “Dummy Active Region”) and a second height of a second upper portion of the cell active region (top portion of element 110a in “Cell Active Region”),
wherein the first upper portion of the dummy active region and the second upper portion of the cell active region are surrounded by the gate electrode (see “Labeled Fig. 2” above), and
wherein the first and second heights are measured in the vertical direction relative to a bottom surface of the gate electrode (see “Labeled Fig. 2” above).
L1, K1 do not disclose the first height is higher than the second height.
L2 discloses the first height is higher than the second height (see Fig. 5C first height of the dummy active regions elements 305a are higher than the second height of the cell active region elements 305c).
The first and second height relationship as taught by L2 is incorporated as the first and second height relationship of L1, K1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K1 with L1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known memory element for another in a similar device for which the options are provided as alternatives to obtain predictable results (see L2 Fig. 5A versus 5C).
18. Claims 1 and 5 are rejected under 35 U.S.C. 103 as obvious over Lee et al. (US 2015/0255464 A1), hereinafter as L1, in view of Kim et al. (US 2014/0061743 A1), hereinafter as K1
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19. Regarding Claim 1, L1 discloses a semiconductor memory device (see Figs. 1-10, “2nd Labeled Fig. 2” above, and see [0005-0006, 0022] “memory devices … cell array”) comprising:
a substrate (element 110 and substrate below, see [0025] “substrate”; and see Fig. 3 element 200, see [0029] “substrate 200”) which includes a cell region (labeled element “Cell Region”) and a connecting region (labeled element “Connecting Region”) around the cell region (defined to be around in a top view);
a cell active region (labeled element “Cell Active Region”) which is defined by a cell element isolation layer (element 112 in the labeled element “Cell Region”, [0023] “device isolation layer 112”) in the cell region;
a connecting element isolation layer (element 112 portion within element “Connecting Region”, see [0023]) which is placed in the connecting region;
a word line structure (element 114 and connection to the sub word line driver through metal line (MO) and portion of element 116 in between elements 114b, see [0022] “buried gate 114 to a sub word line driver (SWD) through a metal line (MO)”) which is buried in the cell region and the connecting region (see “2nd Labeled Fig. 2” above) and extends in a first horizontal direction (first horizontal lateral direction in the cross sectional view of Fig. 2, horizontal direction in the top view of Fig. 1);
a bit line structure (element 118, see [0027] “bit line 118”) which is disposed on the substrate and extends in a second horizontal direction (into and out of the page in the cross sectional view of Fig. 2, vertical direction in the top view of Fig. 1) intersecting the first horizontal direction; and
a dummy active region (labeled element “Dummy Active Region”) disposed between the cell element isolation layer and the connecting element isolation layer (see “2nd Labeled Fig. 2” above),
wherein the word line structure includes a gate electrode (element 114a,b see [0024] “gate electrode 114a … gate electrode 114b”) and a gate capping layer (portion of element 116 in between elements 114b, see [0026] “insulating layer 116”; note, the interpretation of the gate capping layer is consistent with the Applicant’s invention which has a dielectric portion abutting the gate electrode and having a coplanar upper surface), wherein the gate electrode includes:
a first portion (element 114a) that does not overlap the gate capping layer in the first horizontal direction (see Fig. 2), and
a second portion (element 114a) that is disposed on the first portion and overlaps the gate capping layer in the first horizontal direction (see Fig. 2), and
wherein the second portion overlaps the dummy active region in a vertical direction intersecting the first and second horizontal directions (see Fig. 2).
L1 does not disclose a capacitor structure disposed on the cell region and connected to the cell active region.
K1 discloses (see Figs. 1A-C) a capacitor structure (element CA, see [0052] “data storage elements may be capacitors CA”) disposed on the cell region and connected to the cell active region (see Fig. 1B-C and [0016] “bit lines provided on the substrate and connected to the first doped region; and a capacitor on the substrate and coupled to the second doped region”).
The type of memory element as taught by K1 is incorporated as the type of memory element of L1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K1 with L1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known memory element for another in a similar device to obtain predictable results (see K1 Figs. 1A-C).
20. Regarding Claim 5, L1, K1 disclose the semiconductor memory device of claim 1,
wherein the dummy active region does not overlap the gate capping layer in the first horizontal direction (see “2nd Labeled Fig. 2” above).
Allowable Subject Matter
21. Claims 17-20 are allowed.
Claims 6 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reason for indicating allowable subject matter:
The prior art made of record, either singularly or in combination, does not disclose or suggest at least the claim limitations of:
22. Claim 6, “wherein the gate capping layer includes: a gate capping conductive layer, and a gate capping insulating layer on the gate capping conductive layer” – as instantly claimed and in combination with the additionally claimed limitations.
23. Claim 13, “wherein the gate capping layer includes: a gate capping conductive layer, and a gate capping insulating layer on the gate capping conductive layer” – as instantly claimed and in combination with the additionally claimed limitations.
24. Claim 17, “a gate capping conductive layer, and a gate capping insulating layer, and wherein the gate electrode includes: a first portion that does not overlap the gate capping conductive layer and the gate capping insulating layer in the first horizontal direction, and a second portion that overlaps the gate capping conductive layer and the gate capping insulating layer in the first horizontal direction” – as instantly claimed and in combination with the additionally claimed limitations.
All claims depending on the current claim incorporate the same allowable subject matter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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/SAMUEL PARK/Examiner, Art Unit 2818
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