DETAILED ACTION
This action is responsive to the amendment received on 06/01/2026 and the request for continued examination received on 07/01/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/01/2026 has been entered.
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in REPUBLIC OF KOREA on 10/27/2022.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 06/24/2026 has/have been considered by the examiner and made of record in the application file.
Claim Interpretation
At least claims 12 and 14 recite limitations wherein a structure “comprises at least one of . . .” and the phrasing concludes with the word “and” before the final option in the list. A complete example from claim 14 is “the first patterned side surface comprises at least one of a saw pattern, a polygonal pattern, a semicircular pattern, and a semielliptical pattern”. This phrasing has been interpreted to mean the structure may comprise any one of these elements individually and read on the limitation, not that the structure must comprise at least one of each and every one of them. This is in accordance with [0038] of the instant application’s specification stating “each of such phrases as "A or B," "at least one of A and B," "at least one of A or B," "A, B, or C," "at least one of A, B, and C," and "at least one of A, B, or C," may include any one of, or all possible combinations of the items enumerated together in a corresponding one of the phrases”.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim(s) 1-17, 21, and 21-34 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1, 17, and 23 have each been amended to recite the following limitation which is interpreted by the examiner as new matter:
“a distance between the first patterned side surface and the second patterned side surface comprises:
a maximum distance between a top portion of a protrusion of the second patterned side surface and a bottom portion of a recess of the first patterned side surface in the second horizontal direction, and
a minimum distance between the top portion of the protrusion of the second patterned side surface and a top portion of a protrusion of the first patterned side surface”
The remarks submitted with this amendment on 06/01/2026 describe the support for this amendment as being found in Figure 1 of the instant application which has been provided here with some examiner annotations for clarity of the examiner’s position. In the annotated figure, the examiner has provided four double headed arrows with dashed lines representing distances between the first patterned side surface and the second patterned side surface. It is the examiner’s understanding that when referring to the maximum distance in the amendment, applicant is referring to the distance S1 between an opposing protrusion and recess in the respective patterns. It is also the examiner’s understanding that when referring to the minimum distance in the amendment, applicant is referring to the distance D1a between neighboring opposing protrusions in the respective patterns. The examiner interprets referring to these respective distances as being the minimum/maximum as new matter.
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The instant application does not refer to S1 or D1a as being the maximum or minimum distances between the two patterned side surfaces in the originally filed specification and claims. Furthermore, these drawings are not indicated as being drawn to any particular scale or shown to have particular angles and/or dimensions. Without these details, it is entirely conceivable that any of the arrows provided as annotations by the examiner could be the minimum and/or maximum distances between the opposing patterned surfaces of the two metal lines. For this reason, these limitations are interpreted by the examiner as encompassing new matter. Claim(s) 1, 17, and 23 are therefore rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. All of the remaining balance of claims are rejected under 35 U.S.C. 112(a) at least for their dependencies.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 14-17, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0282753 A1; Kim, Sun-Oo; 11/2012; (“Kim”).
Regarding Claim 1. Kim discloses An integrated circuit (Figures 5 and 6, semiconductor capacitor structure #300, Figure 5 is a side view, which may part of an integrated circuit according to [0080], the figure 6 embodiment of the structure wherein capacitor plates are interleaved ([0058]-[0066]) is utilized with the stacked alternating electrodes and vias of Fig. 5 according to [0066]), comprising:
a substrate (#302, Figure 5, equivalent to #102 in Figure 1 described as a workpiece which may be a semiconductor substrate according to [0025]); and
a capacitor structure (#320a and #320b, Figure 5, capacitor plates), disposed above the substrate in a vertical direction (Figure 5, #320a/b are disposed above #302 in a vertical direction), the capacitor structure comprising:
a first electrode (#320a, Figure 5, capacitor plate) configured to receive a first voltage ([0004], capacitor may have an applied voltage) and comprising at least one first metal line (leftmost #306e of #320a, Figures 5 and 6, conductive member) disposed above the substrate (Figure 5, each #306e is disposed above #302), the at least one first metal line extending in a first horizontal direction (Figure 6, each #306e extends in a first up/down horizontal direction in the top view) and having a first patterned side surface extending in the vertical direction (Figure 6, right side surface of leftmost #306e of #320a is patterned and extends in the vertical direction of Figure 5);
a second electrode (#320b, Figure 5, capacitor plate) configured to receive a second voltage ([0004], capacitor may have an applied voltage) and comprising at least one second metal line (leftmost #306e of #320b, Figures 5 and 6, conductive member) disposed above the substrate (Figure 5, each #306e is disposed above #302), the at least one second metal line extending in the first horizontal direction (Figure 6, each #306e extends in a first up/down horizontal direction in the top view) and having a second patterned side surface extending in the vertical direction (Figure 6, left side surface of leftmost #306e of #320b is patterned and extends in the vertical direction of Figure 5); and
a dielectric layer (#304e, Figures 5 and 6, dielectric materials) laterally disposed between the first patterned side surface and the second patterned side surface (Figures 5 and 6, #304e is laterally disposed between the patterned side surfaces of the #306e lines),
wherein the first electrode, the second electrode, and the dielectric layer are disposed on a same layer above the substrate (Figure 5, #320a, #320b, and #304e are all disposed on the same topmost layer above #302),
wherein the at least one second metal line is laterally spaced apart from the at least one first metal line in a second horizontal direction (Figures 5 and 6, each #306e is spaced apart from adjacent #306e structures in a left-right second horizontal direction by at least the distance d5).
Kim does not explicitly disclose that a distance between the first patterned side surface and the second patterned side surface comprises: a maximum distance between a top portion of a protrusion of the second patterned side surface and a bottom portion of a recess of the first patterned side surface in the second horizontal direction, and a minimum distance between the top portion of the protrusion of the second patterned side surface and a top portion of a protrusion of the first patterned side surface.
However, Kim does teach in [0042]-[0044] and [0062] that the dimensions of the device including the widths of the pattern surfaces (d1, d3, and d4) along with the spacing between the protrusions and recesses of adjacent patterned surfaces (d5) may be set as necessary based on minimum feature sizes and the required capacitance of the device (see [0004]) given the available space (see [0073]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider setting the spacing of the distance between the plates and the dimensions of the patterned surface such that a distance between the first patterned side surface and the second patterned side surface comprises: a maximum distance between a top portion of a protrusion of the second patterned side surface and a bottom portion of a recess of the first patterned side surface in the second horizontal direction, and a minimum distance between the top portion of the protrusion of the second patterned side surface and a top portion of a protrusion of the first patterned side surface as an obvious routine optimization (see MPEP 2144.05.II.B). It is well understood by the teachings of Kim that the spacings and dimensions of and between the patterned surfaces are a matter of optimization for the user of the device to achieve a desired capacitance given an available amount of space in the device (see [0004], [0063], and [0073]). This is in agreement with the instant applications descriptions of these spacings (see [0055] and [0057] of the instant application) as being “changed in various ways according to embodiments and/or design constraints”.
Regarding Claim 2. Kim discloses The integrated circuit of claim 1, wherein a first level of a first upper surface of the at least one first metal line matches a second level of a second upper surface of the at least one second metal line (Figure 5, each #306e shares a level of its upper surface with level of the upper surface of each other #306e).
Regarding Claim 3. Kim discloses The integrated circuit of claim 1, wherein:
the first patterned side surface comprises a first pattern (Figure 6, right side surface of leftmost #306e of #320a is patterned to have alternating extent protruding square shapes) extending in the vertical direction ([0062] and Figure 5, the distance between the plates d5 is maintained along the vertical direction such that the pattern necessarily extends in the vertical direction),
the second patterned side surface comprises a second pattern (Figure 6, left side surface of leftmost #306e of #320b is patterned to have alternating extent protruding square shapes) extending in the vertical direction ([0062] and Figure 5, the distance between the plates d5 is maintained along the vertical direction such that the pattern necessarily extends in the vertical direction),
the first patterned side surface faces the second patterned side surface (Figure 6, right side surface of leftmost #306e of #320a faces left side surface of leftmost #306e of #320b), and
the first pattern and the second pattern have an engagement structure (Figure 6, the patterned sidewalls are structured to at least partially engage with one another of adjacent sidewalls, i.e. may partially fit into one another).
Regarding Claim 4. Kim discloses The integrated circuit of claim 3, wherein:
the first patterned side surface and the second patterned side surface are spaced apart by a first space in the second horizontal direction (Figure 6, right side surface of leftmost #306e of #320a is spaced apart from left side surface of leftmost #306e of #320b by a first space d5 in the left-right second horizontal direction), and
the first space comprises at least a portion of the dielectric layer (Figures 5 and 6, the gap d5 comprises at least a portion of #304e).
Regarding Claim 14. Kim discloses The integrated circuit of claim 1, wherein:
the first patterned side surface comprises at least one of a saw pattern, a polygonal pattern, a semicircular pattern, and a semielliptical pattern (Figure 6, right side surface of leftmost #306e of #320a is patterned to have alternating extent protruding polygonal square shapes), and
the second patterned side surface comprises at least one of the saw pattern, the polygonal pattern, the semicircular pattern, and the semielliptical pattern (Figure 6, left side surface of leftmost #306e of #320b is patterned to have alternating extent protruding polygonal square shapes).
Regarding Claim 15. Kim discloses The integrated circuit of claim 1, wherein:
the first electrode (#320a, Figure 5, capacitor plate) comprises a plurality of first metal lines comprising the at least one first metal line (Figure 6, #320a comprises a plurality of #306e conductive members including the leftmost),
the second electrode (#320b, Figure 5, capacitor plate) comprises a plurality of second metal lines comprising the at least one second metal line (Figure 6, #320b comprises a plurality of #306e conductive members including the leftmost), and
the plurality of first metal lines and the plurality of second metal lines are alternately disposed in the second horizontal direction (Figure 6, #306e conductive members of #320a and #320b are alternately disposed along the left-right second horizontal direction).
Regarding Claim 16. Kim discloses The integrated circuit of claim 15, wherein:
the first electrode (#320a, Figure 5, capacitor plate) further comprises a first conductive line (#312a, Figure 6, conductive line), extending in the second horizontal direction, coupled to each of the plurality of first metal lines (Figure 6, #312a extends in the left-right second horizontal direction and is electrically coupled to each #306e of #320a), and
the second electrode (#320b, Figure 5, capacitor plate) further comprises a second conductive line (#312b, Figure 6, conductive line), extending in the second horizontal direction, coupled to each of the plurality of second metal lines (Figure 6, #312b extends in the left-right second horizontal direction and is electrically coupled to each #306e of #320b).
Regarding Claim 17. Kim discloses An integrated circuit (Figures 5 and 6, semiconductor capacitor structure #300, Figure 5 is a side view, which may part of an integrated circuit according to [0080], the figure 6 embodiment of the structure wherein capacitor plates are interleaved ([0058]-[0066]) is utilized with the stacked alternating electrodes and vias of Fig. 5 according to [0066]), comprising:
a substrate (#302, Figure 5, equivalent to #102 in Figure 1 described as a workpiece which may be a semiconductor substrate according to [0025]); and
a capacitor structure (#320a and #320b, Figure 5, capacitor plates), disposed above the substrate in a vertical direction (Figure 5, #320a/b are disposed above #302 in a vertical direction), comprising:
a first electrode (#320a, Figure 5, capacitor plate) configured to receive a first voltage ([0004], capacitor may have an applied voltage),
a second electrode (#320b, Figure 5, capacitor plate) configured to receive a second voltage ([0004], capacitor may have an applied voltage), the first voltage being different from the second voltage ([0004], the function of a capacitor is to store charge through voltage difference in adjacent electrode plates), and
a dielectric layer (#304c, Figures 5 and 6, dielectric materials) disposed between the first electrode and the second electrode (Figures 5 and 6, #304c is disposed between #320a and #320b),
wherein the first electrode (#320a, Figure 5) comprises:
a first metal line disposed above the substrate (leftmost #306c of #320a, Figures 5 and 6, conductive member disposed above #302) extending in a first horizontal direction (Figures 5 and 6, each #306c extends in a first up/down horizontal direction in the top view noting that [0066] describes that Figure 6 also has the staggered structure in the vertical direction like Fig. 5); and
a second metal line (leftmost #306e of #320a, Figures 5 and 6, conductive member) extending in the first horizontal direction (Figures 5 and 6, each #306e extends in a first up/down horizontal direction in the top view), disposed above the first metal line in the vertical direction (Figure 5, #306e members are above #306c members), and coupled to the first metal line (Figure 5, #306e members are coupled to underlying #306c members by vias #308d),
wherein the second electrode (#320b, Figure 5) comprises:
a third metal line disposed above the substrate (leftmost #306c of #320b, Figures 5 and 6, conductive member disposed above #302) extending in the first horizontal direction (Figures 5 and 6, each #306c extends in a first up/down horizontal direction in the top view noting that [0066] describes that Figure 6 also has the staggered structure in the vertical direction like Fig. 5), spaced apart from the first metal line in a second horizontal direction (Figure 5, #306c members of #320a/b are spaced apart from one another in a second left-right horizontal direction), and disposed at a same first level as the first metal line (Figure 6, #306c members are all disposed in the M2 metal layer); and
a fourth metal line (leftmost #306e of #320b, Figures 5 and 6, conductive member) extending in the first horizontal direction (Figures 5 and 6, each #306e extends in a first up/down horizontal direction in the top view), spaced apart from the second metal line in the second horizontal direction (Figure 5, #306e members of #320a/b are spaced apart from one another in the second left-right horizontal direction), disposed at a same second level as the second metal line (Figure 6, #306e members are all disposed in the MX metal layer), and coupled to the third metal line (Figure 5, #306e members are coupled to underlying #306c members by vias #308d),
wherein side surfaces of each of the first metal line, the second metal line, the third metal line, and the fourth metal line comprise respective patterns extending in the vertical direction (Figure 6, side surfaces of all portions of #306e and #306c members are patterned, this is also observed in Figure 7 and described in [0067]),
wherein the first metal line has a first patterned side surface extending in the vertical direction (Figure 6, right side surface of leftmost #306c of #320a is patterned, similar to that of #306e shown in Figure 6 according to [0062]-[0066], and extends in the vertical direction of Figure 5),
wherein the third metal line has a second patterned side surface extending in the vertical direction (Figure 6, left side surface of leftmost #306c of #320b is patterned, similar to that of #306e shown in Figure 6 according to [0062]-[0066], and extends in the vertical direction of Figure 5),
wherein a portion of the dielectric layer is laterally disposed between the first patterned side surface and the second patterned side surface that face each other (Figures 5 and 6, a portion of #304c is laterally disposed between the patterned side surfaces of the #306c lines),
wherein the first metal line, the third metal line, and the portion of the dielectric layer are disposed at the same first level above the substrate (Figure 5, #306c of #320a, #306c of #320b, and #304c are all disposed on the same layer above #302),
wherein each of the first patterned side surface and the second patterned side surface comprises a plurality of protrusions and recesses arranged alternately in the first horizontal direction (Figure 6, left and right side surfaces of #306c lines of #320a and #320b are patterned to have alternating extent protruding square shapes and recesses therebetween in the first up/down horizontal direction in the top view).
Kim does not explicitly disclose that a distance between the first patterned side surface and the second patterned side surface comprises: a maximum distance between a top portion of a protrusion of the second patterned side surface and a bottom portion of a recess of the first patterned side surface in the second horizontal direction, and a minimum distance between the top portion of the protrusion of the second patterned side surface and a top portion of a protrusion of the first patterned side surface.
However, Kim does teach in [0042]-[0044] and [0062] that the dimensions of the device including the widths of the pattern surfaces (d1, d3, and d4) along with the spacing between the protrusions and recesses of adjacent patterned surfaces (d5) may be set as necessary based on minimum feature sizes and the required capacitance of the device (see [0004]) given the available space (see [0073]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider setting the spacing of the distance between the plates and the dimensions of the patterned surface such that a distance between the first patterned side surface and the second patterned side surface comprises: a maximum distance between a top portion of a protrusion of the second patterned side surface and a bottom portion of a recess of the first patterned side surface in the second horizontal direction, and a minimum distance between the top portion of the protrusion of the second patterned side surface and a top portion of a protrusion of the first patterned side surface as an obvious routine optimization (see MPEP 2144.05.II.B). It is well understood by the teachings of Kim that the spacings and dimensions of and between the patterned surfaces are a matter of optimization for the user of the device to achieve a desired capacitance given an available amount of space in the device (see [0004], [0063], and [0073]). This is in agreement with the instant applications descriptions of these spacings (see [0055] and [0057] of the instant application) as being “changed in various ways according to embodiments and/or design constraints”.
Regarding Claim 21. Kim discloses The integrated circuit of claim 17, wherein:
the first electrode (#320a, Figure 5, capacitor plate) further comprises a plurality of first metal lines disposed at the same first level as the first metal line (Figures 5, 6, and 7, [0066], #320a comprises a plurality of #306c conductive members including and at the same level as the leftmost) and a plurality of second metal lines disposed at the same second level as the second metal line (Figures 5, 6, and 7, [0066], #320a comprises a plurality of #306e conductive members including and at the same level as the leftmost),
the second electrode (#320b, Figure 5, capacitor plate) further comprises a plurality of third metal lines disposed at a same third level as the third metal line (Figures 5, 6, and 7, [0066], #320b comprises a plurality of #306c conductive members including and at the same level as the leftmost) and a plurality of fourth metal lines disposed at a same fourth level as the fourth metal line (Figures 5, 6, and 7, [0066], #320a comprises a plurality of #306e conductive members including and at the same level as the leftmost),
the plurality of first metal lines and the plurality of third metal lines are alternately disposed in the second horizontal direction (Figure 5, 6, and 7, [0066], #306c conductive members of #320a and #320b are alternately disposed along the left-right second horizontal direction), and
the plurality of second metal lines and the plurality of fourth metal lines are alternately disposed in the second horizontal direction (Figure 5, 6, and 7, [0066], #306e conductive members of #320a and #320b are alternately disposed along the left-right second horizontal direction).
Claim(s) 5-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0282753 A1; Kim, Sun-Oo; 11/2012; (“Kim”) as applied to claim 1 above, and further in view of US 2021/0005706 A1; Lu et al.; 01/2021; (“Lu”).
Regarding Claim 5. Kim discloses The integrated circuit of claim 1.
Kim does not disclose that the first patterned side surface comprises a first saw pattern extending in the vertical direction, and the second patterned side surface comprises a second saw pattern extending in the vertical direction.
However, Lu teaches an energy storage device which may be a capacitor ([0003]) formed by alternately disposing conductive layers and dielectric layers in a trench structure (#120, [0066], Figure 4) wherein the trench structure may have a saw structure (Figures 3a and 4) such that the resulting conductive plates of the capacitor would have a patterned outer surface comprising a first saw pattern and a second saw pattern extending in the vertical direction (Figure 4). Lu also teaches that the trench pattern structure may be comprised of protruding polygonal squares (Figure 3c)
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to one of ordinary skill in the art to consider replacing the polygonal square pattern in the conductive plates of Kim with the saw pattern structure of Lu, which teaches the two different structures as alternative embodiments (Figure 3 of Lu) since both shapes may increase the surface area of the trench structure without increasing the footprint ([0005] of Lu) which allows for an increase in energy density ([0003] of Lu). This is interpreted by the examiner as an obvious change in shape (see MPEP 2144.04.IV.B) since both configurations are known and provide the same result.
Regarding Claim 6. Kim in view of Lu discloses The integrated circuit of claim 5, wherein:
the first patterned side surface faces the second patterned side surface (Figures 5 and 6 of Kim, sidewalls of the patterned surfaces of electrodes face one another; Figures 3 and 4 of Lu, patterned sidewalls of the respective trenches where the conductive plates are formed face one another),
the first saw pattern of the first patterned side surface has been formed to be engaged with the second saw pattern of the second patterned side surface (Figures 3 and 4 of Lu, patterned saw pattern sidewalls of the respective trenches where the conductive plates are formed are structured to be engaged with one another), and
a first height of the first saw pattern matches a second height of the second saw pattern (Figure 5 of Kim, sidewalls of the patterned surfaces of electrodes on each respective level extend to the same vertical height; Figure 4 of Lu, patterned sidewalls of the respective trenches where the conductive plates are formed all extend to the same vertical height).
Regarding Claim 7. Kim discloses The integrated circuit of claim 1, wherein:
the first patterned side surface comprises a first polygonal pattern (Figure 6, right side surface of leftmost #306e of #320a is patterned to have alternating extent protruding polygonal square shapes) extending in the vertical direction ([0062] and Figure 5, the distance between the plates d5 is maintained along the vertical direction such that the pattern necessarily extends in the vertical direction),
the second patterned side surface comprises a second polygonal pattern (Figure 6, left side surface of leftmost #306e of #320b is patterned to have alternating extent protruding polygonal square shapes) extending in the vertical direction ([0062] and Figure 5, the distance between the plates d5 is maintained along the vertical direction such that the pattern necessarily extends in the vertical direction).
Kim does not disclose that the first polygonal pattern and the second polygonal pattern have a different number of sides.
However, Lu teaches an energy storage device which may be a capacitor ([0003]) formed by alternately disposing conductive layers and dielectric layers in a trench structure (#120, [0066], Figure 4) wherein the trench structure may have a saw structure (Figures 3a and 4), a hemisphere structure (Figure 3b), and polygonal squares (Figure 3c). Lu further discloses in [0060] and claim 4 that the patterns of adjacent structures may be different from one another, i.e. have a different number of sides.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to one of ordinary skill in the art to consider replacing one of the polygonal square patterns in the conductive plates of Kim with the saw or hemisphere pattern structure of Lu such that the two patterns have different shapes and/or numbers of sides since both shapes may increase the surface area of the trench structure without increasing the footprint ([0005] of Lu) which allows for an increase in energy density ([0003] of Lu). This is interpreted by the examiner as an obvious change in shape (see MPEP 2144.04.IV.B) since the various configurations are known and provide the same result.
Regarding Claim 8. Kim in view of Lu discloses The integrated circuit of claim 7, wherein:
the first patterned side surface faces the second patterned side surface (Figures 5 and 6 of Kim, sidewalls of the patterned surfaces of electrodes face one another; Figures 3 and 4 of Lu, patterned sidewalls of the respective trenches where the conductive plates are formed face one another), and
the first polygonal pattern of the first patterned side surface has been formed to be engaged with the second polygonal pattern of the second patterned side surface (Kim, Figure 6, the patterned sidewalls are structured to at least partially engage with one another of adjacent sidewalls, i.e. may partially fit into one another; Lu, Figures 3 and 4, all of the patterns are structured to be engaged with one another).
Regarding Claim 9. Kim discloses The integrated circuit of claim 1.
Kim does not disclose that the first patterned side surface comprises a first trapezoidal pattern extending in the vertical direction, and the second patterned side surface comprises a second trapezoidal pattern extending in the vertical direction.
However, Lu teaches an energy storage device which may be a capacitor ([0003]) formed by alternately disposing conductive layers and dielectric layers in a trench structure (#120, [0066], Figure 4) wherein the trench structure may have a rounded trapezoidal structure extending in a vertical direction (Figures 4 and 8) such that the resulting conductive plates of the capacitor would have a patterned outer surface comprising a first rounded trapezoidal pattern and a second rounded trapezoidal pattern extending in the vertical direction (Figure 4). Lu also teaches that the trench pattern structure may be comprised of protruding polygonal squares (Figure 3c)
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to one of ordinary skill in the art to consider replacing the polygonal square pattern in the conductive plates of Kim with the rounded trapezoidal pattern structure of Lu¸ which teaches the two different structures as alternative embodiments (Figures 4 and 8 of Lu) since both shapes may increase the surface area of the trench structure without increasing the footprint ([0005] of Lu) which allows for an increase in energy density ([0003] of Lu). This is interpreted by the examiner as an obvious change in shape (see MPEP 2144.04.IV.B) since both configurations are known and provide the same result.
Regarding Claim 10. Kim discloses The integrated circuit of claim 1.
Kim does not disclose that the first patterned side surface comprises a first semicircular pattern extending in the vertical direction, and the second patterned side surface comprises a second semicircular pattern extending in the vertical direction.
However, Lu teaches an energy storage device which may be a capacitor ([0003]) formed by alternately disposing conductive layers and dielectric layers in a trench structure (#120, [0066], Figure 4) wherein the trench structure may have a semicircular pattern (Figures 3b and 4) such that the resulting conductive plates of the capacitor would have a patterned outer surface comprising a first semicircular pattern and a second semicircular pattern extending in the vertical direction (Figure 4). Lu also teaches that the trench pattern structure may be comprised of protruding polygonal squares (Figure 3c)
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to one of ordinary skill in the art to consider replacing the polygonal square pattern in the conductive plates of Kim with the semicircular pattern structure of Lu¸ which teaches the two different structures as alternative embodiments (Figure 3 of Lu) since both shapes may increase the surface area of the trench structure without increasing the footprint ([0005] of Lu) which allows for an increase in energy density ([0003] of Lu). This is interpreted by the examiner as an obvious change in shape (see MPEP 2144.04.IV.B) since both configurations are known and provide the same result.
Regarding Claim 11. Kim in view of Lu discloses The integrated circuit of claim 10, wherein
the first patterned side surface faces the second patterned side surface (Figures 5 and 6 of Kim, sidewalls of the patterned surfaces of electrodes face one another; Figures 3 and 4 of Lu, patterned sidewalls of the respective trenches where the conductive plates are formed face one another),
the first semicircular pattern of the first patterned side surface has been formed to be engaged with the second semicircular pattern of the second patterned side surface (Figures 3 and 4 of Lu, patterned semicircular pattern sidewalls of the respective trenches where the conductive plates are formed are structured to be engaged with one another), and
a first diameter of the first semicircular pattern matches a second diameter of the second semicircular pattern (Figures 3 and 4 of Lu, patterned semicircular pattern sidewalls of the respective trenches where the conductive plates are formed match one another to have matching diameters in order to be engaged).
Regarding Claim 12. Kim discloses The integrated circuit of claim 1.
Kim does not disclose that the first patterned side surface comprises at least one of a first semielliptical pattern and a wave pattern extending in the vertical direction, and the second patterned side surface comprises at least one of a second semielliptical pattern and a second wave pattern extending in the vertical direction.
However, Lu teaches an energy storage device which may be a capacitor ([0003]) formed by alternately disposing conductive layers and dielectric layers in a trench structure (#120, [0066], Figure 4) wherein the trench structure may have a wave structure (Figures 3a and 4) or a semielliptical pattern (Figures 3b and 4, noting here that a circle is a type of ellipse and [0061] of Lu states “the first pattern may also be other regular or irregular patterns, which is not limited in the present disclosure”) such that the resulting conductive plates of the capacitor would have a patterned outer surface comprising a first saw/elliptical pattern and a second saw/elliptical pattern extending in the vertical direction (Figure 4). Lu also teaches that the trench pattern structure may be comprised of protruding polygonal squares (Figure 3c)
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to one of ordinary skill in the art to consider replacing the polygonal square pattern in the conductive plates of Kim with the saw pattern structure or semielliptical pattern structure of Lu¸ which teaches the three different structures as alternative embodiments (Figure 3 of Lu) since each shape may increase the surface area of the trench structure without increasing the footprint ([0005] of Lu) which allows for an increase in energy density ([0003] of Lu). This is interpreted by the examiner as an obvious change in shape (see MPEP 2144.04.IV.B) since all configurations are known and provide the same result.
Regarding Claim 13. Kim in view of Lu discloses The integrated circuit of claim 12, wherein
the first patterned side surface faces the second patterned side surface (Figures 5 and 6 of Kim, sidewalls of the patterned surfaces of electrodes face one another; Figures 3 and 4 of Lu, patterned sidewalls of the respective trenches where the conductive plates are formed face one another),
the first patterned side surface comprises the first semielliptical pattern, the second patterned side surface comprises the second semielliptical pattern (Lu, Figure 3b, the trench structure may have a semielliptical pattern, Figures 3b and 4, noting here that a circle is a type of ellipse and [0061] of Lu states “the first pattern may also be other regular or irregular patterns, which is not limited in the present disclosure”),
the first semielliptical pattern of the first patterned side surface has been formed to be engaged with the second semielliptical pattern of the second patterned side surface (Figures 3 and 4 of Lu, patterned semielliptical pattern sidewalls of the respective trenches where the conductive plates are formed are structured to be engaged with one another), and
a first diameter in a long direction of the first semielliptical pattern matches a second diameter in the long direction of the second semielliptical pattern (Figures 3 and 4 of Lu, patterned semielliptical pattern sidewalls of the respective trenches where the conductive plates are formed match one another such that equivalent directions, such as the long direction, will share the same diameter).
Claim(s) 23 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0186992 A1; Guo, Xiaojiang; 06/2023; (“Guo”) in view of US 2012/0282753 A1; Kim, Sun-Oo; 11/2012; (“Kim”).
Regarding Claim 23. Guo discloses A non-volatile memory device (Figures 7A and 7B, memory device which may be non-volatile flash memory according to [0003] and [0043), comprising:
a memory cell array (#501, Figure 7A, memory cell array) comprising a plurality of memory cells (#506, [0042], plurality of memory cells) respectively coupled to a plurality of word lines ([0051], memory cells are electrically coupled to plurality of word lines #518); and
a voltage generator (#710, Figure 7B, voltage generator as part of the control logic in Figure 7A) comprising a charge pump that comprises at least one capacitor configured to generate voltages applied to the plurality of word lines ([0057], voltage generator may include capacitors for controlling voltage output of the logic circuitry which is applied to the memory cell array word line drivers #708 in Figure 7B).
Guo does not disclose that the at least one capacitor comprises a first electrode, a dielectric layer, and a second electrode disposed on a same layer above a substrate,
wherein the first electrode comprises at least one first metal line disposed above the substrate, having a first patterned side surface extending in a vertical direction, extending in a first horizontal direction, and configured to receive a first voltage, and
wherein the second electrode comprises at least one second metal line disposed above the substrate, having a second patterned side surface extending in the vertical direction, extending in the first horizontal direction, laterally spaced apart from the at least one first metal line in a second horizontal direction, and configured to receive a second voltage, the second voltage being different from the first voltage,
wherein the dielectric layer is laterally disposed between the first patterned side surface and the second patterned side surface that face each other,
wherein each of the first patterned side surface and the second patterned side surface comprises a plurality of protrusions and recesses arranged alternately in the first horizontal direction,
wherein a distance between the first patterned side surface and the second patterned side surface comprises:
a maximum distance between a top portion of a protrusion of the second patterned side surface and a bottom portion of a recess of the first patterned side surface in the second horizontal direction, and
a minimum distance between the top portion of the protrusion of the second patterned side surface and a top portion of a protrusion of the first patterned side surface.
However, Kim teaches a capacitor (#320a and #320b, Figure 5, capacitor plates, noting here that [0004] provides that the capacitors may be used in memory devices) comprising a first electrode (#320a, Figure 5, capacitor plate), a dielectric layer (#304e, Figures 5 and 6, dielectric materials), and a second electrode (#320b, Figure 5, capacitor plate) disposed on a same layer above the substrate (Figures 5 and 6, #304e is disposed between #320a and #320b on the same layer above #302),
wherein the first electrode comprises at least one first metal line disposed above the substrate (leftmost #306e of #320a, Figures 5 and 6, conductive member disposed above #302) having a first patterned side surface extending in the vertical direction (Figure 6, right side surface of leftmost #306e of #320a is patterned in the vertical direction in Figure 5), extending in a first horizontal direction (Figure 6, each #306e extends in a first up/down horizontal direction in the top view), and configured to receive a first voltage ([0004], capacitor may have an applied voltage), and
wherein the second electrode (#320b, Figure 5) comprises at least one second metal line disposed above the substrate (leftmost #306e of #320b, Figures 5 and 6, conductive member disposed above #302) having a second patterned side surface extending in the vertical direction (Figure 6, left side surface of leftmost #306e of #320b is patterned and extends in the vertical direction of Figure 5), extending in the first horizontal direction (Figure 6, each #306e extends in a first up/down horizontal direction in the top view), laterally spaced apart from the at least one first metal line in a second horizontal direction (Figures 5 and 6, each #306e is laterally spaced apart from adjacent #306e structures in a left-right second horizontal direction by at least the distance d5), and configured to receive a second voltage ([0004], capacitor may have an applied voltage), the second voltage being different from the first voltage ([0004], the function of a capacitor is to store charge through voltage difference in adjacent electrode plates),
wherein the dielectric layer is laterally disposed between the first patterned side surface and the second patterned side surface that face each other (Figures 5 and 6, #304e is laterally disposed between the patterned side surfaces of the #306e lines),
wherein each of the first patterned side surface and the second patterned side surface comprises a plurality of protrusions and recesses arranged alternately in the first horizontal direction (Figure 6, left and right side surfaces of #306ce lines of #320a and #320b are patterned to have alternating extent protruding square shapes and recesses therebetween in the first up/down horizontal direction in the top view).
Since Guo is silent regarding the structure of the capacitor used as a charge pump in the voltage generator, this would motivate one of ordinary skill to seek out teachings such as Kim in order to practice the invention of primary. It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention, to consider utilizing the capacitor structure from Kim for the capacitor in Guo since “connecting a plurality of plates 320a and 320b together in parallel as shown in an interwoven or interleaved pattern may result in a capacitor with increased capacitance” as taught by Kim in [0063].
Guo in view of Kim do not explicitly disclose that a distance between the first patterned side surface and the second patterned side surface comprises: a maximum distance between a top portion of a protrusion of the second patterned side surface and a bottom portion of a recess of the first patterned side surface in the second horizontal direction, and a minimum distance between the top portion of the protrusion of the second patterned side surface and a top portion of a protrusion of the first patterned side surface.
However, Kim does teach in [0042]-[0044] and [0062] that the dimensions of the device including the widths of the pattern surfaces (d1, d3, and d4) along with the spacing between the protrusions and recesses of adjacent patterned surfaces (d5) may be set as necessary based on minimum feature sizes and the required capacitance of the device (see [0004]) given the available space (see [0073]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider setting the spacing of the distance between the plates and the dimensions of the patterned surface such that a distance between the first patterned side surface and the second patterned side surface comprises: a maximum distance between a top portion of a protrusion of the second patterned side surface and a bottom portion of a recess of the first patterned side surface in the second horizontal direction, and a minimum distance between the top portion of the protrusion of the second patterned side surface and a top portion of a protrusion of the first patterned side surface as an obvious routine optimization (see MPEP 2144.05.II.B). It is well understood by the teachings of Kim that the spacings and dimensions of and between the patterned surfaces are a matter of optimization for the user of the device to achieve a desired capacitance given an available amount of space in the device (see [0004], [0063], and [0073]). This is in agreement with the instant applications descriptions of these spacings (see [0055] and [0057] of the instant application) as being “changed in various ways according to embodiments and/or design constraints”.
Regarding Claim 24. Guo in view of Kim discloses The non-volatile memory device of claim 23, wherein
the first patterned side surface comprises a first pattern (Kim, Figure 6, right side surface of leftmost #306e of #320a is patterned to have alternating extent protruding square shapes) extending in a vertical direction (Kim, [0062] and Figure 5, the distance between the plates d5 is maintained along the vertical direction such that the pattern necessarily extends in the vertical direction),
the second patterned side surface comprises a second pattern (Kim, Figure 6, left side surface of leftmost #306e of #320b is patterned to have alternating extent protruding square shapes) extending in the vertical direction (Kim, [0062] and Figure 5, the distance between the plates d5 is maintained along the vertical direction such that the pattern necessarily extends in the vertical direction),
the first patterned side surface faces the second patterned side surface (Kim, Figure 6, right side surface of leftmost #306e of #320a faces left side surface of leftmost #306e of #320b), and
the first pattern and the second pattern have an engagement structure (Kim, Figure 6, the patterned sidewalls are structured to at least partially engage with one another of adjacent sidewalls, i.e. may partially fit into one another).
Response to Arguments/Amendments
Applicant’s amendments to claims 1, 17, and 23 along with corresponding arguments, see pages 13-20 of the remarks, filed 06/21/2026, with respect to the 35 U.S.C. 102 and 103 rejections of the claims and their respective dependent claims have been fully considered but have only been found partially persuasive.
Applicant is correct that the cited prior art does not explicitly disclose the amended claim limitations. For this reason, all 35 U.S.C. 102 rejections have been withdrawn. However, the amended limitations have resulted in a 35 U.S.C. 112(a) rejection for new matter for the reasons described above. In particular, the examiner believes the limitations of amended claims 1, 17, and 23 requiring “a distance between the first patterned side surface and the second patterned side surface comprises: a maximum distance between a top portion of a protrusion of the second patterned side surface and a bottom portion of a recess of the first patterned side surface in the second horizontal direction, and a minimum distance between the top portion of the protrusion of the second patterned side surface and a top portion of a protrusion of the first patterned side surface” is new matter as it does not appear to be supported by the originally filed specification.
Additionally, it is the examiner’s opinion that while the prior art does not explicitly teach the amended limitations, it does appear to render the limitations obvious. Kim teaches in [0042]-[0044] and [0062] that the dimensions of the device including the widths of the pattern surfaces (d1, d3, and d4) along with the spacing between the protrusions and recesses of adjacent patterned surfaces (d5) may be set as necessary based on minimum feature sizes and the required capacitance of the device (see [0004]) given the available space (see [0073]). As a result, the amended limitations are interpreted by the examiner as an obvious routine optimization (see MPEP 2144.05.II.B). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider setting the spacing of the distance between the plates and the dimensions of the patterned surface to meet the required maximum/minimum distances between points. It is well understood by the teachings of Kim that the spacings and dimensions of and between the patterned surfaces are a matter of optimization for the user of the device to achieve a desired capacitance given an available amount of space in the device (see [0004], [0063], and [0073]). This is in agreement with the instant applications descriptions of these spacings (see [0055] and [0057] of the instant application) as being “changed in various ways according to embodiments and/or design constraints”. Therefore, it is the examiner’s position that the amended claims remain obvious in view of the prior art.
Claim(s) 1-4, 14-17, and 21 stand(s) rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0282753 A1; Kim, Sun-Oo; 11/2012; (“Kim”).
Claim(s) 5-13 stand(s) rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0282753 A1; Kim, Sun-Oo; 11/2012; (“Kim”) as applied to claim 1 above, and further in view of US 2021/0005706 A1; Lu et al.; 01/2021; (“Lu”).
Claim(s) 23 and 24 stand(s) rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0186992 A1; Guo, Xiaojiang; 06/2023; (“Guo”) in view of US 2012/0282753 A1; Kim, Sun-Oo; 11/2012; (“Kim”).
Conclusion
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/TYLER J WIEGAND/Examiner, Art Unit 2812
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