DETAILED ACTION
This action is responsive to the amendment and remarks received on 03/10/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in REPUBLIC OF KOREA on 10/27/2022.
Claim Interpretation
At least claims 12 and 14 recite limitations wherein a structure “comprises at least one of . . .” and the phrasing concludes with the word “and” before the final option in the list. A complete example from claim 14 is “the first patterned side surface comprises at least one of a saw pattern, a polygonal pattern, a semicircular pattern, and a semielliptical pattern”. This phrasing has been interpreted to mean the structure may comprise any one of these elements individually and read on the limitation, not that the structure must comprise at least one of each and every one of them. This is in accordance with [0038] of the instant application’s specification stating “each of such phrases as "A or B," "at least one of A and B," "at least one of A or B," "A, B, or C," "at least one of A, B, and C," and "at least one of A, B, or C," may include any one of, or all possible combinations of the items enumerated together in a corresponding one of the phrases”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 7, 8, 14-17, and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2012/0282753 A1; Kim, Sun-Oo; 11/2012; (“Kim”).
Regarding Claim 1. Kim discloses An integrated circuit (Figures 5 and 6, semiconductor capacitor structure #300, Figure 5 is a side view, which may part of an integrated circuit according to [0080], the figure 6 embodiment of the structure wherein capacitor plates are interleaved ([0058]-[0066]) is utilized with the stacked alternating electrodes and vias of Fig. 5 according to [0066]), comprising:
a substrate (#302, Figure 5, equivalent to #102 in Figure 1 described as a workpiece which may be a semiconductor substrate according to [0025]); and
a capacitor structure (#320a and #320b, Figure 5, capacitor plates), disposed above the substrate in a vertical direction (Figure 5, #320a/b are disposed above #302 in a vertical direction), comprising:
a first electrode (#320a, Figure 5, capacitor plate) configured to receive a first voltage ([0004], capacitor may have an applied voltage) and comprising at least one first metal line (leftmost #306e of #320a, Figures 5 and 6, conductive member) having a first patterned side surface (Figure 6, right side surface of leftmost #306e of #320a is patterned), the at least one first metal line extending in a first horizontal direction (Figure 6, each #306e extends in a first up/down horizontal direction in the top view);
a second electrode (#320b, Figure 5, capacitor plate) configured to receive a second voltage ([0004], capacitor may have an applied voltage) and comprising at least one second metal line (leftmost #306e of #320b, Figures 5 and 6, conductive member) having a second patterned side surface (Figure 6, left side surface of leftmost #306e of #320b is patterned), the at least one second metal line extending in the first horizontal direction (Figure 6, each #306e extends in a first up/down horizontal direction in the top view); and
a dielectric layer (#304e, Figures 5 and 6, dielectric materials) disposed between the first electrode and the second electrode (Figures 5 and 6, #304e is disposed between #320a and #320b),
the first electrode, the second electrode, and the dielectric layer being disposed on a same layer (Figure 5, #320a, #320b, and #304e are all disposed on the same topmost layer),
the at least one second metal line being spaced apart from the at least one first metal line in a second horizontal direction (Figures 5 and 6, each #306e is spaced apart from adjacent #306e structures in a left-right second horizontal direction by at least the distance d5),
the at least one first metal line having a first width in the second horizontal direction (Figures 5 and 6, leftmost #306e of #320a has a first width in the left-right second horizontal direction of the narrower portions between adjacent thicker portions, labeled as d1 in Figure 3), and
the at least one second metal line having a second width in the second horizontal direction (Figures 5 and 6, leftmost #306e of #320b has a width in the left-right second horizontal direction of the wider or thicker portions between adjacent narrow portions, labeled as d3 in Figure 3) different from the first width (Figures 3, 5, and 6, the widths of the wider and narrower portions, i.e. d3 and d1, are different from one another).
Regarding Claim 2. Kim discloses The integrated circuit of claim 1, wherein a first level of a first upper surface of the at least one first metal line matches a second level of a second upper surface of the at least one second metal line (Figure 5, each #306e shares a level of its upper surface with level of the upper surface of each other #306e).
Regarding Claim 3. Kim discloses The integrated circuit of claim 1, wherein:
the first patterned side surface comprises a first pattern (Figure 6, right side surface of leftmost #306e of #320a is patterned to have alternating extent protruding square shapes) extending in the vertical direction ([0062] and Figure 5, the distance between the plates d5 is maintained along the vertical direction such that the pattern necessarily extends in the vertical direction),
the second patterned side surface comprises a second pattern (Figure 6, left side surface of leftmost #306e of #320b is patterned to have alternating extent protruding square shapes) extending in the vertical direction ([0062] and Figure 5, the distance between the plates d5 is maintained along the vertical direction such that the pattern necessarily extends in the vertical direction),
the first patterned side surface faces the second patterned side surface (Figure 6, right side surface of leftmost #306e of #320a faces left side surface of leftmost #306e of #320b), and
the first pattern and the second pattern have an engagement structure (Figure 6, the patterned sidewalls are structured to at least partially engage with one another of adjacent sidewalls, i.e. may partially fit into one another).
Regarding Claim 4. Kim discloses The integrated circuit of claim 3, wherein:
the first patterned side surface and the second patterned side surface are spaced apart by a first space in the second horizontal direction (Figure 6, right side surface of leftmost #306e of #320a is spaced apart from left side surface of leftmost #306e of #320b by a first space d5 in the left-right second horizontal direction), and
the first space comprises at least a portion of the dielectric layer (Figures 5 and 6, the gap d5 comprises at least a portion of #304e).
Regarding Claim 7. Kim discloses The integrated circuit of claim 1, wherein:
the first patterned side surface comprises a first polygonal pattern (Figure 6, right side surface of leftmost #306e of #320a is patterned to have alternating extent protruding polygonal square shapes) extending in the vertical direction ([0062] and Figure 5, the distance between the plates d5 is maintained along the vertical direction such that the pattern necessarily extends in the vertical direction), and
the second patterned side surface comprises a second polygonal pattern (Figure 6, left side surface of leftmost #306e of #320b is patterned to have alternating extent protruding polygonal square shapes) extending in the vertical direction ([0062] and Figure 5, the distance between the plates d5 is maintained along the vertical direction such that the pattern necessarily extends in the vertical direction).
Regarding Claim 8. Kim discloses The integrated circuit of claim 7, wherein:
the first patterned side surface faces the second patterned side surface (Figure 6, right side surface of leftmost #306e of #320a faces left side surface of leftmost #306e of #320b), and
the first polygonal pattern of the first patterned side surface has been formed to be engaged with the second polygonal pattern of the second patterned side surface (Figure 6, the patterned sidewalls are structured to at least partially engage with one another of adjacent sidewalls, i.e. may partially fit into one another).
Regarding Claim 14. Kim discloses The integrated circuit of claim 1, wherein:
the first patterned side surface comprises at least one of a saw pattern, a polygonal pattern, a semicircular pattern, and a semielliptical pattern (Figure 6, right side surface of leftmost #306e of #320a is patterned to have alternating extent protruding polygonal square shapes), and
the second patterned side surface comprises at least one of the saw pattern, the polygonal pattern, the semicircular pattern, and the semielliptical pattern (Figure 6, left side surface of leftmost #306e of #320b is patterned to have alternating extent protruding polygonal square shapes).
Regarding Claim 15. Kim discloses The integrated circuit of claim 1, wherein:
the first electrode (#320a, Figure 5, capacitor plate) comprises a plurality of first metal lines comprising the at least one first metal line (Figure 6, #320a comprises a plurality of #306e conductive members including the leftmost),
the second electrode (#320b, Figure 5, capacitor plate) comprises a plurality of second metal lines comprising the at least one second metal line (Figure 6, #320b comprises a plurality of #306e conductive members including the leftmost), and
the plurality of first metal lines and the plurality of second metal lines are alternately disposed in the second horizontal direction (Figure 6, #306e conductive members of #320a and #320b are alternately disposed along the left-right second horizontal direction).
Regarding Claim 16. Kim discloses The integrated circuit of claim 15, wherein:
the first electrode (#320a, Figure 5, capacitor plate) further comprises a first conductive line (#312a, Figure 6, conductive line), extending in the second horizontal direction, coupled to each of the plurality of first metal lines (Figure 6, #312a extends in the left-right second horizontal direction and is electrically coupled to each #306e of #320a), and
the second electrode (#320b, Figure 5, capacitor plate) further comprises a second conductive line (#312b, Figure 6, conductive line), extending in the second horizontal direction, coupled to each of the plurality of second metal lines (Figure 6, #312b extends in the left-right second horizontal direction and is electrically coupled to each #306e of #320b).
Regarding Claim 17. Kim discloses An integrated circuit (Figures 5 and 6, semiconductor capacitor structure #300, Figure 5 is a side view, which may part of an integrated circuit according to [0080], the figure 6 embodiment of the structure wherein capacitor plates are interleaved ([0058]-[0066]) is utilized with the stacked alternating electrodes and vias of Fig. 5 according to [0066]), comprising:
a substrate (#302, Figure 5, equivalent to #102 in Figure 1 described as a workpiece which may be a semiconductor substrate according to [0025]); and
a capacitor structure (#320a and #320b, Figure 5, capacitor plates), disposed above the substrate in a vertical direction (Figure 5, #320a/b are disposed above #302 in a vertical direction), comprising:
a first electrode (#320a, Figure 5, capacitor plate) configured to receive a first voltage ([0004], capacitor may have an applied voltage),
a second electrode (#320b, Figure 5, capacitor plate) configured to receive a second voltage ([0004], capacitor may have an applied voltage), the first voltage being different from the second voltage ([0004], the function of a capacitor is to store charge through voltage difference in adjacent electrode plates), and
a dielectric layer (#304e, Figures 5 and 6, dielectric materials) disposed between the first electrode and the second electrode (Figures 5 and 6, #304e is disposed between #320a and #320b),
wherein the first electrode (#320a, Figure 5) comprises:
a first metal line (leftmost #306c of #320a, Figures 5 and 6, conductive member) extending in a first horizontal direction (Figures 5 and 6, each #306c extends in a first up/down horizontal direction in the top view noting that [0066] describes that Figure 6 also has the staggered structure in the vertical direction like Fig. 5); and
a second metal line (leftmost #306e of #320a, Figures 5 and 6, conductive member) extending in the first horizontal direction (Figures 5 and 6, each #306e extends in a first up/down horizontal direction in the top view), disposed above the first metal line in the vertical direction (Figure 5, #306e members are above #306c members), and coupled to the first metal line (Figure 5, #306e members are coupled to underlying #306c members by vias #308d),
wherein the second electrode (#320b, Figure 5) comprises:
a third metal line (leftmost #306c of #320b, Figures 5 and 6, conductive member) extending in the first horizontal direction (Figures 5 and 6, each #306c extends in a first up/down horizontal direction in the top view noting that [0066] describes that Figure 6 also has the staggered structure in the vertical direction like Fig. 5), spaced apart from the first metal line in a second horizontal direction (Figure 5, #306c members of #320a/b are spaced apart from one another in a second left-right horizontal direction), and disposed at a same first level as the first metal line (Figure 6, #306c members are all disposed in the M2 metal layer); and
a fourth metal line (leftmost #306e of #320b, Figures 5 and 6, conductive member) extending in the first horizontal direction (Figures 5 and 6, each #306e extends in a first up/down horizontal direction in the top view), spaced apart from the second metal line in the second horizontal direction (Figure 5, #306e members of #320a/b are spaced apart from one another in the second left-right horizontal direction), disposed at a same second level as the second metal line (Figure 6, #306e members are all disposed in the MX metal layer), and coupled to the third metal line (Figure 5, #306e members are coupled to underlying #306c members by vias #308d),
wherein side surfaces of each of the first metal line, the second metal line, the third metal line, and the fourth metal line comprise respective patterns extending in the vertical direction (Figure 6, side surfaces of all portions of #306e and #306c members are patterned, this is also observed in Figure 7 and described in [0067]),
wherein the first metal line has a first width in the second horizontal direction (Figures 5 and 6, leftmost #306e of #320a has a first width in the left-right second horizontal direction of the narrower portions between adjacent thicker portions, labeled as d1 in Figure 3), and
wherein the second metal line has a second width in the second horizontal direction (Figures 5 and 6, leftmost #306e of #320b has a width in the left-right second horizontal direction of the wider or thicker portions between adjacent narrow portions, labeled as d3 in Figure 3) different from the first width (Figures 3, 5, and 6, the widths of the wider and narrower portions, i.e. d3 and d1, are different from one another).
Regarding Claim 21. Kim discloses The integrated circuit of claim 17, wherein:
the first electrode (#320a, Figure 5, capacitor plate) further comprises a plurality of first metal lines disposed at the same first level as the first metal line (Figures 5, 6, and 7, [0066], #320a comprises a plurality of #306c conductive members including and at the same level as the leftmost) and a plurality of second metal lines disposed at the same second level as the second metal line (Figures 5, 6, and 7, [0066], #320a comprises a plurality of #306e conductive members including and at the same level as the leftmost),
the second electrode (#320b, Figure 5, capacitor plate) further comprises a plurality of third metal lines disposed at a same third level as the third metal line (Figures 5, 6, and 7, [0066], #320b comprises a plurality of #306c conductive members including and at the same level as the leftmost) and a plurality of fourth metal lines disposed at a same fourth level as the fourth metal line (Figures 5, 6, and 7, [0066], #320a comprises a plurality of #306e conductive members including and at the same level as the leftmost),
the plurality of first metal lines and the plurality of third metal lines are alternately disposed in the second horizontal direction (Figure 5, 6, and 7, [0066], #306c conductive members of #320a and #320b are alternately disposed along the left-right second horizontal direction), and
the plurality of second metal lines and the plurality of fourth metal lines are alternately disposed in the second horizontal direction (Figure 5, 6, and 7, [0066], #306e conductive members of #320a and #320b are alternately disposed along the left-right second horizontal direction).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 6, and 9-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0282753 A1; Kim, Sun-Oo; 11/2012; (“Kim”) as applied to claims 1 and 8 above, and further in view of US 2021/0005706 A1; Lu et al.; 01/2021; (“Lu”).
Regarding Claim 5. Kim discloses The integrated circuit of claim 1.
Kim does not disclose that the first patterned side surface comprises a first saw pattern extending in the vertical direction, and the second patterned side surface comprises a second saw pattern extending in the vertical direction.
However, Lu teaches an energy storage device which may be a capacitor ([0003]) formed by alternately disposing conductive layers and dielectric layers in a trench structure (#120, [0066], Figure 4) wherein the trench structure may have a saw structure (Figures 3a and 4) such that the resulting conductive plates of the capacitor would have a patterned outer surface comprising a first saw pattern and a second saw pattern extending in the vertical direction (Figure 4). Lu also teaches that the trench pattern structure may be comprised of protruding polygonal squares (Figure 3c)
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to one of ordinary skill in the art to consider replacing the polygonal square pattern in the conductive plates of Kim with the saw pattern structure of Lu¸ which teaches the two different structures as alternative embodiments (Figure 3 of Lu) since both shapes may increase the surface area of the trench structure without increasing the footprint ([0005] of Lu) which allows for an increase in energy density ([0003] of Lu). This is interpreted by the examiner as an obvious change in shape (see MPEP 2144.04.IV.B) since both configurations are known and provide the same result.
Regarding Claim 6. Kim in view of Lu discloses The integrated circuit of claim 5, wherein:
the first patterned side surface faces the second patterned side surface (Figures 5 and 6 of Kim, sidewalls of the patterned surfaces of electrodes face one another; Figures 3 and 4 of Lu, patterned sidewalls of the respective trenches where the conductive plates are formed face one another),
the first saw pattern of the first patterned side surface has been formed to be engaged with the second saw pattern of the second patterned side surface (Figures 3 and 4 of Lu, patterned saw pattern sidewalls of the respective trenches where the conductive plates are formed are structured to be engaged with one another), and
a first height of the first saw pattern matches a second height of the second saw pattern (Figure 5 of Kim, sidewalls of the patterned surfaces of electrodes on each respective level extend to the same vertical height; Figure 4 of Lu, patterned sidewalls of the respective trenches where the conductive plates are formed all extend to the same vertical height).
Regarding Claim 9. Kim discloses The integrated circuit of claim 8.
Kim does not disclose that the first polygonal pattern comprises a first trapezoidal pattern, and the second polygonal pattern comprises a second trapezoidal pattern.
However, Lu teaches an energy storage device which may be a capacitor ([0003]) formed by alternately disposing conductive layers and dielectric layers in a trench structure (#120, [0066], Figure 4) wherein the trench structure may have a rounded trapezoidal structure (Figures 4 and 8) such that the resulting conductive plates of the capacitor would have a patterned outer surface comprising a first rounded trapezoidal pattern and a second rounded trapezoidal pattern extending in the vertical direction (Figure 4). Lu also teaches that the trench pattern structure may be comprised of protruding polygonal squares (Figure 3c)
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to one of ordinary skill in the art to consider replacing the polygonal square pattern in the conductive plates of Kim with the rounded trapezoidal pattern structure of Lu¸ which teaches the two different structures as alternative embodiments (Figures 4 and 8 of Lu) since both shapes may increase the surface area of the trench structure without increasing the footprint ([0005] of Lu) which allows for an increase in energy density ([0003] of Lu). This is interpreted by the examiner as an obvious change in shape (see MPEP 2144.04.IV.B) since both configurations are known and provide the same result.
Regarding Claim 10. Kim discloses The integrated circuit of claim 1.
Kim does not disclose that the first patterned side surface comprises a first semicircular pattern extending in the vertical direction, and the second patterned side surface comprises a second semicircular pattern extending in the vertical direction.
However, Lu teaches an energy storage device which may be a capacitor ([0003]) formed by alternately disposing conductive layers and dielectric layers in a trench structure (#120, [0066], Figure 4) wherein the trench structure may have a semicircular pattern (Figures 3b and 4) such that the resulting conductive plates of the capacitor would have a patterned outer surface comprising a first semicircular pattern and a second semicircular pattern extending in the vertical direction (Figure 4). Lu also teaches that the trench pattern structure may be comprised of protruding polygonal squares (Figure 3c)
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to one of ordinary skill in the art to consider replacing the polygonal square pattern in the conductive plates of Kim with the semicircular pattern structure of Lu¸ which teaches the two different structures as alternative embodiments (Figure 3 of Lu) since both shapes may increase the surface area of the trench structure without increasing the footprint ([0005] of Lu) which allows for an increase in energy density ([0003] of Lu). This is interpreted by the examiner as an obvious change in shape (see MPEP 2144.04.IV.B) since both configurations are known and provide the same result.
Regarding Claim 11. Kim in view of Lu discloses The integrated circuit of claim 10, wherein
the first patterned side surface faces the second patterned side surface (Figures 5 and 6 of Kim, sidewalls of the patterned surfaces of electrodes face one another; Figures 3 and 4 of Lu, patterned sidewalls of the respective trenches where the conductive plates are formed face one another),
the first semicircular pattern of the first patterned side surface has been formed to be engaged with the second semicircular pattern of the second patterned side surface (Figures 3 and 4 of Lu, patterned semicircular pattern sidewalls of the respective trenches where the conductive plates are formed are structured to be engaged with one another), and
a first diameter of the first semicircular pattern matches a second diameter of the second semicircular pattern (Figures 3 and 4 of Lu, patterned semicircular pattern sidewalls of the respective trenches where the conductive plates are formed match one another to have matching diameters in order to be engaged).
Regarding Claim 12. Kim discloses The integrated circuit of claim 1.
Kim does not disclose that the first patterned side surface comprises at least one of a first semielliptical pattern and a wave pattern extending in the vertical direction, and the second patterned side surface comprises at least one of a second semielliptical pattern and a second wave pattern extending in the vertical direction.
However, Lu teaches an energy storage device which may be a capacitor ([0003]) formed by alternately disposing conductive layers and dielectric layers in a trench structure (#120, [0066], Figure 4) wherein the trench structure may have a wave structure (Figures 3a and 4) or a semielliptical pattern (Figures 3b and 4, noting here that a circle is a type of ellipse and [0061] of Lu states “the first pattern may also be other regular or irregular patterns, which is not limited in the present disclosure”) such that the resulting conductive plates of the capacitor would have a patterned outer surface comprising a first saw/elliptical pattern and a second saw/elliptical pattern extending in the vertical direction (Figure 4). Lu also teaches that the trench pattern structure may be comprised of protruding polygonal squares (Figure 3c)
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to one of ordinary skill in the art to consider replacing the polygonal square pattern in the conductive plates of Kim with the saw pattern structure or semielliptical pattern structure of Lu¸ which teaches the three different structures as alternative embodiments (Figure 3 of Lu) since each shape may increase the surface area of the trench structure without increasing the footprint ([0005] of Lu) which allows for an increase in energy density ([0003] of Lu). This is interpreted by the examiner as an obvious change in shape (see MPEP 2144.04.IV.B) since all configurations are known and provide the same result.
Regarding Claim 13. Kim in view of Lu discloses The integrated circuit of claim 12, wherein
the first patterned side surface faces the second patterned side surface (Figures 5 and 6 of Kim, sidewalls of the patterned surfaces of electrodes face one another; Figures 3 and 4 of Lu, patterned sidewalls of the respective trenches where the conductive plates are formed face one another),
the first patterned side surface comprises the first semielliptical pattern, the second patterned side surface comprises the second semielliptical pattern (Lu, Figure 3b, the trench structure may have a semielliptical pattern, Figures 3b and 4, noting here that a circle is a type of ellipse and [0061] of Lu states “the first pattern may also be other regular or irregular patterns, which is not limited in the present disclosure”),
the first semielliptical pattern of the first patterned side surface has been formed to be engaged with the second semielliptical pattern of the second patterned side surface (Figures 3 and 4 of Lu, patterned semielliptical pattern sidewalls of the respective trenches where the conductive plates are formed are structured to be engaged with one another), and
a first diameter in a long direction of the first semielliptical pattern matches a second diameter in the long direction of the second semielliptical pattern (Figures 3 and 4 of Lu, patterned semielliptical pattern sidewalls of the respective trenches where the conductive plates are formed match one another such that equivalent directions, such as the long direction, will share the same diameter).
Claim(s) 23 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0186992 A1; Guo, Xiaojiang; 06/2023; (“Guo”) in view of US 2012/0282753 A1; Kim, Sun-Oo; 11/2012; (“Kim”).
Regarding Claim 23. Guo discloses A non-volatile memory device (Figures 7A and 7B, memory device which may be non-volatile flash memory according to [0003] and [0043), comprising:
a memory cell array (#501, Figure 7A, memory cell array) comprising a plurality of memory cells (#506, [0042], plurality of memory cells) respectively coupled to a plurality of word lines ([0051], memory cells are electrically coupled to plurality of word lines #518); and
a voltage generator (#710, Figure 7B, voltage generator as part of the control logic in Figure 7A) comprising a charge pump that comprises at least one capacitor configured to generate voltages applied to the plurality of word lines ([0057], voltage generator may include capacitors for controlling voltage output of the logic circuitry which is applied to the memory cell array word line drivers #708 in Figure 7B).
Guo does not disclose that the at least one capacitor comprises a first electrode, a dielectric layer, and a second electrode disposed on a same layer,
wherein the first electrode comprises at least one first metal line having a first patterned side surface, extending in a first horizontal direction, and configured to receive a first voltage, and
wherein the second electrode comprises at least one second metal line having a second patterned side surface, extending in the first horizontal direction, spaced apart from the at least one first metal line in a second horizontal direction, and configured to receive a second voltage, the second voltage being different from the first voltage,
wherein the at least one first metal line has a first width in the second horizontal direction, and
wherein the at least one second metal line has a second width in the second horizontal direction different from the first width.
However, Kim teaches a capacitor (#320a and #320b, Figure 5, capacitor plates, noting here that [0004] provides that the capacitors may be used in memory devices) comprising a first electrode (#320a, Figure 5, capacitor plate), a dielectric layer (#304e, Figures 5 and 6, dielectric materials), and a second electrode (#320b, Figure 5, capacitor plate) disposed on a same layer (Figures 5 and 6, #304e is disposed between #320a and #320b on the same layer),
wherein the first electrode comprises at least one first metal line (leftmost #306e of #320a, Figures 5 and 6, conductive member) having a first patterned side surface (Figure 6, right side surface of leftmost #306e of #320a is patterned), extending in a first horizontal direction (Figure 6, each #306e extends in a first up/down horizontal direction in the top view), and configured to receive a first voltage ([0004], capacitor may have an applied voltage), and
wherein the second electrode (#320b, Figure 5) comprises at least one second metal line (leftmost #306e of #320b, Figures 5 and 6, conductive member) having a second patterned side surface (Figure 6, left side surface of leftmost #306e of #320b is patterned), extending in the first horizontal direction (Figure 6, each #306e extends in a first up/down horizontal direction in the top view), spaced apart from the at least one first metal line in a second horizontal direction (Figures 5 and 6, each #306e is spaced apart from adjacent #306e structures in a left-right second horizontal direction by at least the distance d5), and configured to receive a second voltage ([0004], capacitor may have an applied voltage), the second voltage being different from the first voltage ([0004], the function of a capacitor is to store charge through voltage difference in adjacent electrode plates),
wherein the at least one first metal line has a first width in the second horizontal direction (Figures 5 and 6, leftmost #306e of #320a has a first width in the left-right second horizontal direction of the narrower portions between adjacent thicker portions, labeled as d1 in Figure 3), and
wherein the at least one second metal line has a second width in the second horizontal direction (Figures 5 and 6, leftmost #306e of #320b has a width in the left-right second horizontal direction of the wider or thicker portions between adjacent narrow portions, labeled as d3 in Figure 3) different from the first width (Figures 3, 5, and 6, the widths of the wider and narrower portions, i.e. d3 and d1, are different from one another).
Since Guo is silent regarding the structure of the capacitor used as a charge pump in the voltage generator, this would motivate one of ordinary skill to seek out teachings such as Kim in order to practice the invention of primary. It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention, to consider utilizing the capacitor structure from Kim for the capacitor in Guo since “connecting a plurality of plates 320a and 320b together in parallel as shown in an interwoven or interleaved pattern may result in a capacitor with increased capacitance” as taught by Kim in [0063].
Regarding Claim 24. Guo in view of Kim discloses The non-volatile memory device of claim 23, wherein
the first patterned side surface comprises a first pattern (Kim, Figure 6, right side surface of leftmost #306e of #320a is patterned to have alternating extent protruding square shapes) extending in a vertical direction (Kim, [0062] and Figure 5, the distance between the plates d5 is maintained along the vertical direction such that the pattern necessarily extends in the vertical direction),
the second patterned side surface comprises a second pattern (Kim, Figure 6, left side surface of leftmost #306e of #320b is patterned to have alternating extent protruding square shapes) extending in the vertical direction (Kim, [0062] and Figure 5, the distance between the plates d5 is maintained along the vertical direction such that the pattern necessarily extends in the vertical direction),
the first patterned side surface faces the second patterned side surface (Kim, Figure 6, right side surface of leftmost #306e of #320a faces left side surface of leftmost #306e of #320b), and
the first pattern and the second pattern have an engagement structure (Kim, Figure 6, the patterned sidewalls are structured to at least partially engage with one another of adjacent sidewalls, i.e. may partially fit into one another).
Response to Arguments/Amendments
Applicant’s amendments to the abstract and corresponding remarks, see page 13 of the remarks, filed 03/10/2026, with respect to the objection to the abstract have been fully considered. The objection to the abstract has been withdrawn.
Applicant’s amendments to claims 3 and 4 and corresponding remarks, see page 13 of the remarks, filed 03/10/2026, with respect to the objections to claims 3 and 4 have been fully considered. The objections to claims 3 and 4 have been withdrawn.
Applicant’s amendments to claim 13 and corresponding remarks, see pages 13-14 of the remarks, filed 03/10/2026, with respect to the 35 U.S.C. 112(b) rejection of claim 13 have been fully considered. The 35 U.S.C. 112(b) rejection of claim 13 has been withdrawn.
Applicant’s amendments to claims 1, 17, and 23 and corresponding arguments, see pages 14-21 of the remarks, filed 03/10/2026, with respect to the 35 U.S.C. 102 rejections of claims 1 and 17, and the 35 U.S.C. 103 rejection of claim 23, and the corresponding rejections of their dependent claims, have been fully considered but are not found persuasive.
Applicant argues that the cited prior art, in particular US 2012/0282753 A1; Kim, Sun-Oo; 11/2012; (“Kim”), does not disclose “the at least one first metal line having a first width in the second horizontal direction, and the at least one second metal line having a second width in the second horizontal direction different from the first width” as required in claims 1, 17, and 23. Applicant argues (Argument A, pages 15-16) that Kim discloses that both capacitor plates have a dimension of d3 in Figures 2 and 3 of Kim and that the two plates are symmetrically formed. Applicant further argues (Argument B, pages 17-21) that the additional cited references, US 2021/0005706 A1; Lu et al.; 01/2021; (“Lu”) and US 2023/0186992 A1; Guo, Xiaojiang; 06/2023; (“Guo”) do not resolve the believed missing limitation in Kim. Applicant finally argues (Argument C, page 21) that all of the dependent claims are allowable at least for their dependencies on claims 1, 17, and 23. The examiner respectfully disagrees with applicant’s arguments.
While applicant is correct that Kim does disclose the two capacitor plates as having a width d3 in Figures 2 and 3, Kim also discloses the capacitors plates as having the width d1 in Figures 2 and 3. The current amendment does not require any particular details about the claimed widths (i.e. a greatest width, a narrowest width, etc.) such that any width of either capacitor plate may read on the respective claimed widths, i.e. the narrowest and the widest widths may be taken separately. The claim also does not require the individual capacitor plates to have a first/second width which the other does not have, i.e. both plates may have the first width and the second width, so long as the two widths are different from one another. Therefore, it is the examiner’s interpretation that Kim discloses the at least one first metal line having a first width in the second horizontal direction (Figures 5 and 6, leftmost #306e of #320a has a first width in the left-right second horizontal direction of the narrower portions between adjacent thicker portions, labeled as d1 in Figure 3), and the at least one second metal line having a second width in the second horizontal direction (Figures 5 and 6, leftmost #306e of #320b has a width in the left-right second horizontal direction of the wider or thicker portions between adjacent narrow portions, labeled as d3 in Figure 3) different from the first width (Figures 3, 5, and 6, the widths of the wider and narrower portions, i.e. d3 and d1, are different from one another). For this reason, Argument A is not found persuasive. With regard to the Lu and Guo references (Argument B), it is not necessary that these references disclose the amended limitation as the Kim reference already discloses the amended limitations as described above, the argument is therefore moot. With regard to the dependent claims (Argument C), they are no longer considered allowable for their dependencies as the cited prior art is interpreted to disclose all of the limitations of the amended independent claims, the argument is therefore moot.
Claim(s) 1-4, 7, 8, 14-17, and 21 stand rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2012/0282753 A1; Kim, Sun-Oo; 11/2012; (“Kim”).
Claim(s) 5, 6, and 9-13 stand rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0282753 A1; Kim, Sun-Oo; 11/2012; (“Kim”) as applied to claims 1 and 8 above, and further in view of US 2021/0005706 A1; Lu et al.; 01/2021; (“Lu”).
Claim(s) 23 and 24 stand rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0186992 A1; Guo, Xiaojiang; 06/2023; (“Guo”) in view of US 2012/0282753 A1; Kim, Sun-Oo; 11/2012; (“Kim”).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TYLER J WIEGAND/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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