DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed April 13, 2026 has been entered. Claims 1-25 and 27-29 remain pending in the application. Applicant’s amendments to the Claims have overcome each and every objection previously set forth in the Non-Final Office Action mailed January 12, 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13, 20-25, and 27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the amended limitation of “in contact with an upper surface of a same layer,” can be interpreted in two different ways.
The first way is that “a same layer” can be any insulating layer. The upper surface of a same layer would be in electrical contact with the third capacitor electrode, the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode since all of the electrodes claimed are part of the device and “a same insulating layer” is applied over the entire surface.
The second way is that “a same layer” is “a same layer located immediately below the first insulating layer,” as amended in claim 23. This would require the electrodes claimed to be in direct contact with the upper surface of the “same layer.”
For purposes of examination, Examiner will use the second interpretation.
Claims 2-13 and 20-22 are also rejected as they are dependent on claim 1.
Regarding claim 23, the amended limitation with the “at least one capacitor including two capacitor electrodes facing each other with the first insulating layer in between,” can be interpreted in two different ways.
The first way is the two capacitor electrodes are part of the same capacitor, the top and bottom electrodes facing each other, with the first insulating layer being the dielectric material located between (inside) of the same capacitor.
The second way is the two capacitor electrodes are part of two different capacitors located on the same level with the sides of the electrodes facing each other. Since the two capacitor electrodes are on the same level, when they are covered with the first insulating layer, there will be a portion of the first insulating layer located between the sides of the two capacitor electrodes.
For purposes of examination, Examiner will use the second interpretation.
Claims 24-25, and 27 are also rejected as they are dependent on claim 23.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et. al. (US 20220115625 A1), hereinafter Yu.
Regarding claim 1, Yu teaches a display device (Fig 1 not labeled, consist of display region 100, binding region 200, and edge region 300, [0075]) comprising: a substrate (Fig 23 substrate 10, [0078]) including a display area (Fig 23 display region 100, [0140]) and a non-display area (Fig 23 edge region 300, [0140]) disposed adjacent (Fig 23) to the display area (Fig 23 display region 100, [0140]); a first transistor (Fig 23 transistor 101, [0141]) disposed in the display area (Fig 23 display region 100, [0140]), the first transistor (Fig 23 transistor 101, [0141]) including a first semiconductor layer (Fig 23 not labeled active layer of transistor 101, [0141]; See annotated figure for representative active layer), a first gate electrode (Fig 23 not labeled gate electrode of transistor 101, [0141]; See annotated figure for representative gate electrode), a first source electrode (Fig 23 not labeled source electrode of transistor 101, [0141]; See annotated figure for representative source electrode), and a first drain electrode (Fig 23 not labeled drain of transistor 101, [0141]; See annotated figure for representative drain electrode); a driver circuit area (See annotated figure) and a dam area (See annotated figure) disposed in the non-display area (Fig 23 edge region 300, [0140]); a second transistor (Fig 23 transistor 103, [0141]) disposed in the driver circuit area (See annotated figure), the second transistor (Fig 23 transistor 103, [0141]) including a second semiconductor layer (Fig 23 not labeled active layer of transistor 103, [0141]; See annotated figure for representative active layer), a second gate electrode (Fig 23 not labeled gate electrode of transistor 103, [0141]; See annotated figure for representative gate electrode), a second source electrode (Fig 23 not labeled source electrode of transistor 103, [0141]; See annotated figure for representative source electrode), and a second drain electrode (Fig 23 not labeled drain of transistor 103, [0141]; See annotated figure for representative drain electrode); a first insulating layer (Fig 23 insulating layer 13, [0141]) disposed on (Fig 23 the insulating layer is on the transistor components of active layer, gate layer, and source/drain electrodes; Examiner notes the insulating layer is on the sides of the source/drain electrodes) the first transistor (Fig 23 transistor 101, [0141]) and the second transistor (Fig 23 transistor 103, [0141]); a first capacitor (Fig 23 capacitor 102, [0141]) disposed in (Fig 23) the display area (Fig 23 display region 100, [0140]); and a second capacitor (Fig 23 capacitor 105, [0162]) disposed in (Fig 23) the driver circuit area (See annotated figure), wherein the first capacitor (Fig 23 capacitor 102, [0141]) includes a first capacitor electrode (Fig 23 not labeled top electrode of capacitor 102, [0141]; See annotated figure for electrode) disposed on (Fig 23) the first insulating layer (Fig 23 insulating layer 13, [0141]), and a third capacitor electrode (Fig 23 not labeled bottom electrode of capacitor 102, [0141]; See annotated figure of claim 2 for electrode) disposed under the first insulating layer (Fig 23 insulating layer 13, [0141]), wherein the second capacitor (Fig 23 capacitor 105, [0162]) includes a second capacitor electrode (Fig 23 not labeled top electrode of capacitor 105, [0141]; See annotated figure for electrode) disposed on (Fig 23) the first insulating layer (Fig 23 insulating layer 13, [0141]), and wherein the third capacitor electrode (Fig 23 not labeled bottom electrode of capacitor 102, [0141]; See annotated figure of claim 2 for electrode), the first source electrode (Fig 23 not labeled source electrode of transistor 101, [0141]; See annotated figure for representative source electrode), the first drain electrode (Fig 23 not labeled drain of transistor 101, [0141]; See annotated figure for representative drain electrode), the second source electrode (Fig 23 not labeled source electrode of transistor 103, [0141]; See annotated figure for representative source electrode), and the second drain electrode (Fig 23 not labeled drain of transistor 103, [0141]; See annotated figure for representative drain electrode) are in contact (See note below) with an upper surface (Fig 23 upper surface of insulating layer 12, [0162]) of a same layer (Fig 23 insulating layer 12, [0162]).
Regarding the electrodes being in contact with the upper surface of a same layer. The bottom surface of the third capacitor electrode is in direct contact with the upper surface of insulating layer 12. The side surfaces of the first/second source/drain electrodes are in direct contact with the upper surface of insulating layer 12.
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Regarding claim 2, Yu teaches the second capacitor (Fig 23 capacitor 105, [0162]) further includes a fourth capacitor electrode (Fig 23 not labeled bottom electrode of capacitor 105, [0141]; See annotated figure for electrode) disposed under (Fig 23) the first insulating layer (Fig 23 insulating layer 13, [0141]).
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Regarding claim 3, Yu teaches the third capacitor electrode (Fig 23 not labeled bottom electrode of capacitor 102, [0141]; See annotated figure of claim 2 for electrode), the first source electrode (Fig 23 not labeled source electrode of transistor 101, [0141]; See annotated figure of claim 1for representative source electrode), the first drain electrode (Fig 23 not labeled drain of transistor 101, [0141]; See annotated figure of claim 1 for representative drain electrode), the second source electrode (Fig 23 not labeled source electrode of transistor 101, [0141]; See annotated figure for representative source electrode), and the second drain electrode (Fig 23 not labeled drain of transistor 101, [0141]; See annotated figure for representative drain electrode) are made of a same material (the metal layers can be made from a list of materials, [0093]).
Regarding claim 4, Yu teaches a first planarization layer (Fig 23 flat layer 15, [0141]) disposed on (Fig 23) the first insulating layer (Fig 23 insulating layer 13, [0141]); an anode electrode (Fig 23 anode 21, [0141]) disposed on (Fig 23) the first planarization layer (Fig 23 flat layer 15, [0141]) and in the display area (Fig 23 display region 100, [0140]); and a first connection line (Fig 23 connection electrode 804, [0159]) disposed on (Fig 23) the first planarization layer (Fig 23 flat layer 15, [0141]) and in the non-display area (Fig 23 edge region 300, [0140]).
Regarding claim 5, Yu teaches the first connection line (Fig 23 connection electrode 804, [0159]) overlaps with (See annotated figure of claim 1) the driver circuit area (See annotated figure of claim 1).
Regarding claim 6, Yu teaches a light-emitting layer (Fig 23 light-emitting layer 23, [0141]) disposed on (Fig 23) the anode electrode (Fig 23 anode 21, [0141]); and a cathode electrode (Fig 23 cathode 24, [0141]) disposed on (Fig 23) the light-emitting layer (Fig 23 light-emitting layer 23, [0141]), wherein the first connection line (Fig 23 connection electrode 804, [0159]) is electrically connected (Fig 23, [0159]) to the cathode electrode (Fig 23 cathode 24, [0141]) in the dam area (See annotated figure of claim 1).
Regarding claim 7, Yu teaches a second connection line (Fig 23 connection electrode 803, [0159]) electrically connected (Fig 23, [0154]) to the first connection line (Fig 23 connection electrode 804, [0159]) in the dam area (See annotated figure of claim 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et. al. (US 20220115625 A1), hereinafter Yu, in view of Jia (US 20220149024 A1).
Regarding claim 8, Yu fails to teach a third transistor disposed in the display area, wherein the third transistor includes a third semiconductor layer, a third gate electrode, a third source electrode, and a third drain electrode.
However, Jia teaches a third transistor (Fig 3A transistor T1, [0132]) disposed in the display area (Fig 3A display region 102, [0125] corresponds to Yu: Fig 23 display region 100, [0140]), wherein the third transistor (Fig 3A transistor T1, [0132]) includes a third semiconductor layer (Fig 3A semiconductor layer 205, [0132] corresponds to Yu: Fig 23 not labeled active layer of a transistor; See annotated figure of claim 1 for representative active layer), a third gate electrode (Fig 3A gate electrode 208, [0132] corresponds to Yu: Fig 23 not labeled gate electrode of a transistor; See annotated figure of claim 1 for representative gate electrode), a third source electrode (Fig 3A source electrode 206, [0132] corresponds to Yu: Fig 23 not labeled source electrode of a transistor; See annotated figure of claim 1 for representative source electrode), and a third drain electrode (Fig 3A drain electrode 207, [0132] corresponds to Yu: Fig 23 not labeled drain of a transistor; See annotated figure of claim 1 for representative drain electrode).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Yu to incorporate the teachings of Jia by having a third transistor in the display area. This would allow for the driver circuit to have more than two transistors for more stable light emission ([0020]).
Examiner notes the transistors of Jia are similar to those of Yu, in that they are formed on the same layer. Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that display drive circuits can have more than two transistors that may not be shown in the drawings supplied.
Regarding claim 9, Yu as modified in claim 8 teaches a first metal layer (Yu: Fig 18 connection electrode 801, [0129]) disposed on (Yu: Fig 18) the first insulating layer (Yu: Fig 18 insulating layer 13, [0141]) and overlapping with (Yu: Fig 18) a portion of the first transistor (Yu: Fig 18 transistor 101, [0141]).
Yu fails to teach a second metal layer disposed on the first insulating layer and overlapping with a portion of the third transistor.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that since the third transistor has a similar structure to the first transistor then the third transistor would also have a similar additional metal layer. In having a similar structure, there would be a second metal layer (Yu: Fig 18 connection electrode 801, [0129]; same as for the first metal layer) disposed on (Yu: Fig 18) the first insulating layer (Yu: Fig 18 insulating layer 13, [0141]) and overlapping with (Yu: Fig 18) a portion of the third transistor (Jia: Fig 3A transistor T1, [0132]).
Examiner notes that while the connection electrode 801 is not shown in Fig 23, there is a description of the inclusion of the connection electrode 801 in [0141], [0146] and [0148] of Yu.
Regarding claim 10, Yu as modified in claim 9 teaches each of the first metal layer (Yu: Fig 18 connection electrode 801, [0129]), the second metal layer (Yu: Fig 18 connection electrode 801, [0129]), and the first capacitor electrode (Yu: Fig 23 not labeled top electrode of capacitor 102, [0141]; See annotated figure of claim 1 for electrode) includes at least one of titanium (Ti) (Yu: the metal layers can be made from a list of materials; Ti, [0093]), (the rest are optional so they are not considered) molybdenum (Mo), copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), gold (Au), neodymium (Nd), or nickel (Ni), or is made of an alloy thereof.
Regarding claim 11, Yu as modified in claim 9 teaches each of the first metal layer (Yu: Fig 18 connection electrode 801, [0129]), the second metal layer (Yu: Fig 18 connection electrode 801, [0129]), and the first capacitor electrode (Yu: Fig 23 not labeled top electrode of capacitor 102, [0141]; See annotated figure of claim 1 for electrode) is composed of at least two layers including a first layer made of titanium (Ti) (Yu: the metal layers can be made from a list of materials; the multilayer composite has Ti for the first layer, [0093]), and a second layer made of at least one of molybdenum (Mo) (the rest are optional so they are not considered), copper (Cu), aluminum (Al) (Yu: the multilayer composite has Al for the second layer, [0093]), (the rest are optional so they are not considered) silver (Ag), chromium (Cr), gold (Au), neodymium (Nd), or nickel (Ni).
Regarding claim 12, Yu as modified in claim 9 teaches a first planarization layer (Yu: Fig 18 flat layer 17, [0129]) disposed on (Yu: Fig 18) the first insulating layer (Yu: Fig 18 insulating layer 13, [0129]); and an anode electrode (Yu: Fig 18 anode 21, [0129]) disposed on the first planarization layer (Yu: Fig 18 flat layer 17, [0141]) and in the display area (Yu: Fig 18 display region 100, [0129]), wherein the first metal layer (Yu: Fig 18 connection electrode 801, [0129]) electrically connects (Yu: Fig 18, [0129]) the first drain electrode (Yu: Fig 18 not labeled drain of transistor 101, [0141]; See annotated figure of claim 1 for representative drain electrode) of the first transistor (Yu: Fig 18 transistor 101, [0129]) with the anode electrode (Yu: Fig 18 anode 21, [0129]).
Regarding claim 13, Yu as modified in claim 12 teaches a fourth transistor (Fig 23 transistor 104, [0142]) disposed in the driver circuit area (See annotated figure of claim 1) , wherein the fourth transistor (Fig 23 transistor 104, [0142]) includes a fourth semiconductor layer (Fig 23 not labeled active layer of transistor 104, [0142]; See annotated figure of claim 1 for representative active layer), a fourth gate electrode (Fig 23 not labeled gate electrode of transistor 104, [0142]; See annotated figure of claim 1 for representative gate electrode), a fourth source electrode (Fig 23 not labeled source electrode of transistor 104, [0142]; See annotated figure of claim 1 for representative source electrode), and a fourth drain electrode (Fig 23 not labeled drain of transistor 104, [0142]; See annotated figure of claim 1 for representative drain electrode).
Regarding claim 20, Yu as modified in claim 9 teaches the first metal layer (Yu: Fig 18 connection electrode 801, [0129]), the second metal layer (Yu: Fig 18 connection electrode 801, [0129]; modified by Jia to have third transistor), and the first capacitor electrode (Yu: Fig 18 not labeled top electrode of capacitor 102, [0141]; See annotated figure of claim 1 for electrode) are disposed on a same layer (Fig 18 insulating layer 11, [0149]).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et. al. (US 20220115625 A1), hereinafter Yu, in view of Jia (US 20220149024 A1), in further view of Xiao et. al. (CN 114122025 A), hereinafter Xiao.
Yu fails to teach the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer is made of an oxide semiconductor, and wherein the fourth semiconductor layer is made of a polycrystalline silicon semiconductor.
However, Xiao teaches transistors may be polycrystalline silicon, oxide, or a combination of low-temperature polycrystalline silicon and oxide thin-film transistors ([n0077] of translation). Further, Xiao teaches polycrystalline silicon transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current ([n0077] of translation). Additionally, Xiao teaches in combining polysilicon and oxide transistors onto a single display substrate allows for the utilization of the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality ([n0077] of translation). Yu also teaches the active layers may be made of either polysilicon or oxide materials ([0093]). One having ordinary skill in the art before the effective filing date of the claimed invention would be able to arrive at a combination of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer being made of an oxide semiconductor, and the fourth semiconductor layer being made of a polycrystalline silicon semiconductor with a reasonable expectation of success. This would aid in achieving a balance between reduced power consumption and improved display quality, as taught by Xiao.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et. al. (US 20220115625 A1), hereinafter Yu, in view of Park et. al. (US 20200321292 A1), hereinafter Park.
Yu fails to teach a light- blocking layer disposed under the first semiconductor layer, the light blocking layer overlapping with the first semiconductor layer, wherein the light-blocking layer is electrically connected to the first drain electrode.
However, Park teaches a light-blocking layer (Fig 4 light blocking layer LB, [0075]) disposed under the first semiconductor layer (Fig 4 semiconductor layer Ap corresponds to Yu: Fig 23 not labeled active layer of transistor 101, [0141]; See annotated figure of claim 1 for representative active layer), the light blocking layer (Fig 4 light blocking layer LB, [0075]) overlapping with the (Fig 4) first semiconductor layer (Fig 4 semiconductor layer Ap corresponds to Yu: Fig 23 not labeled active layer of transistor 101, [0141]; See annotated figure of claim 1 for representative active layer), wherein the light-blocking layer (Fig 4 light blocking layer LB, [0075]) is electrically connected ([0085]) to the first drain electrode (Fig 4 drain electrode Dp, [0082] corresponds to Yu: Fig 23 not labeled drain of transistor 101, [0141]; See annotated figure for representative drain electrode).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Yu to incorporate the teachings of Park by having a light blocking layer overlapping with the first semiconductor layer and being electrically connected to the first drain electrode. This would prevent deterioration of the semiconductor layer from light and improve the transistor characteristics ([0075]).
Claims 23-25 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et. al. (US 20220115625 A1), hereinafter Yu, in view of Jia (US 20220149024 A1), in further view of Xiao et. al. (CN 114122025 A), hereinafter Xiao.
Regarding claim 23, Yu teaches a display device (Fig 1 not labeled, consist of display region 100, binding region 200, and edge region 300, [0075]) comprising: a first transistor (Fig 23 transistor 101, [0141]) disposed in a display area (Fig 23 display region 100, [0140]) of a substrate (Fig 23 substrate 10, [0078]), the first transistor (Fig 23 transistor 101, [0141]) including a first semiconductor layer (Fig 23 not labeled active layer of transistor 101, [0141]; See annotated figure for representative active layer), a first gate electrode (Fig 23 not labeled gate electrode of transistor 101, [0141]; See annotated figure for representative gate electrode), a first source electrode (Fig 23 not labeled source electrode of transistor 101, [0141]; See annotated figure for representative source electrode) and a first drain electrode (Fig 23 not labeled drain of transistor 101, [0141]; See annotated figure for representative drain electrode); a second transistor disposed a non-display area (Fig 23 edge region 300, [0140]) of the substrate (Fig 23 substrate 10, [0078]), the second transistor (Fig 23 transistor 103, [0141]) including a second semiconductor layer (Fig 23 not labeled active layer of transistor 101, [0141]; See annotated figure for representative active layer), a second gate electrode (Fig 23 not labeled gate electrode of transistor 103, [0141]; See annotated figure for representative gate electrode), a second source electrode (Fig 23 not labeled source electrode of transistor 103, [0141]; See annotated figure for representative source electrode) and a second drain electrode (Fig 23 not labeled drain of transistor 103, [0141]; See annotated figure for representative drain electrode); a first insulating layer (Fig 23 insulating layer 13, [0141]) disposed across the (Fig 23 the insulating layer is across the transistor components of active layer, gate layer, and source/drain electrodes; Examiner notes the insulating layer is across the sides of the source/drain electrodes) first transistor (Fig 23 transistor 101, [0141]) and the second transistor (Fig 23 transistor 103, [0141]); and at least one capacitor (Fig 23 capacitor 102, [0141]) including two capacitor electrodes (Fig 23 bottom electrodes for capacitors 102 and 105) facing each other (the side surfaces are facing each other) with the first insulating layer (Fig 23 insulating layer 13, [0141]) in between, wherein the at least one capacitor (Fig 23 capacitor 102, [0141]) includes a material (the metal layers can be made from a list of materials; Ti is chosen, [0093]) configured to absorb hydrogen ([0093] of the specification discloses Ti adsorbs hydrogen; Ti was chosen from the list of materials of Yu; the Ti of Yu also adsorbs hydrogen, MPEP 2112.01(II)), and wherein any one of the two capacitor electrodes (Fig 23 bottom electrode for capacitors 102), the first source electrode (Fig 23 not labeled source electrode of transistor 101, [0141]; See annotated figure for representative source electrode), the first drain electrode (Fig 23 not labeled drain of transistor 101, [0141]; See annotated figure for representative drain electrode), the second source electrode (Fig 23 not labeled source electrode of transistor 103, [0141]; See annotated figure for representative source electrode), and the second drain electrode (Fig 23 not labeled drain of transistor 103, [0141]; See annotated figure for representative drain electrode) are in contact (See note below) with an upper surface of a same layer (Fig 23 upper surface of insulating layer 12, [0142]) located immediately below (Fig 23) the first insulating layer (Fig 23 insulating layer 13, [0141]).
Yu fails to teach a first oxide transistor, a first oxide semiconductor layer, a second polycrystalline silicon transistor, a second polycrystalline silicon semiconductor layer.
However, Xiao teaches transistors may be polycrystalline silicon, oxide, or a combination of low-temperature polycrystalline silicon and oxide thin-film transistors ([n0077] of translation). Further, Xiao teaches polycrystalline silicon transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current ([n0077] of translation). Additionally, Xiao teaches in combining polycrystalline silicon and oxide transistors onto a single display substrate allows for the utilization of the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality ([n0077] of translation). Yu also teaches the active layers may be made of either polysilicon or oxide materials ([0093]).
Regarding the choice of having a first oxide transistor and a second polycrystalline silicon transistor, this particular combination would have been obvious to try. As stated above, Xiao shows there was a known need in the display arts for reduced power consumption and improved display quality. In pursuing this arrangement in the device of Yu, there are only four combinations to achieve this result: all transistors being oxide, the first transistor being oxide/ the second transistor being polycrystalline silicon, the first transistor being polycrystalline silicon/ the second transistor being oxide, or all semiconductor layers being polysilicon. One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that there would be an intersection between the desired reduction in power consumption with the improvement of display quality. That is, "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103." KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421.
In modifying Yu with the teachings of Xiao to have a first oxide transistor and a second polycrystalline silicon transistor, the respective semiconductor layers would also be oxide or polycrystalline silicon, respectively.
Regarding the electrodes being in contact with the upper surface of a same layer. The bottom surface of the third capacitor electrode is in direct contact with the upper surface of insulating layer 12. The side surfaces of the first/second source/drain electrodes are in direct contact with the upper surface of insulating layer 12.
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Regarding claim 24, Yu as modified in claim 23 teaches the at least one capacitor (Yu: Fig 23 capacitor 102, [0141]) includes: a first capacitor (Yu: Fig 23 capacitor 102, [0141]) disposed in the display area (Yu: Fig 23 display region 100, [0140]); and a second capacitor (Yu: Fig 23 capacitor 105, [0162]) disposed in the non-display area (Yu: Fig 23 edge region 300, [0140]), wherein the first capacitor (Yu: Fig 23 not labeled top electrode of capacitor 102, [0141]; See annotated figure for electrode) includes a first capacitor electrode (Yu: See annotated figure) disposed on the first insulating layer (Yu: Fig 23 insulating layer 13, [0141]), and a third capacitor electrode(Yu: Fig 23 not labeled bottom electrode of capacitor 102, [0141]) disposed under the first insulating layer (Yu: Fig 23 insulating layer 13, [0141]), and wherein the second capacitor (Yu: Fig 23 capacitor 105, [0162]) includes a second capacitor electrode (Yu: Fig 23 not labeled top electrode of capacitor 105, [0141]; See annotated figure for electrode) disposed on the first insulating layer (Yu: Fig 23 insulating layer 13, [0141]), and a fourth capacitor electrode (Yu: Fig 23 not labeled bottom electrode of capacitor 105, [0141]) disposed under the first insulating layer (Yu: Fig 23 insulating layer 13, [0141]).
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Regarding claim 25, Yu as modified in claim 24 fails to teach the first oxide transistor is disposed between the first capacitor in the display area and the second capacitor in the non-display area.
However, one having ordinary skill in the art before the effective filing date of the claimed invention would be able to move the position of the first capacitor such that the first oxide transistor (Yu: Fig 23 transistor 101, [0141]) is disposed between the first capacitor (Yu: Fig 23 capacitor 102, [0141]) in the display area (Yu: Fig 23 display region 100, [0140]) and the second capacitor (Yu: Fig 23 capacitor 105, [0162]) in the non-display area (Yu: Fig 23 edge region 300, [0140]) with a reasonable expectation of success and there would be no change in the operation of the device if the capacitor was on the left or right side of the first oxide transistor. MPEP 2144.04(VI)(C)
Regarding claim 27, Yu as modified in claim 26 teaches the first source electrode (Yu: Fig 23 not labeled source electrode of transistor 101, [0141]; See annotated figure of claim 23 for representative source electrode), the first drain electrode (Yu: Fig 23 not labeled drain of transistor 101, [0141]; See annotated figure of claim 23 for representative drain electrode), the second source electrode (Yu: Fig 23 not labeled source electrode of transistor 103, [0141]; See annotated figure of claim 23 for representative source electrode), the second drain electrode (Yu: Fig 23 not labeled drain of transistor 101, [0141]; See annotated figure of claim 23 for representative drain electrode), the third capacitor electrode (Yu: Fig 23 not labeled bottom electrode of capacitor 102, [0141]) of the first capacitor (Yu: Fig 23 capacitor 102, [0141]) and the fourth capacitor electrode (Yu: Fig 23 not labeled bottom electrode of capacitor 105, [0141]) of the second capacitor (Yu: Fig 23 capacitor 105, [0162]) include a same material (Yu: the metal layers can be made from a list of materials; Ti is chosen, [0093]) configured to absorb hydrogen (Yu: [0093] of the specification discloses Ti adsorbs hydrogen; Ti was chosen from the list of materials of Yu; the Ti of Yu also adsorbs hydrogen, MPEP 2112.01(II)).
Response to Arguments
Applicant’s arguments, see 35 USC §112 section on page 9, filed April 13, 2026, with respect to amendments to claim 23 to overcome the 35 USC §112 rejection have been fully considered and are persuasive. The 35 USC §112 rejection of claims 23-27 has been withdrawn.
Applicant’s arguments, see 35 USC §102/103 section starting on page 9, filed April 13, 2026, with respect to the rejections of claims 1-7 under 35 USC §102 and claims 8-13 and 20 under 35 USC §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a different interpretation of Yu for claims 1-13 and 20.
The amendments to the claims can be interpreted to read on a different perspective of Yu. The top most surface of the source/drain electrodes is in direct contact with insulating layer 16. However, the side surfaces of the source/drain electrodes extends from the source/drain region of the active layer to the top most surface, through many different insulating layers; all of the insulating layers along the way, in direct contact with the side surface of the source/drain electrodes. As such, there is an insulating layer that is in direct contact with an upper surface of an underlying insulating layer, as well as direct contact the electrodes as claimed.
Applicant’s arguments, see 35 USC §102/103 section starting on page 9, filed April 13, 2026, with respect to the rejections of claims 23-24 and 27 under 35 USC §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a different interpretation of Yu for claims 1-13 and 20.
Similar to claim 1, the amendments to the claims can be interpreted to read on a different perspective of Yu. The top most surface of the source/drain electrodes is in direct contact with insulating layer 16. However, the side surfaces of the source/drain electrodes extends from the source/drain region of the active layer to the top most surface, through many different insulating layers; all of the insulating layers along the way, in direct contact with the side surface of the source/drain electrodes. As such, there is an insulating layer that is in direct contact with an upper surface of an underlying insulating layer, as well as direct contact the electrodes as claimed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN GAUTHIER can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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