DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group II (claims 10-17) in the reply filed on 11/03/25 is acknowledged. The traversal is on the ground(s) that all groups of the claims are sufficiently related to each other that an undue burden would not be placed upon the examiner by maintaining all groups in a single application. This is not found persuasive because the search of Group II (a full color LED display) would require a search in different subclasses in combination with the use of different search queries than that of the manufacturing method of an LED display. Although a search of the two inventions have overlapping areas of scope, the divergent limitations associated with each group cover an area of search that would provide an undue burden on examination.
The requirement is still deemed proper and is therefore made FINAL.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 10 and 12-17 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 11-19 of copending Application No. 18/221213 (reference application US 20210021588 (Do)). Although the claims at issue are not identical, they are not patentably distinct from each other because:
Concerning claim 10, Do discloses a full-color LED display comprising: a lower electrode line in which a plurality of sub-pixel sites are formed (Claim 11); a plurality of ultra-thin pin LED devices including, based on mutually perpendicular x-axis, y-axis and z-axis wherein the x-axis direction is a major axis and a plurality of layers are stacked in the z-axis direction, a first surface and a second surface opposite to each other in the z-axis direction, and other side surfaces (Claim 11), wherein the ultra-thin pin LED devices are mounted so that one surface thereof is in contact with the lower electrode line in each sub-pixel site (Claim 11), and emit substantially the same light color; an upper electrode line disposed on the plurality of ultra-thin pin LED devices (Claim 11); and a color conversion layer patterned on the upper electrode line (Claim 18) so that each of the plurality of sub-pixel sites becomes a sub-pixel site emitting any one color among blue, green, and red (Claim 19), wherein the plurality of ultra-thin pin LED devices mounted have a drivable mounting ratio of 55% or more in which the first surface or the second surface of each device is mounted so as to contact the lower electrode line (Claim 11).
Continuing to claim 12, Do discloses wherein the width of the ultra-thin pin LED device, which is the length in the y-axis direction, is smaller than the thickness, which is the length in the z-axis direction (Claim 13).
Considering claim 13, Do discloses wherein the drivable mounting ratio of the plurality of ultra-thin pin LED devices mounted is 70% or more (Claim 14).
Regarding claim 14, Do discloses wherein a selective mounting ratio, which is a ratio of the number of devices mounted such that any one of the first and second surfaces thereof is in contact with the lower electrode line among the plurality of ultra-thin pin LED devices mounted, satisfies 70% or more (Claim 15).
Referring to claim 15, Do discloses wherein the selective mounting ratio satisfies 85% or more (Claim 16).
Pertaining to claim 16, Do discloses wherein the light color is blue, white or UV (Claim 19).
As to claim 17, Do discloses a full-color LED display capable of DC driving, comprising: a lower electrode line in which a plurality of sub-pixel sites are formed (Claim 11), wherein the plurality of sub-pixel sites include all of blue, green, and red, and each site is designated with one of these light colors (Claim 19); a plurality of ultra-thin pin LED devices including, based on mutually perpendicular x-axis, y-axis and z-axis wherein the x-axis direction is a major axis and a plurality of layers are stacked in the z-axis direction, a first surface and a second surface opposite to each other in the z-axis direction, and other side surfaces (Claim 11), wherein each of the plurality of ultra-thin pin LED devices independently emits light of any one of blue, green, and red (Claim 19), wherein the ultra-thin pin LED devices are mounted so that one surface thereof is in contact with the lower electrode line in each sub-pixel site (Claim 11), and emit substantially the same light color; an upper electrode line disposed on the plurality of ultra-thin pin LED devices (Claim 11); wherein the plurality of ultra-thin pin LED devices mounted have a drivable mounting ratio of 55% or more in which the first surface or the second surface of each device is mounted so as to contact the lower electrode line (Claim 11)
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim 11 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 18 of copending Application No. 18221213 (US 20210021588 (Do)) in view of US 20220209063 (Do, hereafter referred to as Do’063).
Concerning claim 11, Do discloses forming an ultra-thin fin LED with a plurality of layers (Claim 11).
Do does not disclose wherein each of the plurality of layers in the ultra-thin fin LED device includes an n-type conductive semiconductor layer, a photoactive layer, and a p-type conductive semiconductor layer, and the thickness, which is a distance in the z-axis direction, is 0.1 to 3 µm, and the length in the x-axis direction is 1 to 10 µm. However, Do’063 discloses an ultra-thin fin LED device that includes an n-type conductive semiconductor layer, a photoactive layer, and a p-type conductive semiconductor layer ([0011]), and the thickness, which is a distance in the z-axis direction, is 0.1 to 3 µm, and the length in the x-axis direction is 1 to 10 µm ([0012]-[0014]). Do’063 also discloses that this configuration of the ultra-thin light-emitting diode (LED) element is suitable for ink formation, has a wide emission area, minimizes or prevents a decrease in efficiency due to surface defects, and has an optimized electron-hole recombination rate ([0010]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form the plurality of layers of the ultra-thin fin LED to include an n-type conductive semiconductor layer, a photoactive layer, and a p-type conductive semiconductor layer, and the thickness, which is a distance in the z-axis direction, is 0.1 to 3 µm, and the length in the x-axis direction is 1 to 10 µm in order to form a device with an optimized electron-hole recombination rate.
This is a provisional nonstatutory double patenting rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20220044624 discloses an LED display panel formed by the use of driving electrodes (Abstract and Figs. 8 and 9).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VALERIE N NEWTON/Examiner, Art Unit 2897 02/03/26
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897