Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed January 9, 2026. Claims 1, 15 and 20 are amended. The Examiner notes that claims 1-20 are examined.
Response to Arguments
Applicant's arguments filed January 9, 2026 have been fully considered but they are not persuasive.
Applicant argues that Suh allegedly does not teach “a uniform encapsulant” because insulation member 140 and filler material 160 are not made from the same material and are therefore not uniform. The Examiner notes that in the rejection below, only insulation member 140 is identified with the “uniform encapsulant” and filler member 160 is identified as a part of the conductive through holes (analogous to element 160 of the instant application). Insulation member 140 is made of a single material and therefore is considered uniform. The argument is found unpersuasive and the rejection is maintained.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-15, and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suh (US 2011/0227217 A1).
With respect to claim 1, Suh teaches in Fig. 1-8E:
A semiconductor device, comprising:
a plurality of stacked semiconductor dies (stacked semiconductor chips 120),
the plurality of semiconductor dies together defining a sidewall (step surfaces S on left side of 120 that first conductive part 130a is disposed on, including both vertical and horizontal portions of the wall);
a plurality of die bond pads (bonding pads 122) on the plurality of semiconductor dies (120) and positioned at the sidewall (positioned on the sidewall S which includes the vertical and horizontal parts on the left of 120);
a uniform encapsulant (insulation member 140) covering at least portions of the plurality of stacked semiconductor dies including the sidewall and the plurality of die bond pads (para. 64 “an insulation member 140 (shown in FIG. 8B) is formed in such a way as to cover the upper surface of the carrier 200 including the semiconductor chip groups 210.”)
and conductive through-holes (filler member 160 which can be conductive paste or conductive film and conductive patterns 130) formed in through-hole cavities (recess 142) developed through the encapsulant (para. 65 “By selectively removing the insulation member 140, recesses 142 are defined in such a way as to expose the step surfaces S”),
the plurality of die bond pads (122) exposed at the through-hole cavities (see Fig. 1).
Examiner Note: The limitations “an encapsulant covering at least portions of the plurality of stacked semiconductor dies including the sidewall and the plurality of die bond pads and conductive through-holes formed in through-hole cavities developed through the encapsulant” appears to direct to a product-by-process limitation as the encapsulant covering the sidewall and plurality of die bond pads appears in an intermediate step of Fig. 16 of the instant application and hole cavities developed through the encapsulant is shown in an intermediate step in Fig. 17. For the purpose of determining patentability, “The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” (In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), see MPEP 2113(I). As claim 1 directs to a product, limitations reciting methods of forming the encapsulant and conductive through hole are not given patentable weight. However, as the method of Suh does recite the limitations drawn to intermediate steps and the process of making the product of the instant application, the limitations are mapped to Suh in the rejection above.
With respect to claim 3, Suh further teaches:
wherein the sidewall (S) is a stepped, offset sidewall (see Fig. 1).
With respect to claim 4, Suh further teaches:
wherein the through-hole cavities (142) are through the encapsulant (140).
With respect to claim 5, Suh further teaches:
further comprising a plurality of contact pads (ball lands 114) formed on a surface of the semiconductor device (ball lands 114 are formed on the lower surface 110b of substrate 110 which is formed on the bottom surface of encapsulant 170).
With respect to claim 6, Suh further teaches:
further comprising a redistribution pattern (substrate 110 which connects to external connection terminals 180) on the surface of the semiconductor device (on the bottom surface of encapsulant 170 and underfill 162), the redistribution pattern electrically coupling the plurality of contact pads (114) to the conductive through-holes (160/130).
With respect to claim 7, Suh further teaches:
wherein the surface is on a surface of the encapsulant (the bottom surface 110b is on a bottom surface of the encapsulant 170 through substrate 110).
With respect to claim 8, Suh further teaches:
wherein the encapsulant (140 and 170) comprises a photo imageable dielectric material (para. 64, 140 may be polyimide, which is listed in para. 46 of the instant application as an exemplary material for the PID layer).
With respect to claim 9, Suh further teaches:
wherein the through-hole cavities (142) have a uniform cross-sectional shape along a length of the through-hole cavities (uniform cross section along the partial length of the hole cavity equal to the length of an individual step as indicated in annotated Fig. 3 below).
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With respect to claim 10, Suh further teaches:
wherein the through-hole cavities (142) are wider at a top portion of the through-hole cavities than at a bottom portion of the through-hole cavities (see Fig. 1).
With respect to claim 11, Suh further teaches:
wherein the conductive through-holes (130 and 160) comprise an electrical conductor lining the through-hole cavities (conductive patterns 130).
With respect to claim 12, Suh further teaches:
wherein the conductive through-holes (130 and 160) comprise an electrical conductor filling (160 may be an anisotropic conductive paste or anisotropic conductive film) the through-hole cavities (142).
With respect to claim 13, Suh further teaches:
wherein the plurality of semiconductor dies comprise one or more stacks of individual semiconductor dies (see Fig. 7A, multiple stacks 120 are deposited on a carrier wafer 200 for wafer level processing as shown in Fig. 8A-8E)).
With respect to claim 14, Suh further teaches:
wherein the plurality of semiconductor dies comprise whole semiconductor wafers of semiconductor dies (see Fig. 7A, multiple stacks 120 are deposited on a carrier wafer 200 for wafer level processing as shown in Fig. 8A-8E).
With respect to claim 15, Suh teaches in Fig. 1-8E:
A semiconductor device, comprising:
a plurality of stacked semiconductor dies (stacked semiconductor chips 120),
the plurality of semiconductor dies together defining a sidewall (step surfaces S on left side of 120 that first conductive part 130a is disposed on, including both vertical and horizontal portions of the wall);
a plurality of die bond pads (bonding pads 122) on the plurality of semiconductor dies (120) and arranged in columns at the sidewall (arranged on the sidewall S which includes the vertical and horizontal parts on the left of 120. Meets limitation of “arranged in columns” under definition of column of “an accumulation arranged vertically: stack”);
a uniform layer of photo imageable dielectric material (insulation member 140 which may be polyimide) covering at least portions of the plurality of stacked semiconductor dies including the sidewall and the plurality of die bond pads (para. 64 “an insulation member 140 (shown in FIG. 8B) is formed in such a way as to cover the upper surface of the carrier 200 including the semiconductor chip groups 210.”)
and conductive through-holes (filler member 160 which can be conductive paste or conductive film and conductive patterns 130) formed in the photo imageable dielectric material (140),
the plurality of die bond pads (122) exposed at the through-hole cavities (see Fig. 1).
and the conductive through-holes (130 and 160) electrically coupling die bond pads (122) on the columns of die bond pads together (see Fig. 1).
With respect to claim 17, Suh further teaches:
wherein the plurality of stacked semiconductor dies (120) comprise a stack of semiconductor dies offset from each other with a stepped offset (see fig. 1).
With respect to claim 18, Suh further teaches:
wherein the conductive through holes (130 and 160) are wider at a first end of the conductive through-holes than at a second end of the conductive through-holes (see Fig. 1).
With respect to claim 19, Suh further teaches:
wherein the plurality of stacked semiconductor dies (120) comprise one or more stacks of individual semiconductor dies (see Fig. 7A, multiple stacks 120 are deposited on a carrier wafer 200 for wafer level processing as shown in Fig. 8A-8E)).
With respect to claim 20, Suh teaches:
A semiconductor device, comprising:
a plurality of stacked semiconductor dies (stacked semiconductor chips 120),
the plurality of semiconductor dies together defining a sidewall (step surfaces S on left side of 120 that first conductive part 130a is disposed on, including both vertical and horizontal portions of the wall);
a plurality of die bond pads (bonding pads 122) on the plurality of semiconductor dies (120) and arranged in columns at the sidewall (arranged on the sidewall S which includes the vertical and horizontal parts on the left of 120. Meets limitation of “arranged in columns” under definition of column of “an accumulation arranged vertically: stack”);
a uniform layer of photo imageable dielectric material (insulation member 140 which may be polyimide) covering at least portions of the plurality of stacked semiconductor dies including the sidewall and the plurality of die bond pads (para. 64 “an insulation member 140 (shown in FIG. 8B) is formed in such a way as to cover the upper surface of the carrier 200 including the semiconductor chip groups 210.”)
and means formed through the photo imageable dielectric material (140) for electrically coupling die bond pads on the columns of die bond pads together (conductive patterns 130 and filler material 160 which may be conductive).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Suh (US 2011/0227217 A1) as applied to independent claims 1 and 15 above and in view of Liu (US 2011/0317371 A1).
With respect to claim 2, Suh teaches all limitations of independent claim 1 upon which claim 2 depends. Suh fails to teach:
wherein the sidewall is a planar sidewall.
Liu teaches in Fig. 7b:
wherein the sidewall is a planar sidewall (see annotated Fig. 7b below. For the purpose of this action, the stack of Liu includes semiconductor chips 200b, 214b, 226b, and 238b, the insulating layers between them, and pads 202, 216, 228, and 240).
Suh discloses the claimed invention except for shape of the sidewall of the semiconductor die stack. Liu discloses that it is known in the art to provide a sidewall that is planar, not stepped. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the die stack of Suh with the planar shape of Liu, in order to reduce the footprint of the stack on the device. See MPEP 2144. Further, claim 2 differs from Suh only in the shape of the die stack. It has been ruled that changes of shape are prima facie obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV)(B)) and the ordinary artisan would be motivated to modify Suh in order to optimize the layout of the die package.
With respect to claim 16, Suh teaches all limitations of independent claim 15 upon which claim 16 depends. Suh fails to teach:
wherein the plurality of stacked semiconductor dies comprise a stack of vertically aligned semiconductor dies and the sidewall is a planar sidewall.
Liu teaches in Fig. 7b:
wherein the plurality of stacked semiconductor dies (semiconductor chips 200b, 214b, 226b, and 238b) comprise a stack of vertically aligned semiconductor dies (comprises the chips, insulating layers between them, and pads 202, 216, 228, and 240) and the sidewall is a planar sidewall (see annotated Fig. 7b above).
Suh discloses the claimed invention except for shape of the sidewall of the semiconductor die stack. Liu discloses that it is known in the art to provide a sidewall that is planar, not stepped. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the die stack of Suh with the planar shape of Liu, in order to reduce the footprint of the stack on the device. See MPEP 2144. Further, claim 2 differs from Suh only in the shape of the die stack. It has been ruled that changes of shape are prima facie obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV)(B)) and the ordinary artisan would be motivated to modify Suh in order to optimize the layout of the die package.
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Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897