DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 20 are pending for examination.
Examiner’s Note
The prior art rejection below cites particular paragraphs, columns, and/or line numbers in the references for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1 - 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
As to claim 1, the claim recites
A method of operating a cost estimation tool for estimating a cost of implementing an operation unit graph on a reconfigurable processor, comprising:
receiving the operation unit graph comprising a first logical unit that performs a first data operation and has a first port, a second logical unit that performs a second data operation and has a second port, and a logical edge that connects the first port with the second port;
determining a timing group from a predetermined number of timing groups for the logical edge;
determining a first upper bandwidth limit of the first port based on the first data operation;
determining a second upper bandwidth limit of the second port based on the second data operation;
determining a logical edge bandwidth of the logical edge based on the first and second upper bandwidth limits; and
providing the logical edge bandwidth and the timing group as a cost estimation of implementing the operation unit graph on the reconfigurable processor.
Step 2A:
Prong 1: the limitations of " operating a cost estimation tool for estimating a cost of implementing an operation unit graph" and “determining a timing group from a predetermined number of timing groups for the logical edge;
determining a first upper bandwidth limit of the first port based on the first data operation;
determining a second upper bandwidth limit of the second port based on the second data operation;
determining a logical edge bandwidth of the logical edge based on the first and second upper bandwidth limits; and
providing the logical edge bandwidth and the timing group as a cost estimation of implementing the operation unit graph” are all functions that can be reasonably performed in the human mind including observations and with or without the use of pen and paper through observation, evaluation, judgement and opinion.
Prong 2: the additional element of “receiving the operation unit graph comprising a first logical unit that performs a first data operation and has a first port, a second logical unit that performs a second data operation and has a second port, and a logical edge that connects the first port with the second port" is mere data gathering which the courts have held to be insignificant extra-solution activity (see MPEP 2106.05(g)). The additional elements “the additional elements “on the reconfigurable processor” merely recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
Thus, these additional elements do not integrate the judicial exception into a practical application.
Step 2B: the additional element of “receiving the operation unit graph comprising a first logical unit that performs a first data operation and has a first port, a second logical unit that performs a second data operation and has a second port, and a logical edge that connects the first port with the second port" is mere data gathering which the courts have held to be insignificant extra-solution activity (see MPEP 2106.05(g)). The additional elements “the additional elements “on the reconfigurable processor” merely recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
Accordingly, the additional elements do not amount to significantly more than the abstract idea.
As to claim 2. The method of claim 1, wherein the reconfigurable processor comprises arrays of coarse-grained reconfigurable (CGR) units merely recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
As to claim 3. The method of claim 1, wherein one of the first and second logical units comprises a compute unit or a memory unit merely recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
As to claim 4. The method of claim 1, wherein determining the timing group from the predetermined number of timing groups for the logical edge further comprises:
determining whether the logical edge is active during a first execution phase of the operation unit graph or during a second execution phase of the operation unit graph, wherein the first and second execution phases are non-overlapping are functions that can be reasonably carried out in the human mind with the aid of pen and paper, through observation, evaluation, judgment, opinion, thus it is reasonable to identify these limitation as reciting a mental process.
As to claim 5. The method of claim 4, further comprising:
in response to determining that the logical edge is active during the first execution phase, assigning a first timing group of the predetermined number of timing groups to the logical edge; and in response to determining that the logical edge is active during the second execution phase, assigning a second timing group of the predetermined number of timing groups to the logical edge are functions that can be reasonably carried out in the human mind with the aid of pen and paper, through observation, evaluation, judgment, opinion, thus it is reasonable to identify these limitation as reciting a mental process.
As to claim 6. The method of claim 1, wherein the first logical unit comprises assembler code that is associated with the first data operation merely recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
As to claim 7. The method of claim 6, wherein determining the first upper bandwidth limit of the first port based on the first data operation further comprises: determining a pattern in the assembler code merely recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
As to claim 8. The method of claim 7, further comprising:
in response to determining that the pattern in the assembler code comprises a sequence-id based address calculation, determining the first upper bandwidth limit of the first port based on a length of an input first-in first-out (FIFO) buffer of the first port divided by a number of arithmetic logic unit (ALU) stages used for address calculation are functions that can be reasonably carried out in the human mind with the aid of pen and paper, through observation, evaluation, judgment, opinion, thus it is reasonable to identify these limitation as reciting a mental process.
As to claim 9. The method of claim 7, further comprising:
in response to determining that the pattern in the assembler code comprises bubbles in a pipeline of a memory unit, determining the first upper bandwidth limit of the first port based on a number of vectors processed by the memory unit to trigger a token generation divided by a sum of a constant that is based on the bubbles being inserted into the pipeline and the number of vectors processed by the memory unit to trigger the token generation are functions that can be reasonably carried out in the human mind with the aid of pen and paper, through observation, evaluation, judgment, opinion, thus it is reasonable to identify these limitation as reciting a mental process.
As to claim 10. The method of claim 7, further comprising:
in response to determining that the pattern in the assembler code comprises a dequeue operation of a memory unit, determining the first upper bandwidth limit of the first port based on one divided by a number of memory access operations that occur before the memory unit consumes one entry from an input FIFO buffer of the first port are functions that can be reasonably carried out in the human mind with the aid of pen and paper, through observation, evaluation, judgment, opinion, thus it is reasonable to identify these limitation as reciting a mental process.
As to claim 11. The method of claim 7, further comprising:
in response to determining that the pattern in the assembler code comprises a dequeue operation of a compute unit, determining the first upper bandwidth limit of the first port based on one divided by a number of enable signals that flow through a number of arithmetic logic unit (ALU) stages are functions that can be reasonably carried out in the human mind with the aid of pen and paper, through observation, evaluation, judgment, opinion, thus it is reasonable to identify these limitation as reciting a mental process.
As to claim 12. The method of claim 7, further comprising:
in response to determining that the pattern in the assembler code comprises a tail function of a compute unit or a systolic operation of a compute unit, determining the first upper bandwidth limit of the first port based on a number of vectors being processed by the compute unit divided by a sum of a constant and a latency of the compute unit are functions that can be reasonably carried out in the human mind with the aid of pen and paper, through observation, evaluation, judgment, opinion, thus it is reasonable to identify these limitation as reciting a mental process.
As to claim 13, this is a system claim of claim 1. See rejection for claim 1 above.
As to claims 14 - 19, these claims recite similar scope of claims 2 – 7. See rejection for claims 2 – 7 above.
As to claim 20, this is a non-transitory computer-readable storage medium claim of claim 1. See rejection for claim 1 above. Further, the additional elements a non-transitory computer-readable storage medium including instructions and a processing unit merely recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3, 13, 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cascaval et al., (US PUB 2008/02288957 hereinafter Cascaval) in view of Enrici, (US PUB 2022/0253482).
As to claim 1, Cascaval teaches a method of operating a cost estimation tool for estimating a cost (“...cost estimator algorithm...” figure 6 and associated text, especially para. 0058) of implementing an operation unit graph on a [reconfigurable] processor (“..generic graph structure having one or more processing elements at a lowest level in the topology...” para. 0044) and (figures 2-3 shows processor elements), comprising:
receiving the operation unit graph comprising a first logical unit that performs a first data operation (“..generic graph structure having one or more processing elements at a lowest level in the topology...” para. 0044) and has a first port (figure 2A-B shows element Up Port), a second logical unit that performs a second data operation and has a second port (figure 2B show element down ports), [and a logical edge that connects the first port with the second port];
determining a timing group from a predetermined number of timing groups (“...In this class of applications, there are four places where performance can be improved: 1) Computation: the amount of time required to perform the computation; 2) Computation Imbalance: the difference between the longest and shortest compute times per phase; 3) Communication Overhead: the amount of time required to perform communication; and, 4) Communication Imbalance: the difference in time between when the last task finishes communication in a given phase from when the first task finishes...” para. 0033) [for the logical edge];
determining a first upper bandwidth limit of the first port based on the first data operation (“..The switch element's "down ports" models the bandwidth to the lower-level components connected to the switch element. The single "up port" represents how a component communicates with a higher-level switch element. As shown in FIG. 2B, two bandwidths are associated with each port, an "in" bandwidth (pictorially represented as a down arrow) and an "out" bandwidth (pictorially represented as an up arrow). This represents the fact that bidirectional communication through a switch element port can occur in parallel. In addition, each pair of communicating tasks has the full bandwidth of the ports they are using provided no other tasks are using the same ports. If ports are shared between pairs of processing elements, then the port's aggregate bandwidth is bound by the maximal bandwidth of the port.” para. 0044);
determining a second upper bandwidth limit of the second port based on the second data operation (“...The single "up port" represents how a component communicates with a higher-level switch element. As shown in FIG. 2B, two bandwidths are associated with each port... the maximal bandwidth of the port.” para. 0044. Note: up port is second port);
[determining a logical edge bandwidth of the logical edge based on the first and second upper bandwidth limits]; and
providing [the logical edge bandwidth and] the timing group as a cost estimation of implementing the operation unit graph on the [reconfigurable] processor (“...cost estimator algorithm...” figure 6 and associated text, especially para. 0058)
Cascaval does not but Enrici teaches reconfigurable processor (“...a field-programmable gate array (FPGA) architecture that may enable improved memory bandwidth allocation for multi-tenant workloads that execute on FPGA nodes” title and para. 0003); a logical edge and determining a logical edge bandwidth of the logical edge (“...determining a set of groups of edges and nodes in the dependency graph based on the DFST; and means for allocating the memory bandwidth to the set of tasks by allocating the memory bandwidth to edges included in the set of groups of edges and nodes...” para. 0011 – 0013. Note: specification defines logical edges that represents nets in of a graph (para. 0078, 0092). Similarly, Enrici’s edges are connected between two nodes in a graph).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Cascaval by applying the teachings of Enrici because Enrici also teaches determining bandwidth for allocation to graph nodes and edges (para. 0011 – 0013). Enrici provide a configuration processor as another design choice.
As to claim 3, Cascaval modified by Enrici teaches The method of claim 1, Cascaval teaches wherein one of the first and second logical units comprises a compute unit (“...processors...” para. 0046) or a memory unit.
As to claim 13, this is a system claim of claim 1. See rejection for claim 1 above.
As to claim 15, this claim recites similar scope of claim 3. See rejection for claim 3 above.
As to claim 20, this is a non-transitory computer-readable storage medium claim of claim 1. See rejection for claim 1 above. Further, a non-transitory computer-readable storage medium (“...computer readable storage medium...” para. 0045) including instructions and a processing unit (“... the computation unit...” figure 1 and associated text, especially para. 0038).
Claims 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Cascaval in view of Enrici, as applied to claim 1 and 13 and further in view of Lavasani, (US PUB 2017/0024338).
As to claim 2, Cascaval modified by Enrici teaches The method of claim 1, Cascaval and Enrici do not but Lavasani teaches wherein the reconfigurable processor comprises arrays of coarse-grained reconfigurable (CGR) units (“...In an embodiment, in-line accelerator 111 may be implemented using any device known to be used as accelerator, including but not limited to field-programmable gate array (FPGA), Coarse-Grained Reconfigurable Architecture (CGRA)...” para. 0056).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Cascaval and Enrici by applying the teachings of Lavasani because Lavasani would provide multiple types of accelerators including (CGRA). While Enrici teaches similar types of accelerators for the processor can support multiple types of accelerators.
As to claim 14, this claim recites similar scope of claim 2. See rejection for claim 2 above.
Claims 4 - 5 and 16 - 17 are rejected under 35 U.S.C. 103 as being unpatentable over Cascaval in view of Enrici, as applied to claims 1 and 13, and further in view of Fluegel, (US PUB 2013/0318223).
As to claim 4, Cascaval modified by Enrici teaches The method of claim 1, wherein determining the timing group from the predetermined number of timing groups for the logical edge further comprises: Cascaval teaches
determining whether the logical edge is active during a [first execution phase] of the operation unit graph or during [a second execution phase] of the operation unit graph (“..Edges in E denote precedence constraints (dependencies); for instance, edge (x,y) means that task x must be executed before task y...” para. 0028) and (“...Dependency graphs may be annotated. In one example, edges of dependency graphs may be annotated with a positive integer number n that denotes the input/output memory consumed/produced by a node upon execution...” para. 0030),
Cascaval does not but Enrici teaches wherein the [first and second] execution phases are non-overlapping (“...4) Communication Imbalance: the difference in time between when the last task finishes communication in a given phase from when the first task finishes.” Para. 0033).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Cascaval by applying the teachings of Enrici because Enrici would determine schedule of execution for optimal result.
Cascaval and Enrici do not but Fluegel teaches first and second execution phases (“...first execution phase” para. 0016) and (“...second execution phase “ para. 0017) and (“...When running or using the FPGA system 1, in a first phase FPGA configuration files are loaded into each of the FPGAs 2 for programming the FPGAs. Furthermore, resources of the FPGA system are configured, including for example global clocking and resets. Once the FPGAs 2 are programmed during the first phase, a second phase may be started. The second phase is a so-called system configuration phase. In the configuration phase virtual communication channels, in the present specification also called virtual channels, are established and logic units may be preloaded with data if necessary” para. 0029).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Cascaval and Enrici by applying the teachings of Fluegel because Fluegel would provide details of FPGA execution (para. 0029 - 0032). Cascaval would implement details of execution of processor.
As to claim 5, Cascaval modified by Enrici and Fluegel teaches the method of claim 4, further comprising:
in response to determining that the logical edge is active [during the first execution phase] (“..Edges in E denote precedence constraints (dependencies); for instance, edge (x,y) means that task x must be executed before task y...” para. 0028) and (“...Dependency graphs may be annotated. In one example, edges of dependency graphs may be annotated with a positive integer number n that denotes the input/output memory consumed/produced by a node upon execution...” para. 0030), [assigning a first timing group of the predetermined number of timing groups] to the logical edge; and
in response to determining that the logical edge is active [during the second execution phase] (“..Edges in E denote precedence constraints (dependencies); for instance, edge (x,y) means that task x must be executed before task y...” para. 0028), [assigning a second timing group of the predetermined number of timing groups] to the logical edge.
Cascaval does not but Enrici teaches assigning a first timing group of the predetermined number of timing groups to the logical edge and assigning a second timing group of the predetermined number of timing groups to the logical edge (“...4) Communication Imbalance: the difference in time between when the last task finishes communication in a given phase from when the first task finishes.” Para. 0033).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Cascaval by applying the teachings of Enrici because Enrici would determine schedule of execution for optimal result.
Cascaval and Enrici do not but Fluegel teaches first and second execution phases (“...first execution phase” para. 0016) and (“...second execution phase “ para. 0017) and (“...When running or using the FPGA system 1, in a first phase FPGA configuration files are loaded into each of the FPGAs 2 for programming the FPGAs. Furthermore, resources of the FPGA system are configured, including for example global clocking and resets. Once the FPGAs 2 are programmed during the first phase, a second phase may be started. The second phase is a so-called system configuration phase. In the configuration phase virtual communication channels, in the present specification also called virtual channels, are established and logic units may be preloaded with data if necessary” para. 0029).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Cascaval and Enrici by applying the teachings of Fluegel because Fluegel would provide details of FPGA execution (para. 0029 - 0032). Cascaval would implement details of execution of processor.
As to claims 16 - 17, these claims recite similar scope of claims 4 – 5. See rejection for claims 4 – 5 above.
Claims 6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Cascaval in view of Enrici as applied to claim 1, and further in view of Koker et al., (US PAT 6,457,121 hereinafter Koker).
As to claim 6, Cascaval modified by Enrici teaches The method of claim 1, Cascaval and Enrici do not but Koker teaches wherein the first logical unit comprises assembler code that is associated with the first data operation (“...token assembler 540 of figure 5 and associated text).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Cascaval and Enrici by applying the teachings of because Koker’s processor would provide token assembler during data processing to process data address (abstract).
Allowable Subject Matter
Claims 7 – 12 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and overcome 101 rejection.
Conclusion
The prior art made of record but not relied upon request is considered to be pertinent to applicant’s disclosure.
Aibester (US PUB 2023/0138522), discloses a method of bandwidth estimation for operating on shared buffer on Field-Programmable Gate Arrays (FPGA) (title, abstract and figures 1 – 5).
Toy, (US PUB 2021/0306219), discloses a method for optimal resource allocation for Multi-Access Edge Computing (MEC) cluster (title, abstract and figures 1 – 7).
Hasija, (US PUB 2020/0104230), discloses a prediction model including a DAG pipeline estimate resource allocation (title, abstract and figures 1 – 18).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHUONG N HOANG whose telephone number is (571)272-3763. The examiner can normally be reached 9:5-30.
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/PHUONG N HOANG/Examiner, Art Unit 2194 /KEVIN L YOUNG/Supervisory Patent Examiner, Art Unit 2194
Prosecution Insights