DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions Acknowledged
Applicant’s election for examination, without traverse, Invention II directed to a device, Species II-3 of the chosen invention and shown in Fig. 66 in the Response to Restriction Requirements filed on 12/15/25 has been acknowledged. Applicant stated that Claims 1-13 are read on the elected species.
Status of Claims
Claims 14-20 are withdrawn from further consideration as being drawn to a nonelected invention.
Claims 1-13 are examined on merits herein.
Specification
The disclosure is objected to because it is inconsistent with identifying liners while various liners are cited by claims of the application. As such:
paragraphs 0175, 194, 197, 212, 213 identify “first dielectric liner” as 22 (or 22, 26), while earlier paragraphs identify “first dielectric liner” by number 23, and figures of the application have number 23, but do not have number 22 and 26;
paragraph 0175 identifies a third dielectric liner by number 26 and paragraph 0194 identifies a third dielectric liner by number 24, while earlier paragraphs identify a third dielectric liner by number 27. There is no element with number 26 in the drawings.
paragraph 214 refers to: “underlying dielectric liner (22 or 26)”, while there are no elements 22 and 26 in the drawings; there are elements 23 and 27, over which liners 124 and 128 are disposed (in Figs. 63 through 66) by substituting liners 24 and 28 used in other embodiments.
Appropriate corrections/clarifications are required.
Double Patenting
Claims 1 and 9-12 of this application is patentably indistinct from claims 1-5 and 12 of Application No.18/221,689. Pursuant to 37 CFR 1.78(f), when two or more applications filed by the same applicant or assignee contain patentably indistinct claims, elimination of such claims from all but one application may be required in the absence of good and sufficient reason for their retention during pendency in more than one application. Applicant is required to either cancel the patentably indistinct claims from all but one application or maintain a clear line of demarcation between the applications. See MPEP § 822.
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 9-12 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5 and 12 of copending Application No. 18/221,689. Table of Comparison below compares the above claims of both applications.
Table of Comparison
Claims of 18/221,711
Claims of 18/221,689
Comparison, Anticipation or Obviousness
1
1+12
Claims 1 of 18/221,711 has most limitations of claim 1 of 18/221,689, but also has additional limitations directed to a dielectric liner: “a dielectric liner overlying multiple horizontal surface segments and multiple vertical surfaces segments of the stepped surfaces and extending over multiple levels of the of the electrically conductive layers; a retro-stepped dielectric material portion contacting top surface segments of the dielectric liner”.
However, Claim 12 of 18/221,689, dependent on Claim 1, teaches: “at least one dielectric material portion and the stepped surfaces of the of the alternating stack, wherein a horizontal surface of the at least one dielectric linear is located within a same horizontal plane as the annular top surface of the one of the layer contact via structures”. Although Claim 12 does not recite: “multiple vertical surfaces segments of the stepped surfaces”, one of ordinary skill in the art would understand that where one dielectric liner covers all horizontal surfaces of the stepped structure, it would obviously cover all vertical surfaces of the same structure. It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify Claim 1 by adding into this claim the limitations of Claim 12 (as understood above), wherein it is desirable to prevent over-etching a lower disposed layer.
In addition, since all limitations of Claim 1 of 18,221,711 are inherently incorporated into Claim 12, Claim 12 of 18/221,689 makes obvoius all limitations of Claim 1 of 18/221,711.
9
2
Identical language
10
3
Identical language
11
4
Identical language
12
5
Identical language
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Koto et al. (US 2021/0159239).
In re Claim 1, Kato teaches a three-dimensional memory device (paragraph 0003), comprising (Fig. 4):
an alternating stack of insulating layers 23 and electrically conductive layers 24, 25, 26 having stepped surfaces in a contact region (paragraph 0081);
memory openings – for memory pillars MP (paragraph 0066) vertically extending through the alternating stack;
memory opening fill structures (51, 52, 53, 54, 55, as shown in details in Fig. 8, paragraph 0103) located in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements – such as a charge storage 52 - and a respective vertical semiconductor channel – as a semiconductor layer 54;
a dielectric liner 27 (paragraph 0081) overlying multiple horizontal surface segments and multiple vertical surfaces segments of the stepped surfaces and extending over multiple levels of the electrically conductive layers;
a retro-stepped dielectric material portion 28 (paragraph 0081) contacting top surface segments of the dielectric liner 27;
finned (as being a fin to a contact via structure described below) dielectric pillar structures 30 (as shown in details in Figs. 5-7, paragraph 0083) vertically extending through the alternating stack in the contact region; and
layer contact via structures CC (see details in Figs. 5-7, paragraph 0065) vertically extending through the retro-stepped dielectric material portion 28 and contacting a respective one of the electrically conductive layers and a respective one of the finned dielectric pillar structures 30.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kato in view of Shin (US 2023/0343705).
In re Claim 2, Kato teaches the three-dimensional memory device of Claim 1 as cited above, wherein each of an electrically conductive layer has a thickness and a dielectric liner has a thickness – inherently.
Kato does not teach that the dielectric liner has a thickness that is greater than a thickness of the electrically conductive layers. However, Kato teaches that the dielectric liner 27 is used as an (etch) stopper layer (paragraph 0114; see also paragraph 0116 and Fig. 14 explaining a need for an etch stopper 27).
Shin teaches a memory device incorporating an etch stop layer 30 (Fig. 2A, paragraph 0050) where the etch stop layer is thicker than a conductive layer (such as a word line).
Kato and Shin teach analogous arts directed to three-dimensional memories, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Kato device in view of the Shin device, since they are from the same field of endeavor, and the Shin device successfully operates.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to create the dielectric linear thicker than the conductive line (per Shin), wherein such thickness of the etch stop layer is needed for preventing over-etching (Kato, paragraph 0114).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kato in view of Lee et al. (US 2012/0119283).
In re Claim 5, Kato teaches the three-dimensional memory device of Claim 1 as cited above, including the dielectric liner, but does not teach an underlying dielectric liner contacting the multiple horizontal surface segments and the multiple vertical surfaces segments of the stepped surfaces and extending over multiple levels of the electrically conductive layers and under the dielectric liner.
Lee teaches (Fig. 1C) a dielectric liner/etch stopper 120 (paragraph 0085), where the liner comprises multiple layers (paragraph 0090).
Kato and Lee teach analogous arts directed to three-dimensional memories comprised a dielectric liner/etch stopper disposed on the stepped region, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Kato device in view of the Lee device, since they are from the same field of endeavor, and the Lee device successfully operates.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Kato device by substituting a single-layer dielectric liner with a multi-layer dielectric liner, creating by that an underlaying dielectric liner contacting the multiple horizontal surface segments and the multiple vertical surfaces segments of the stepped surfaces and extending over multiple levels of the electrically conductive layers and under the dielectric liner, wherein the manufacturer prefers having a multi-layer dielectric liner over the single-layer dielectric liner: See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kato in view of Su et al. (US 2022/0344496), Murooka (US 2015/0103581), and Kang et al. (US 2017/0358590).
In re Claim 6, Kato teaches the three-dimensional memory device of Claim 1 as cited above.
Kato further teaches (Figs. 4-5) that: each of the finned dielectric pillar structures 30 comprises a first dielectric via liner 32 (paragraph 0085) having a linear vertical cross-sectional profile at each level of the insulating layers 23 that underlies a respective layer contact via structure CC among the layer contact via structures; and each of the first dielectric via liners has a thickness and each of the electrically conductive layers 25 has a thickness.
Kato does not teach that the first dielectric via liner has a laterally-undulating vertical cross-sectional profile that laterally protrudes outward at each level of the insulating layers and does not teach that each of the first dielectric via liners has a thickness less than one half of a thickness of the electrically conductive layers. However, the first dielectric via liner is created as a continuation of a liner for the contact via structure CC and has a same thickness.
Su teaches (paragraph 0050) a thickness of a via liner is chosen from a range of 0.5 nm to 2.5 nm, and Murooka teaches (paragraph 0184) that a thickness of the conductive layer is 10 nm.
Kato, Su, and Murooka teach analogous arts directed to memories, word lines as conductive layers, and contact vias, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Kato device in view of the Su and Murooka devices, since they are from the same field of endeavor, and devices of Su and Murooka successfully operates.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Kato device by creating its first dielectric via liner with a thickness taught by Su and each of the conductive layers with a thickness taught by Murooka, in order to enable thickness of the cited elements, creating by that each of the first dielectric via liners with a thickness that is less than one half of the thickness of the electrically conductive layers.
With the above modifications, Kato/Su/Murooka does not teach that the first dielectric via liner has a laterally-undulating vertical cross-sectional profile and laterally protrudes outward at each level of the insulating layers.
Kang teaches (Fig. 2N) finned dielectric pillar structures 300 (paragraph 0048) comprising at least one dielectric fin 302 (paragraph 0055) that laterally protrudes outward at a level of one of insulating layers 140 (paragraph 0031), while the entire finned dielectric pillar structure has a laterally-undulating vertical cross-sectional profile.
Kato and Kang teach analogous arts directed to three-dimensional memories comprised finned dielectric pillars, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Kato device in view of the Kang device, since they are from the same field of endeavor, and the Kang device successfully operates.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Kato/Su/Murooka device by changing a shape of the finned dielectric pillar per Kang to a shape of the Kang’ finned dielectric pillar structures, when such shape is preferred for the manufacturer: Note that in accordance with MPEP 2144.04. I.B, referencing In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), the court held that changes in shape is not patentable since this is a matter of choice of a person of ordinary skill in the art in absent persuasive evidence that the particular configuration is significant.
Since it is common in the art to dispose a liners along outer walls of an opening and later on depositing a fill material on the liner (as is shown in Figs. 18-19 of Kato), it would have been obvious for one of ordinary skill in the art before filing the application that the first dielectric liner of Kato would repeat a shape of outer walls of the finned structure and would have a laterally-undulating vertical cross-sectional profile (similar to openings profile 155E in the Kang structure 2F before depositing the finned pillar structure material into these openings).
In re Claim 7, Kato/Su/Murooka/Kang teaches the three-dimensional memory device of Claim 6 as cited above, including the first dielectric via liner of Kato.
Kato further teaches (Figs. 4-5) that:
the respective one of the electrically conductive layers 25 comprises a respective opening having a respective cylindrical sidewall that contacts a respective one of the first dielectric via liners 32; and
each of the first dielectric via liners 32 comprises a respective annular top surface contacting a respective one of the layer contact via structures CC (based on Fig. 3 of Kato showing an annular top surface of CC and based on the method of creation of the first dielectric via liners and contact vias).
Claims 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kato in view of Kang.
In re Claim 9, Kato teaches the three-dimensional memory device of Claim 1 as cited above, including the finned dielectric pillar structures, but does not teach that each of the finned dielectric pillar structures comprises at least one dielectric fin that laterally protrudes outward at a level of a respective one of the insulating layers.
Kang teaches (Fig. 2N) finned dielectric pillar structures 300 (paragraph 0048) comprising at least one dielectric fin 302 (paragraph 0055) that laterally protrudes outward at a level of one of insulating layers 140 (paragraph 0031).
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Kato device by substituting its finned dielectric pillar with a pillar having an outer shape of a finned support pillar of Kang (while leaving a dielectric liner 32 on a core 31 of Kato in the new dielectric pillars, as Kato teaches, e.g., preserving a cylindrical structure of the Kato’ dielectric pillar), where a shape of the Kang finned dielectric pillars comprised fins is more desirable either for providing a better support for the memory structure (Kang, paragraph 0048), or because the manufacturer is wishing creating these pillars with the shape taught by Kang: Note that in accordance with MPEP 2144.04. I.B, referencing In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), the court held that changes in shape is not patentable since this is a matter of choice of a person of ordinary skill in the art in absent persuasive evidence that the particular configuration is significant.
In re Claim 10, Kato/Kang teaches the three-dimensional memory device of Claim 9 as cited above, including the dielectric fins of the finned pillars that contact insulating layer of the alternative stack – as Kang teaches.
Kang does not explicitly teach that the at least one dielectric fin comprises a cylindrical sidewall in contact with a respective one of the insulating layers. However, Kang dielectric spacers 304 (Fig. 2M) that are created in a same opening in which the finned dielectric pillars are created (with spacers being higher than the finned pillars). Kang further teaches that the spacers have outer walls aligned with walls of the fins 302 and each spacer has a cylindrical shape (paragraph 0077).
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application that the finned parts of the finned dielectric pillars also have a cylindrical shape, and, as such, their cylindrical sidewalls are in contact with a corresponding one of the insulating layers.
In re Claim 11, Kato/Kang teaches the three-dimensional memory device of Claim 9 as cited above, with a shape of the finned dielectric pillar structures of Kato substituted with the shape of the finned dielectric pillar structure of Kang.
Kato/Kang further teaches (Kang, Fig. 2N) that each of the finned dielectric pillar structures 300 further comprises a dielectric pedestal structure (such as a tubular portion of the finned dielectric pillar, from which fins are distributed) that vertically extends from a substrate 100 underlying the alternating stack to a bottom surface of a respective one of the layer contact via structures (using a definition for the pedestal based on paragraph 0144 of the current application).
In re Claim 12, Kato/Kang teaches the three-dimensional memory device of Claim 11 as cited above, wherein, as shown for Claim 9, a material structure of the finned dielectric pillar is taught by Kato and comprises two layers, while a shape of the finned dielectric pillar is created per Kang and with the pedestal being a tubular portion of the finned pillar structure, as shown for Claim 11.
Kato/Kang further teaches that for each of the finned dielectric pillar structure 30 (Kato, Figs. 4-5):
the at least one dielectric fin (302 in Fig. 2M of Kang) and a tubular portion (304 in Fig. 2M of Kang) of the dielectric pedestal structure (such as a tubular portion that is left from the Kato dielectric finned pillar) comprise a first dielectric fill material 32; and
a cylindrical core portion 31 of the dielectric pedestal structure comprises a second dielectric fill material 9which is different from 31, see paragraph 0085 of Kato).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kato.
In re Claim 13, Kato teaches the three-dimensional memory device of Claim 1, wherein (Fig. 4) each of the layer contact via structures CC comprises a respective annular bottom surface (as is shown in Fig. 3 for a top surface of CC, and based on a method of CC creation shown in Figs. 14-32 and described in paragraphs starting with 0116) contacting an annular top surface segment of the respective one of the electrically conductive layers 24, 25, 26: a segment of a layer being in direct contact with an annular layer is inherently an annular layer (there is no reason creating the via wider than a layer it directly contacts).
Allowable Subject Matter
Claims 3-4 and 8 are objected to since Claims 3 and 7 contain allowable subject matter while being dependent on a rejected base Claim 1, while Claim 4 depends on Claim 3.
Reason for Indicating Allowable Subject Matter
Re Claim 3: Although there are prior arts teaching dielectric layers or liners comprising a seam (the arts include at least Kubo (US 2022/0328413), Sano (US 2022/0189872), Kaminaga (US 10,727248), the examiner found no motivation in substituting the Kato’ dielectric liner having no seam (Kato does not teach a seam) with a dielectric liner/layer comprising a seam.
Re Claim 8: Kato/Su/Murooka/Kang teaching most limitations of Claim 8, does not teach that the second liner is a dielectric liner: for the Kato device, it is essential to have an electrically conductive liner since this liner provides an electrical connection between a contact via and an electrically conductive layer of the alternating stack of the memory device.
Conclusion
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 12/20/25