DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/23/2025 was filed after the mailing date of the non-final rejection on 9/30/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Status
Previous rejection: 1, 2, 6, 7, 10-14 and 20 rejected, 2, 5, 8, and 9 objected, 15-19 allowed
Present rejection: 1, 2, 3, 5 through 19 are allowed, claim 20 is rejected
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shao (US 2012/0013359) in view of Tsujii (US 6351836) in view of Ferreira (US 2005/0099201).
Regarding claim 20.
Shao teaches
A semiconductor wafer (fig 10:1000; [para 0070])configured to be tested by a test assembly comprising a probe card (fig 10:104; [para 0072]), the semiconductor wafer (fig 10:1000; [para 0070]) comprising:
a plurality of semiconductor dies (fig 10:1004,1006,1030; [para 0072]), each comprising integrated circuits (core logic; [para 0073]) and a plurality of die bond pads (fig 10; [para 0071,0072]), the plurality of die bond pads on each semiconductor die (fig 10:1004,1006,1030; [para 0072]) comprising test pads (fig 10; [para 0071]) ;
a first set of scribe lines (fig 10:kerf 1018; [para 0072]) oriented along an x-axis between adjacent semiconductor dies (fig 10:1006,1030; [para 0072]) of the plurality of semiconductor dies (fig 10:1004,1006,1030; [para 0072]);
a second set of scribe lines (fig 10:kerf 1018; [para 0072]) oriented along a y-axis, orthogonal to the x-axis, between adjacent semiconductor dies (fig 10:1004,1006; [para 0072]) of the plurality of semiconductor dies (fig 10:1004,1006,1030; [para 0072]);
a plurality of traces (fig 10; [para 0072]) extending between the test pads of pairs of semiconductor dies of the plurality of semiconductor dies (fig 10:1004,1006,1030; [para 0072]), the plurality of traces (fig 10; [para 0072]) extending into the first and/or second set of scribe lines (fig 10:kerf 1018; [para 0072]), and the plurality of traces electrically coupling like channels (fig 10:TDI,TMS,TCK; [para 0072,0073]) of the test pads of first (fig 10:1006; [para 0071]) and second (fig 10:1030; [para 0071]) dies of the pairs of semiconductor dies pairs together;
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Shao does not teach a voltage pad
Tsujii teaches:
A plurality of die bond pads (fig 1:3; [column 7 lines 1-15])on a semiconductor die (fig 1:2; [column 7 lines 1-15])the plurality of die bond pads (fig 1:3; [column 7 lines 1-15])comprising at least one voltage pad (fig 1:3ab; [column 7 lines 1-15]);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide at least one voltage pad in order to energize the devices which will enable the device to function during test procedures.
Shao does not teach a means for addressing the first semiconductor die uniquely from the second semiconductor die.
Ferreira teaches:
a means for (fig 3:20a; [para 0058]) addressing ([para 0048]) the first semiconductor die (fig 3:3a; [para 0053]) uniquely (unambiguous; [para 0041]) from the second semiconductor die (fig 3:3b; [para 0053]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a unique identifier in order that the test data can be specifically and individually ascribed to a tested die (Ferreira paragraph 7).
Response to Arguments
Applicant’s arguments with respect to claim(s) 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Newly applied combination Shao (US 2012/0013359) in view of Tsujii (US 6351836) in view of Ferreira (US 2005/0099201) anticipates claim 20
Allowable Subject Matter
Claims 1, 2, 3, and 5 through 19 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 1, the prior art does not teach:a semiconductor wafer configured to be tested by a test assembly the plurality of semiconductor dies, the plurality of traces electrically coupling the test pads of first and second dies of the pairs of semiconductor dies pairs together; wherein the voltage pad on a first semiconductor die of a pair of semiconductor dies of the pairs of semiconductor dies is configured to mate with a ground pin on the probe card to distinguish between the first and second semiconductor dies in combination with all other elements of the claim.
Regarding claim 15, the prior art does not teach:a semiconductor die configured to be tested by a test assembly while part of a wafer, wherein the voltage pad is configured to mate with one of a ground pin and power pin on the probe card, the semiconductor die having an address unique from the second semiconductor die, depending on whether the voltage pad is configured to mate with the ground or power pins on the probe card in combination with all other elements of the claim.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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