DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: claims 1 through 3 and 5 through 19 allowed, claim 20 rejected.
Present action: claims 1 through 3 and 5 through 19 rejected, claim 20 allowed.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/15/2026 and 8/26/2026 was filed after the mailing date of the non-final rejection on The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the 5/4/2026 information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 through 3 and 5 through 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the voltage pad" in line 14. There is insufficient antecedent basis for this limitation in the claim. The precent recites “at least one voltage pad” in claim 1 line 5
Claim 3 recites the limitation "the voltage pads" in line 1. There is insufficient antecedent basis for this limitation in the claim. The precedent recites “at least one voltage pad” in claim1 line 5.
Claim 3 recites “a pair of semiconductor dies of the pairs of semiconductor dies” in line 2. However, it is unclear whether this refires to the “a pair of semiconductor dies of the pairs of semiconductor dies” recited in claim 1 line 14.
Claim 5 recites the limitation "the voltage pad" in line 1. There is insufficient antecedent basis for this limitation in the claim. The precent recites “at least one voltage pad” claim 1 line 5
Claim 8 recites the limitation "the voltage pad" in line 1. There is insufficient antecedent basis for this limitation in the claim. The precent recites “at least one voltage pad” claim 1 line 5
Claim 9 recites the limitation "the voltage pad" in line 1. There is insufficient antecedent basis for this limitation in the claim. The precent recites “at least one voltage pad” claim 1 line 5
Claim 15 recites the limitation "the voltage pad" in line 9. There is insufficient antecedent basis for this limitation in the claim. The precent recites “at least one voltage pad” claim 15 line 5
Claim 15 recites “a plurality of severed traces extending from the test pads, the plurality of severed traces configured to couple the test pads of the semiconductor die with a second set of test pads of a second semiconductor die” in lines 6 through 8. The phrase comprises a contradiction, if the traces are severed then the traces are not configured to couple test pads of first and second die, if the traces are configured to couple test pads of first and second die, then they are not severed.
Claims 2 through 14 depend from and incorporate claim 1.
Claims 16 through 19 depend from and incorporate claim 15.
Allowable Subject Matter
Claim 20 is allowed.
Claims 1 through 3 and 5 through 19 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 1, in combination with other elements of the claim, the prior art does not teach a semiconductor wafer configured to be tested by a test assembly a plurality of semiconductor dies, comprising test pads and at least one voltage pad; a plurality of traces extending between the test pads of pairs of semiconductor dies, the plurality of traces extending into the first and/or second sets of scribe lines, and the plurality of traces electrically coupling the test pads of first and second dies of the pairs of semiconductor dies together; wherein the voltage pad on a first semiconductor die of a pair of semiconductor dies of the pairs of semiconductor dies is configured to mate with a ground pin on the probe card to distinguish between the first and second semiconductor dies.
Regarding claim 15, in combination with other elements of the claim, the prior art does not teach a semiconductor die configured to be tested by a test assembly while part of a wafer, a plurality of die bond pads comprising test pads and at least one voltage pad; a plurality of severed traces extending from the test pads; wherein the voltage pad is configured to mate with one of a ground pin and power pin on the probe card, the semiconductor die having an address unique from the second semiconductor die, depending on whether the voltage pad is configured to mate with the ground or power pins on the probe card.
Regarding claim 20, in combination with other elements of the claim, the prior art does not teach a semiconductor wafer configured to be tested by a test assembly a plurality of semiconductor dies, each comprising test pads and at least one voltage pad; a first set of scribe lines; a second set of scribe lines; a plurality of traces extending between the test pads of pairs of semiconductor dies, and the plurality of traces electrically coupling like channels of the test pads of first and second dies of the pairs of semiconductor dies together; and means for selectively addressing the first semiconductor die uniquely from the second semiconductor die.
Response to Arguments
Applicant’s arguments, see remarks, filed 7/29/2026, with respect to 20 have been fully considered and are persuasive. The rejection of claim 20 has been withdrawn.
However new rejections based 35 U.S.C. 112 (pre-AIA ), second paragraph have been applied to claims 1 through 3 and 5 through 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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