DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/3/2025 was filed after the mailing date of the non-final rejection on 10/20/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Previous action: Claims 1 through 20 rejected
Present action: Claims 11 through 16 and 19 rejected, 1 through 10 and 20 allowed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11, 12, 13, 14, 15, 16, and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation "the core addressing pad" in line 12 and in line 13. There is insufficient antecedent basis for this limitation in the claim. The examiner will assume the applicant is referring to the voltage pad.
Claim 11 recites “a plurality of severed traces extending from the test pads, the plurality of severed traces configured to couple the test pads of the semiconductor die with a second set of test pads of a second semiconductor die prior to being severed” in lines 6 through 8.
A severed trace is not configured to couple test pads, and if the trace is configured to connect test pads it is not severed. Further, it is unclear how a severed trace (line 6) can be a severed trace prior to being severed (line 8). The applicant is advised to claim the structure as a whole rather than refer to components that are not part of the structure.
The applicant is advised to claim the structure as a whole rather than refer to components that are not part of the structure.
Claims 12, 13, 14, 15, 16, and 19 depend from and incorporate claim 11.
Response to Arguments
Applicant’s arguments with respect to claim(s) 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 1 through 10 and 20 are allowed.
Claims 11 through 16 and 19 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Regarding claim 1, the prior art does not teach, in combination with other elements of the claim, a semiconductor wafer configured to be tested by a test assembly a plurality of traces extending between the test pads of pairs of semiconductor dies of the plurality of semiconductor dies, the plurality of traces extending into the first and/or second set of scribe lines, and the plurality of traces electrically coupling channels of the test pads of first and second dies of the pairs of semiconductor dies together; and a pull-down resistor coupled to ground and the at least one voltage pad on the first semiconductor dies, the pull-down resistor providing the at least one voltage pad on the first semiconductor dies with a pull down to ground to assign the first semiconductor dies a logical 0 address used to distinguish between the first and second semiconductor dies.
Regarding claim 11, the prior art does not teach, in combination with other elements of the claim, a semiconductor die configured to be tested by a test assembly while part of a wafer, the test assembly comprising a probe card, the semiconductor die comprising: integrated circuits; configured to couple the test pads of the semiconductor die with a second set of test pads of a second semiconductor die prior to being severed; and a pull-down resistor coupled to ground, the pull-down resistor configured to pull the semiconductor die to a logical 0 address when the pull-down resistor is coupled to the at least one voltage pad: wherein the pull-down resistor is electrically coupled to the core addressing pad; and wherein the core addressing pad to which the pull-down resistor is coupled is used to identify the semiconductor die when stacked in a package of multiple semiconductor dies.
Regarding claim 20, the prior art does not teach, in combination with other elements of the claim, a semiconductor wafer configured to be tested by a test assembly comprising a probe card, the semiconductor wafer comprising: a plurality of traces extending between the test pads of pairs of semiconductor dies of the plurality of semiconductor dies, the plurality of traces extending into the first and/or second set of scribe lines, and the plurality of traces electrically coupling channels of the test pads of first and second semiconductor dies of the die pairs of semiconductor dies together; and means for biasing the at least one voltage pad on the first semiconductor dies to assign the first semiconductor dies a logical 0 address used to distinguish between the first and second semiconductor dies.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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