Prosecution Insights
Last updated: April 19, 2026
Application No. 18/222,296

LED MODULE, METHOD OF MANUFACTURING THE SAME, AND LED DISPLAY APPARATUS

Non-Final OA §103§112
Filed
Jul 14, 2023
Examiner
YEMELYANOV, DMITRIY
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
92%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allow Rate
393 granted / 538 resolved
+5.0% vs TC avg
Strong +19% interview lift
Without
With
+18.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
43 currently pending
Career history
581
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
52.4%
+12.4% vs TC avg
§102
23.2%
-16.8% vs TC avg
§112
22.4%
-17.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 538 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species B (Fig. 6A-6-B) in the reply filed on 01/16/2026 is acknowledged. The Examiner notes that Embodiment of Fig. 6A-6E related to method where the openings have a same pitch and different widths and using a single mask. Claims 12-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species F (Fig. 11A-F), there being no allowable generic or linking claim. The Examiner notes that Claims 12 recites “forming a second mask pattern covering the first opening and the second opening, the second mask pattern having a third opening configured to open a third region of the first conductivity-type semiconductor base layer” which is mutually exclusive with single mask present in embodiment of Species B (Fig. 6A-6E). Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species F (Fig. 12A-D), there being no allowable generic or linking claim. The Examiner notes that Claims 17 recites “the first opening has a first width, the second opening has a second width, and the third opening has a third width, and the first width is greater than the second width, and the first width is the same as the third width” which is mutually exclusive with openings have a same pitch and different widths in embodiment of Species B (Fig. 6A-6E). Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 1-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites “simultaneously forming a first light emitting laminate, a second light emitting laminate, and a third light emitting laminate in the first opening, the second opening, and the third opening, respectively, by sequentially growing a first active layer, a second active layer, and a third active layer and the third active layer have a first quantum well layer, a second quantum well layer, and a third quantum well layer emitting light of different wavelengths, respectively”. It is not clear how can the first active layer, a second active layer, and a third active layer can be sequentially grown while a first light emitting laminate, a second light emitting laminate, and a third light emitting laminate are simultaneously formed. For the purposes of examination the examiner will treat the limitation as first active layer, a second active layer, and a third active layer are simultaneously grown. Claims 2-11 are rejected as being dependent on Claim 1 Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-4, 7 and 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugawara (JP 2003158296 A) in view of Tsou et al. (US 2015/0060913 A1). Regarding Claim 1, Sugawara (Fig. 1-6, 18) discloses a method comprising: forming a first conductivity-type semiconductor base layer (“n-type GaN layer 4” ) on a growth substrate (1, 3); forming a mask pattern (2) on the first conductivity-type semiconductor base layer (4), wherein the mask pattern has a first opening (S3), a second opening (s2) and a third opening (S1) having different widths, and the first opening, the second opening and the third opening are arranged with a same pitch (See Fig. 18); simultaneously forming a first light emitting laminate (41, 51, 61), a second light emitting laminate (42, 52, 62), and a third light emitting laminate (43, 53, 63) in the first opening (S3), the second opening (S2), and the third opening (S1), respectively, by sequentially growing a first active layer (53), a second active layer (52), and a third active layer (51) and second conductivity-type semiconductor layers (63, 62, 61) on regions of the first conductivity-type semiconductor base layer (4) opened by the first opening (S3), the second opening (S2), and the third opening (S1), respectively; removing the mask pattern (2) from the first conductivity-type semiconductor base layer (4) (“the SiO .sub.2 film 2 is removed by etching”) (Fig. 8); and forming the first light emitting laminate (43, 53, 63), the second light emitting laminate (42, 52, 62), and the third light emitting laminate (41, 51, 61) is performed by a same growth process, and the first active layer (53), the second active layer (52), and the third active layer (51) have a first quantum well layer, a second quantum well layer, and a third quantum well layer (“multiple quantum well active layers 53, 52, 51”) emitting light of different wavelengths, respectively. (“an active layer having a different thickness and emits light having a different wavelength.”) and (“As a result, the active layers 53, 52 and 51 are grown with the same ratio of TMI and TMG, but the emission wavelength is shortened in the order of Sl, S2 and S3 due to the difference in the layer thickness. You can FIG. 3 shows the relationship between the mask opening width and the emission wavelength when the InGaN quantum well active layer is grown under the above film forming conditions. In the graph of FIG. 3, w represents the stripe width of the SiO .sub.2 mask, and in this embodiment the SiO .sub.2 mask width w is 50 μm. Therefore, the opening widths Sl, S. If S2 and S3 are set to 20 μm, 40 μm, and 200 μm, respectively, the wavelength is 6 from the Sl region in the same film formation time. A red emission of 30 nm is obtained, and the wavelength is 5 from the S2 region. Green emission of 30 nm is obtained, and blue emission of 470 nm wavelength can be obtained from the S3 region.”) Sugawara does not explicitly disclose removing an edge region of each of the first light emitting laminate, the second light emitting laminate, and the third light emitting laminate, Tsou (Fig. 4) discloses removing edge region of a light emitting laminate (D). [0024] It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the a process in Sugawara in view of Tsou such that the process further comprises removing an edge region of each of the first light emitting laminate, the second light emitting laminate, and the third light emitting laminate in order to reduce the probability of making a total reflection of the light and increase a light-emitting scope of the light and enhance light extraction efficiency of the light-emitting diode [0024]. Regarding Claim 2, Sugawara in view of Tsou discloses the method of claim 1, wherein the first opening has a first width, the second opening has a second width, and the third opening has a third width, and the first width is greater than the second width, and the second width is greater than the third width. (“the opening widths Sl, S2, and S3 are set to Sl <S2 <S3”) Regarding Claim 3, Sugawara in view of Tsou discloses the method of claim 2, wherein the first quantum well layer (453) emits light having a wavelength of 440 nm to 480 nm, (“Green emission of 30 nm is obtained, and blue emission of 470 nm wavelength can be obtained from the S3 region.”) the second quantum well layer emits light having a wavelength of 510 nm to 550 nm (thickness t2 of the active layer 52 is 5 nm, green light emission having a wavelength of 530), and the third quantum well layer emits light having a wavelength of 610 nm to 650 nm. (the active layer 53 is formed. 4 when the thickness t3 is 3 nm a blue emission of 70 nm is obtained) Regarding Claim 4, Sugawara in view of Tsou discloses the method of claim 1, wherein the first light emitting laminate, the second light emitting laminate, and the third light emitting laminate include a nitride single crystal laminate (“ the epitaxial growth of the nitride semiconductor layer “ and “n-type GaN layers 41, 42, 43, In Multiple quantum well active layers 51, 52, 53 composed of GaN well layers and GaN barrier layers, p-type AlGaN layers 61, 62, 63, p-type GaN layers 71, 72, 73”), and wherein the first quantum well layer, the second quantum well layer, and the third quantum well layer include nitride single crystal layers satisfying In.sub.xGa.sub.1-xN having different contents of indium (x), respectively. (a multi-quantum well active layer 51, 52, 53 composed of an InGaN well layer and a GaN barrier layer also see difference in width between openings S1, S2, and S3). The Examiner notes that according to originally filed specifications the difference in contents of indium is due to the area sizes of the grown region [0101 of PGPub] “by controlling the area sizes of the grown region for the first to third LED cells LC1, LC2, and LC3, the difference in content of indium may be induced, and accordingly, the first to third light emitting laminates LC1′, LC2′, and LC3′ may be configured to emit light of different wavelengths.” Regarding Claim 7 Sugawara in view of Tsou discloses the method of claim 1, wherein forming the first light emitting laminate, the second light emitting laminate, and the third light emitting laminate includes growing first conductivity-type semiconductor cap layers (43, 42, 41) on the regions of the first conductivity-type semiconductor base layer (43), respectively, before growing the first active layer (43), the second active layer (42), and the third active layer (41). Regarding Claim 9, Sugawara in view of Tsou discloses the method of claim 1, wherein Sugawara in view of Tsou as previously combined does not explicitly disclose removing the edge region includes removing edge regions having different widths from the first light emitting laminate, the second light emitting laminate, and the third light emitting laminate such that the first light emitting laminate, the second light emitting laminate, and the third light emitting laminate have the same width after removing the edge region. However, Tsou (Fig. 1, 3, 5) discloses removing an edge region includes removing edge regions having different widths from a light emitting laminate (See laddered sidewall) and laminate have different width after removing the edge region (width between steps). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the a process in Sugawara in view of Tsou such that the process further comprises removing the edge region includes removing edge regions having different widths from the first light emitting laminate, the second light emitting laminate, and the third light emitting laminate such that the first light emitting laminate, the second light emitting laminate, and the third light emitting laminate have the same width after removing the edge region in order to broaden light-emitting scope of the light emitting from the light-emitting diode, guide a lateral-light emitting from the light-emitting diode to an axial-light emission and reduce the probability of making a total reflection of the light and increase a light-emitting scope of the light and enhance light extraction efficiency of the light-emitting diode and reduce the fabrication cost. [0022, 0024, 0034, 0038]. Regarding Claim 10, Sugawara in view of Tsou discloses the method of claim 1, wherein Sugawara in view of Tsou as previously combined does not explicitly disclose the first light emitting laminate, the second light emitting laminate, and the third light emitting laminate have different widths after the removing the edge region. However, Tsou (Fig. 1, 3, 5) discloses removing a laminate have different width after removing the edge region (width between steps). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the a process in Sugawara in view of Tsou such that the process further the first light emitting laminate, the second light emitting laminate, and the third light emitting laminate have different widths after the removing the edge region in order to broaden light-emitting scope of the light emitting from the light-emitting diode, guide a lateral-light emitting from the light-emitting diode to an axial-light emission and reduce the probability of making a total reflection of the light and increase a light-emitting scope of the light and enhance light extraction efficiency of the light-emitting diode and reduce the fabrication cost. [0022, 0024, 0034, 0038]. Regarding Claim 11, Sugawara in view of Tsou discloses the method of claim 1, further comprising: forming a first electrode layer , a second electrode layer, and a third electrode layer (a mold electrode 8) on upper surfaces of the first light emitting laminate, the second light emitting laminate, and the third light emitting laminate, respectively, (See Fig. 1, 4) to be connected to the second conductivity-type semiconductor layers (43, 62, 61); and forming a common electrode (n-type electrode 9) connected to the first conductivity-type semiconductor base layer. (4) Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugawara (JP 2003158296 A) and in view of Tsou et al. (US 2015/0060913 A1) further in view of Robin (US 2018/0323339 A1) Regarding Claim 5, Sugawara in view of Tsou discloses the method of claim 4, wherein the first opening has a first area (area od S3), the second opening has a second area (area of S2), and the third opening has a third area (area of S1), and the first area is larger than the second area, and the second area is larger than the third area (See Fig. 1-6, 18). Sugawara in view of Tsou further discloses first quantum well layer, the second quantum well layer, the third quantum well layer emit light of different wavelength Sugawara in view of Tsou does not explicitly disclose wherein a content of indium of the first quantum well layer is in a range of 0.15 to 0.2, a content of indium of the second quantum well layer is in a range of 0.25 to 0.3, and a content of indium of the third quantum well layer is in a range of 0.3 to 0.35. Robin discloses variation of indium content in QW layer in reference to green light (“ a conversion into green light, the indium concentration X.sub.2 may be between around 0.22 and 0.25,”) , for red light (“red light, the indium concentration X.sub.2 may be between around 0.3 and 0.4, and for example equal to around 0.35”) and blue light ( indium concentration X.sub.1 may be between around 0.09 and 0.18, and for example equal to around 0.15”) [0031-0033]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the process in Sugawara in view of Tsou and Robin such that a content of indium of the first quantum well layer is in a range of 0.15 to 0.2, a content of indium of the second quantum well layer is in a range of 0.25 to 0.3, and a content of indium of the third quantum well layer is in a range of 0.3 to 0.35 in order to obtain light emitting spectrum corresponding to blue light, green light and red light [0031-0033, 0060-0062, 0071-0073, 0083] Regarding Claim 6 Sugawara in view of Tsou and Robin discloses the method of claim 5, wherein the first quantum well layer has a first thickness, the second quantum well layer has a second thickness, and the third quantum well layer has a third thickness, and the first thickness is greater than the second thickness, and the second thickness is greater than the third thickness. (Fig. 1-6, 18 of Sugawara) Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugawara (JP 2003158296 A) and in view of Tsou et al. (US 2015/0060913 A1) further in view of Schneider Jr. (US 2017/0323925 A1). Regarding Claim 8, Sugawara in view of Tsou discloses the method of claim 1, wherein each of the first light emitting laminate (43,53,63), the second light emitting laminate (42, 52, 62), and the third light emitting laminate includes a nitride single crystal laminate having an upper surface which is a (0001) plane, and wherein the edge region of each of the first light emitting laminate, the second light emitting laminate, and the third light emitting laminate includes an inclined side surface region. ( Sugawara in view of Tsou does not explicitly disclose an upper surface which is a (0001) plane. Schneider, Jr (Fig. 28, 29, 30) discloses having an upper surface which is a (0001) plane. [c-plane; 0072 “c-plane can be parallel to the top surface of the base semiconductor layer 26] It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the process in Sugawara in view of Tsou and Schneider, Jr such that an upper surface which is a (0001) plane in order to obtain epitaxially aligned to one another light emitting diode laminates [0159] Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DMITRIY YEMELYANOV/Examiner, Art Unit 2891
Read full office action

Prosecution Timeline

Jul 14, 2023
Application Filed
Feb 04, 2026
Non-Final Rejection — §103, §112
Mar 10, 2026
Interview Requested
Mar 16, 2026
Applicant Interview (Telephonic)
Mar 16, 2026
Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604565
MICRO LIGHT-EMITTING COMPONENT
2y 5m to grant Granted Apr 14, 2026
Patent 12581773
INDIUM GALLIUM NITRIDE LIGHT EMITTING DIODES WITH REDUCED STRAIN
2y 5m to grant Granted Mar 17, 2026
Patent 12575096
THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME
2y 5m to grant Granted Mar 10, 2026
Patent 12568724
DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Mar 03, 2026
Patent 12568716
WAFER-SCALE SEPARATION AND TRANSFER OF GAN MATERIAL
2y 5m to grant Granted Mar 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
92%
With Interview (+18.7%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 538 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month