Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to an Office action mailed on 09/25/2026 (“09-25-26 OA”), the Applicant substantively amended claims 1, 4, 5 and 15 on 01/06/2026 ("01-06-26 Response”). The Applicant traverses the 112(b) rejection of claim 20 with arguments alone in the 01-06-26 Response.
Currently, claims 1-20 are pending.
Response to Arguments
Applicant’s amendments to claims 5 and 15 have overcome the 35 U.S.C. 112(b) rejection of claim 5 and 15 as set forth on page 2 under line item number 1 of the 09-25-25 OA.
With respect to the 35 U.S.C. 112(b) rejection of claim 20 set forth starting on page 3 of the 09-25-25 OA, the Applicant’s arguments staring on page 6 of the 01-06-26 Response are not persuasive.
On page 7 of the 01-06-26 Response, the Applicant argues that “It would be clear to the skilled artisan that at least the above provides explicit examples of structure(s) in the specification which perform the claimed function of conducting heat from the semiconductor die.” The examiner respectfully disagrees because term “means” per se has a broad structural implication. Here, “means for conducting heat” does not impose any meaningful structural specific structure. Same goes for “means for allowing escape of outgassed material when the semiconductor device is affixed to a host device.”
Furthermore, without the Applicant disclaiming that the claimed means-plus-function limitations will be limited to the specified examples in the Specification (Option (c) on page 6 of the 09-25-25 OA), the scope of the claimed means-plus-function of “means for conducting heat” and “means for allowing escape of outgassed material” cannot be limited to the specified examples. As noted on page 5 of the 09-25-25 OA, without the constraints imposed by 35 U.S.C. 112(f), if claim 20 were to issue, the Applicant will likely argue that claim 20 should not be limited by specified examples of the Specification because one cannot import limitations from the Specification into the claims and that the claims are to be given broader scope that what is imposed by the Specification. Thereby, a zone of uncertainty would be created around what would constitute “means” in “means for conducting heat” and “means for allowing escape of outgassed material.”
Nevertheless, amendments that imbue more structural in the “means” recitations would take it out of the 35 U.S.C. 112(f) purview (see option (a) on page 6 of the 09-25-25 OA).
Despite the Applicant’s amendments to the independent claim 1, the previously-cited Huang still reads on the amended independent claim 1, infra.
On page 8 and 9 of the 01-06-26 OA, the Applicant argues that the examiner erred in considering the limitation of “channels configured to channel outgassed material away from the semiconductor device” as intended use and were given no patentable significance. Examiner respectfully disagrees.
The “configured to” language has been reasonably interpreted as “capable of” and that it was considered in so far as that the channels are functionally capable of channeling outgassed material away from the semiconductor device. As noted on page 9 of the 09-25-25 OA, the blocks 38a’ are spaced apart from each other to define one or more “channels” such that the channels are in fluidic communication or exposed to the surrounding. Thus, the spaced-apart blocks are reasonably capable (functionally speaking) to channel air away from the semiconductor device to dissipate the heat generated by the semiconductor chip 42.
With respect to the 35 U.S.C. 102(a)(1) rejection of the independent claim 13, the Applicant’s arguments on pages 8 and 9 of the 01-06-26 Response are not persuasive for the same reason(s) that the Applicant’s arguments are not persuasive for the independent claim 1, supra.
With respect to the 35 U.S.C. 102(a)(1) rejection of the independent claim 20, the Applicant’s arguments on pages 8 and 9 of the 01-06-26 Response are not persuasive for the same reason(s) that the Applicant’s arguments are not persuasive for the independent claim 1, supra.
For the reasons above, the independent claims 1, 13 and 20 and their respective dependent claims, if any, remain anticipated by Huang.
Claim Rejections - 35 USC § 112
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Limitations of “means for conducting heat from the semiconductor die” and “means for allowing escape of outgassed material when the semiconductor device is affixed to a host device” invoke 35 U.S.C. 112(f).
"35 U.S.C. 112, sixth paragraph {112(f) for AIA } states that a claim limitation expressed in means-plus-function language “shall be construed to cover the corresponding structure…described in the specification and equivalents thereof.” “If one employs means plus function language in a claim, one must set forth in the specification an adequate disclosure showing what is meant by that language. If an applicant fails to set forth an adequate disclosure, the applicant has in effect failed to particularly point out and distinctly claim the invention as required by the second paragraph of section 112.” In re Donaldson Co., 16 F.3d 1189, 1195, 29 USPQ2d 1845, 1850 (Fed. Cir. 1994) (in banc)
The proper test for meeting the definiteness requirement is that the corresponding structure (or material or acts) of a means (or step)-plus-function limitation must be disclosed in the specification itself in a way that one skilled in the art will understand what structure (or material or acts) will perform the recited function. See Atmel Corp. v. Information Storage Devices, Inc., 198 F.3d 1374, 1381, 53 USPQ2d 1225, 1230 (Fed. Cir. 1999). In Atmel, the patentee claimed an apparatus that included a “high voltage generating means” limitation, thereby invoking 35 U.S.C. 112, sixth paragraph. The specification incorporated by reference a non-patent document from a technical journal, which described a particular high voltage generating circuit. The Federal Circuit concluded that the title of the article in the specification may, by itself, be sufficient to indicate to one skilled in the art the precise structure of the means for performing the recited function, and it remanded the case to the district court “to consider the knowledge of one skilled in the art that indicated, based on unrefuted testimony, that the specification disclosed sufficient structure corresponding to the high-voltage means limitation.” Id. at 1382, 53 USPQ2d at 1231." (quoting Section 2174.III of the MPEP).
Here, the written description fails to clearly link or associate the disclosed structure, material, or acts to the claimed function such that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function. Since the Applicant failed to set forth an adequate disclosure, the applicant has in effect failed to particularly point out and distinctly claim the invention as required by 35 U.S.C. 112(b).
Moreover, it is unclear what the corresponding structure(s) of the claimed "means" in the apparent "means-plus-function" limitation of the claimed "means for conducting heat.” Without the Applicant amending the means with corresponding structure(s) or disclaiming that the Applicant wishes to be limited to corresponding structure(s), it is be unclear what the equivalent structure(s) of the claimed "means" would be.
It is also unclear what the corresponding structure(s) of the claimed "means" in the apparent "means-plus-function" limitation of the claimed “means for allowing escape of outgassed material.” Without the Applicant amending the means with corresponding structure(s) or disclaiming that the Applicant wishes to be limited to corresponding structure(s), it is be unclear what the equivalent structure(s) of the claimed "means" would be.
If the independent claim 20 were to issue, without being constrained by the requirements of 35 U.S.C. 112(f), the Applicant will likely argue that the independent claim 20 is not to be limited by the Specification. How would the Courts able to determine under Doctrine of Equivalence, what equivalent structure(s) for "means" are? With such uncertainty, the public would not have the requisite notice to know what "means" would be infringing on the claims.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112, sixth paragraph (that is, replace "means" with a specific structure); or
(b) Amend the written description of the specification such that it clearly links or associates the corresponding structure, material, or acts to the claimed function without introducing any new matter (35 U.S.C. 132(a)) (that is, amend the specification such that there is a clearly link or association between the corresponding structure to the claimed function without introducing any new matter.); or
(c) State on the record where the corresponding structure, material, or acts are set forth in the written description of the specification and linked or associated to the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
If applicant does not wish to have the claim limitation treated under 35 U.S.C. 112(f), applicant may amend the claim so that it will clearly not invoke 35 U.S.C. 112(f), or present a sufficient showing that the claim recites sufficient structure, material, or acts for performing the claimed function to preclude application of 35 U.S.C. 112(f).
If applicant wishes to provide further explanation or dispute the examiner’s interpretation of the corresponding structure, applicant must identify the corresponding structure with reference to the specification by page and line number, and to the drawing, if any, by reference characters in response to this Office action.
For more information, see Supplementary Examination Guidelines for Determining Compliance with 35 U.S.C. § 112 and for Treatment of Related Issues in Patent Applications, 76 FR 7162, 7167 (Feb. 9, 2011).
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-8, 10, 11 and 13-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang (previously-cited Pub. No. US 2020/0279814 A1 to Huang et al.).
Fig. 4 of Huang has been provided to support the rejection below:
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Regarding independent claim 1, Huang teaches a semiconductor device, comprising:
a substrate 1c (para [0120] - “wiring structure 1c”);
a semiconductor die 42 (para [0120] - “a semiconductor chip 42”) mounted on a first side 21 (para [0083] - “top surface 21”) of the substrate 1c;
electrical interconnections 28, 44 (para [0081] - “an outer circuit layer 28”; para [0120] - “a plurality of first connecting elements 44”) or 28, 44, CP, 16 (para [0103] - “through via 16”. Fig. 4 shows an opposing pair of through vias 16.) electrically coupling the semiconductor die 42 to the substrate 1c; and
a pad 38a’ mounted on a second side 32 of the substrate 1c opposite the first side 21, the pad 38a’ (para [0096] - “second lower circuit layer 38a’”) comprising a plurality of discrete thermally conductive blocks 38a’, the blocks 38a’ spaced from each other to define one or more outgassing channels C1 and/or C2 between the blocks 38a’, the pad 38’ configured to channel outgassed material away from the semiconductor device 42 and the one or more outgassing channels C1 and/or C2 configured to channel outgassed material away from the semiconductor device through the one or more outgassing channels (A limitation of “configured to channel outgassed material away from the semiconductor device through the one or more outgassing channels” is directed to an intended use of the blocks that are spaced from each other to define one or more outgassing channels so the limitation does not structurally distinguish the claimed semiconductor device over the semiconductor device taught by Huang. Since Huang teaches the blocks 38a’ spaced from each other to define one or more channels with the channel(s) being exposed to the surrounding, the blocks being spaced apart are reasonably capable of channeling air away from the semiconductor device; see also para [0121] - “…there are two paths (including a first path 90 and a second path 91) to dissipate the heat generated by the semiconductor chip 42 (especially from the active surface 421 of the semiconductor chip 42) to the substrate 46.”).
Regarding claim 2, Huang teaches a plurality of thermal columns 16 (para [0103] - “through via 16”. Fig. 4 shows an opposing pair of through vias 16.) positioned between the semiconductor die 42 on the first side 21 of the substrate 1c and the pad 38a on the second side 32 of the substrate 1c, wherein the plurality of thermal columns 16 are configured to conduct heat away from the semiconductor die 42 (para [0121] - “…there are two paths (including a first path 90 and a second path 91) to dissipate the heat generated by the semiconductor chip 42 (especially from the active surface 421 of the semiconductor chip 42) to the substrate 46.”).
Regarding claim 3, Huang teaches the substrate 1c that comprises first conductive layer 28 (para [0081] - “an outer circuit layer 28”) and second conductive layer 38a’, and wherein the thermal pad 38a’ is formed in the second conductive layer 38a’.
Regarding claim 4, Huang teaches the thermal pad 38a’ that is affixed to the second side of the substrate 1c by a solder 48 (para [0120] - “a plurality of second connecting elements 48”).
Regarding claim 5, Huang teaches the electrical interconnections 28, 44, CP, 16 comprises a first plurality of contact pads 28 on the first side of the substrate 1c, the semiconductor device further comprising a plurality of thermal columns 16 extending between the first and second sides 21, 32 of the substrate 1c, wherein the plurality of thermal columns 16 are configured to conduct heat away from the semiconductor die 42, and wherein the plurality of thermal columns 16 are interspersed with the first plurality of contact pads 28 on the first side 21 of the semiconductor die 42.
Regarding claim 6, Huang teaches a second plurality of contact pads 38a on the second side 32 of the substrate 1c, wherein the second plurality of contact pads 38a are configured to electrically couple the semiconductor device to a host device 46 (para [0125] - “substrate 46 (e.g. a mother board such as a PCB)”).
Regarding claim 7, Huang teaches the pad 38’ that is further configured to physically couple the semiconductor device to the host device 46 (see Fig. 4).
Regarding claim 8, Huang teaches the plurality of thermally conductive blocks 38a’ that are arranged in rows (implicitly another row is more likely than not to be situated in front or behind this cross-sectional view) and columns (Fig. 4 shows 5 columns.) of blocks defining a plurality of outgassing channels.
Regarding claim 10, Huang teaches molding compound 491 (para [0126] - “an underfill 491”) for (partially) encapsulating the semiconductor die 42 and electrical interconnections 44, 28.
Regarding claim 11, Huang teaches the semiconductor die 42 that comprises a controller die (para [0127] discloses that the semiconductor chips 42 are designed to produce high-speed digital signals and RF signals, so the semiconductor chip is reasonably capable of being able to control the high-speed digital signals and RF signals.).
Regarding independent claim 13, Huang teaches a semiconductor device configured to mount on a solder shim of a printed circuit board (A limitation of “configured to mount to a solder shim of a printed circuit board” does not structurally distinguish the claimed semiconductor device over the semiconductor device of Huang, because it is directed to an intended use of the semiconductor device.), the semiconductor device, comprising:
a substrate 1c (para [0120] - “wiring structure 1c”);
a semiconductor die 42 (para [0120] - “a semiconductor chip 42”) mounted on a first side 21 (para [0083] - “top surface 21”) of the substrate 1c; and
a pad 38a’ mounted on a second side 32 of the substrate 1c opposite the first side 21 and configured to mount on the solder shim 48, the pad 38a’ (para [0096] - “second lower circuit layer 38a’”) comprising a plurality of discrete thermally conductive blocks 38a’, the blocks 38a’ spaced from each other to define one or more outgassing channels C1 and/or C2 between the blocks 38a’,
wherein the one or more outgassing channels C1 and/or C2 are configured to provide a pathway to escape outgassed material when the pad 38a’ of the semiconductor device is attached to the solder shim 48 of the printed circuit board 46. (A limitation of “configured provide a pathway to escape outgassed material when the pad of the semiconductor device is attached to the solder shim of the printed circuit board” is directed to an intended use of the blocks that are spaced from each other to define one or more outgassing channels so the limitation does not structurally distinguish the claimed semiconductor device over the semiconductor device taught by Huang. Since Huang teaches the blocks 38a’ spaced from each other to define one or more channels with the channel(s) being exposed to the surrounding, the blocks being spaced apart are reasonably capable of channeling air away from the semiconductor device; see also para [0121] - “…there are two paths (including a first path 90 and a second path 91) to dissipate the heat generated by the semiconductor chip 42 (especially from the active surface 421 of the semiconductor chip 42) to the substrate 46.”) when the pad of the semiconductor device is attached to the solder shim of the printed circuit board.
Regarding claim 14, Huang teaches the pad 38a’ of the semiconductor device is thermally conductive to conduct heat away from the semiconductor die 42 (see Fig. 4).
Regarding claim 15, Huang teaches a set of thermal columns 16 (para [0103] - “through via 16”. Fig. 4 shows an opposing pair of through vias 16.) in the substrate 1c of the semiconductor device, the thermal columns 16 configured to conduct heat from the semiconductor device.
Regarding claim 16, Huang teaches a plurality of solder balls 48 on the second surface 32 of the substrate 1c, the plurality of solder balls 48 configured to mate with contact pads of the printed circuit board upon reflow of the solder shim (A limitation of “configured to mate with contact pads of the printed circuit board upon reflow of the solder shim” does not structurally distinguish the claimed semiconductor device over the semiconductor device of Huang, because it is directed to an intended use of the semiconductor device.).
Regarding claim 17, a limitation of “wherein the pad is configured to physically couple the semiconductor device to the printed circuit board at the solder shim” does not structurally distinguish the claimed semiconductor device over the semiconductor device of Huang, because it is directed to an intended use of the semiconductor device.
Regarding claim 18, Huang teaches the plurality of thermally conductive blocks 38a’ that are arranged in rows (implicitly another row is more likely than not to be situated in front or behind this cross-sectional view) and columns (Fig. 4 shows 5 columns.) of blocks defining a plurality of outgassing channels.
Regarding claim 19, Huang teaches the semiconductor die 42 that comprises a controller die (para [0127] discloses that the semiconductor chips 42 are designed to produce high-speed digital signals and RF signals, so the semiconductor chip is reasonably capable of being able to control the high-speed digital signals and RF signals.).
Regarding independent claim 20, Huang teaches a semiconductor device, comprising:
a substrate 1c (para [0120] - “wiring structure 1c”);
a semiconductor die 42 (para [0120] - “a semiconductor chip 42”) mounted on a first side 21 (para [0083] - “top surface 21”) of the substrate 1c;
electrical interconnections 28, 44 (para [0081] - “an outer circuit layer 28”; para [0120] - “a plurality of first connecting elements 44”) or 28, 44, CP, 16 (para [0103] - “through via 16”. Fig. 4 shows an opposing pair of through vias 16.) electrically coupling the semiconductor die 42 to the substrate 1c; and
means 38a’ (para [0096] - “second lower circuit layer 38a’”) for conducting heat from the semiconductor die 42;
means C1 and/or C2 for allowing escape of outgassed material when the semiconductor device is affixed to host device (A limitation of “for allowing escape of outgassed material when the semiconductor device is affixed to host device” is directed to an intended use of the means so the limitation does not structurally distinguish the claimed semiconductor device over the semiconductor device taught by Huang. Since Huang teaches the blocks 38a’ spaced from each other to define one or more channels with the channel(s) being exposed to the surrounding, the blocks being spaced apart are reasonably capable of channeling air away from the semiconductor device when the semiconductor device is affixed to a host device; see also para [0121] - “…there are two paths (including a first path 90 and a second path 91) to dissipate the heat generated by the semiconductor chip 42 (especially from the active surface 421 of the semiconductor chip 42) to the substrate 46.”).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Huang and further in view of Applicant’s Admission of Prior Art (“AAPA”).
Regarding claim 12, Huang does not disclose a memory die mounted to the substrate to a side of the controller die 42.
Since the Applicant did not particularly and distinctly point out why the Examiner erred in asserting an official notice of the fact that a memory die mounted to a substrate to the side of a controller die is well known in the semiconductor art, said official notice has been taken as AAPA.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the semiconductor device of Huang by providing a memory die to a side of the controller die as taught by AAPA, so as to provide the controller die a function of being able to store information regarding digital signals and/or RF signals.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 9 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 9.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408)918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano, can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL JUNG/Primary Examiner, Art Unit 2817 08 May 2026
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