Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Species I (Figs. 1-4 and 9, Claims 1, 2, 4-13 and 15-20) in the reply filed on 01/26/2026 is acknowledged.
Claims 3 and 14 have withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/26/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/17/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nam et al. (US 2014/0167291).
As for claim 1, Nam et al. disclose in Fig. 1-3 and the related text a semiconductor package, comprising semiconductor structures 200 stacked in a stepwise manner,
wherein each of the semiconductor structures comprises:
a lower structure 7;
an upper structure 10 on the lower structure (Fig. 1); and
an insulating layer 59/54 provided on a bottom surface of the upper structure 10 to be in (thermally) contact with at least a portion of side surfaces of the lower structure 7 (Fig. 1),
wherein an area of the lower structure 7 is smaller than an area of the upper structure 10, when viewed in a plan view (Fig. 3); and a (inner) side surface of the insulating layer 59/54 is vertically aligned to a side surface of the upper structure (Fig. 1).
As for claim 4, Nam et al. disclose the semiconductor package of claim 1, further comprising a supporter 50, which is provided between the side surface of the insulating layer 59 and one of the side surfaces of the lower structure adjacent thereto and is buried in the insulating layer 59 (Fig. 1).
As for claim 9, Nam et al. disclose the semiconductor package of claim 1, further comprising: a substrate 2/3/4, on which the semiconductor structures 7/10 are disposed; bonding wires 41/43 provided to connect a substrate pad 33/31 and chip pads (pads/portion connect to 43), which are respectively disposed on a top surface of the substrate and top surfaces of the semiconductor structures, to each other (Fig. 1); and a mold layer 59 provided on the substrate to cover the semiconductor structures (Fig. 1).
Claims 10, 12-13 and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ye et al. (US 2016/0148918).
As for claim 10, Ye et al. disclose in Figs. 2-4 and the related text a semiconductor package, comprising:
a substrate 104 including substrate pads 120/122 provided on a top surface thereof (Fig. 4);
substrate connection terminals 150/152 provided on a bottom surface of the substrate (Fig. 4);
semiconductor structures (106/a portion of 162 above 106)/108a/108b/108c stacked on the substrate, the semiconductor structures comprising chip pads 130/132 on top surfaces of the semiconductor structures (Fig. 3C);
bonding wires 140/142 connecting the substrate pads 130/132 to the chip pads (Fig. 1); and
a mold layer 116 provided on the substrate to cover the semiconductor structures 106/108a, wherein each of the semiconductor structures comprises:
a lower structure (106/a portion of 162 above 106);
an upper structure 108a disposed on the lower structure, the lower structure (106/a portion of 162 above 106) exposing a portion of a bottom surface of the upper structure (Fig. 3C); and
an insulating layer 310 provided on the exposed portion of the bottom surface of the upper structure (Fig. 4), wherein the semiconductor package further comprises a supporter 162 (Fig. 3C), which is disposed between a side surface of the insulating layer 310 and one of side surfaces of the lower structure and is buried in the insulating layer (Fig. 4.).
As for claim 12, Ye et al. disclose the semiconductor package of claim 10, wherein the side surface of the insulating layer 310 is vertically aligned to a side surface of the upper structure 108a (fig. 4).
As for claim 13, Ye et al. disclose the semiconductor package of claim 10, wherein the insulating layer 310 is provided to cover the side surfaces of the lower structure (Fig. 4).
As for claim 15, Ye et al. disclose the semiconductor package of claim 10, wherein the upper structure 108a comprises a cell array structure [0016], and the lower structure 106 comprises a peripheral circuit structure [0012].
As for claim 16, Ye et al. disclose the semiconductor package of claim 10, wherein each of the semiconductor structures is offset from another one of the semiconductor structures disposed thereunder in a first direction parallel to a top surface of the substrate (Fig. 4).
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 17 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hu (US 2023/0065535).
As for claim 17, Hu disclose in Figs. 1-4 and the related text a semiconductor package, comprising semiconductor structures 200A/200B stacked in a stepwise manner, wherein each of the semiconductor structures comprises:
a cell array structure 200B;
a peripheral circuit structure 200A disposed on the cell array structure (Fig. 1-2); and
an insulating layer (outer 222) provided on the cell array structure to enclose a side surface of the peripheral circuit structure (Fig. 2), wherein the cell array structure 200B comprises:
electrode layers 234 stacked on a first substrate 248;
a channel region 236 provided to vertically penetrate the electrode layers (Fig. 2);
a first interlayer insulating layer 242 covering the electrode layers and the channel region (Fig. 2); and
first chip pads 238/240, which are exposed to an outside of the first interlayer insulating layer 242 and are connected to the electrode layers and the channel region (Fig. 2),
wherein the peripheral circuit structure 200A comprises:
at least one transistor 204/206 provided on a second substrate 202;
a second interlayer insulating layer (inner 222) covering the at least one transistor (Fig. 2); and
second chip pads 228b/228c, which are exposed to an outside of the second interlayer insulating layer and are connected to the transistor (Fig. 2),
wherein the first and second chip pads 238/240/228b/228c are in contact with each other to form a single element (Fig. 2).
As for claim 20, Hu disclose the semiconductor package of claim 17, wherein the cell array structure 200B further comprises a memory cell array [0044], and the memory cell array comprises: cell strings including memory cells; word lines connected to the memory cells, respectively; bit lines connected to the cell strings; and a ground selection line connected to the cell strings (Fig. 1-2).
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 and 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (12,362,323) in view of Park et al. (2013/0147063).
As for claim 1, Chang et al. disclose in Figs. 1-2, 5A-5B and the related text a semiconductor package, comprising semiconductor structures 102/104 stacked in a stepwise manner,
wherein each of the semiconductor structures 102/104 comprises:
a lower structure 102;
an upper structure 104 on the lower structure (Fig. 2); and
an insulating layer 362 provided on a bottom surface of the upper structure 104 to be in contact with at least a portion of side surfaces of the lower structure 102 (Fig. 2),
wherein an area of the lower structure 102 is smaller than an area of the upper structure 104, when viewed in a plan view (Fig. 5A in view of 5B, as looking from top down show an area of the lower structure is smaller than an area of the upper structure).
Chang et al. do not disclose a side surface of the insulating layer is vertically aligned to a side surface of the upper structure.
Park et al. teach in Fig. 14 and the related text a side surface of an insulating layer MD is vertically aligned to a side surface of the upper structure CP1.
Chang et al. and Park et al. are analogous art because they both are directed packaging device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Chang et al. to include the limitations as taught by Park et al., in order to protect the semiconductor device.
As for claim 2, Chang et al. disclose the semiconductor package of claim 1, wherein the insulating layer 362 is provided to enclose the side surfaces of the lower structure 102 (Fig. 2).
As for claim 5, Chang et al. disclose the semiconductor package of claim 1, wherein the insulating layer 362 comprises a material (Col. 6 lines 40-44) whose thermal expansion coefficient is substantially equal to or lower than that of (layer 148 of 104) the upper structure (similar to layer 108, col. 3 lines 25-43).
As for claim 6, Chang et al. disclose the semiconductor package of claim 1, wherein the insulating layer 362 comprises a material (Col. 6 lines 40-44) whose thermal conductivity is higher than that of (layers 114 of 104) the upper structure (Col. 4 lines 10-25).
As for claim 7, Chang et al. disclose the semiconductor package of claim 1, wherein the lower structure comprises a first chip pad 326 provided on a top surface of the lower structure 102, the upper structure comprises a second chip pad 328 provided on a bottom surface of the upper structure 104, and the first and second chip pads are in contact with each other to form a single element (Fig. 2, 5B).
As for claim 8, Chang et al. disclose the semiconductor package of claim 1, wherein the upper structure 104 comprises a cell array structure (Col. 8 lines 60-64), and the lower structure 102 comprises a peripheral circuit structure (Fig. 2 and 5B, Col. 8 lines 60-64).
Claim(s) 11, 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ye et al. or Hu in view of Nam et al..
As for claims 11 and 18-19, Ye et al. or Hu disclose the semiconductor package of claim 10 or 17, except an area of the lower structure is smaller than an area of the upper structure, when viewed in a plan view or an area of the cell array structure is larger than an area of the peripheral circuit structure, when viewed in a plan view; and a side surface of the insulating layer is vertically aligned to the side surface of the peripheral circuit structure.
Nam et al. teach in Fig. 1 and 3 an area of the lower structure 7 is smaller than an area of the upper structure 10, when viewed in a plan view or an area of the cell array structure 10 is larger than an area of the peripheral circuit structure 7, when viewed in a plan view; and a side surface of the insulating layer 50 is vertically aligned to the side surface of the peripheral circuit structure 10.
Ye et al. and Nam et al. are analogous art because they both are directed packaging device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ye et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Ye et al. to include the limitations as taught by Nam et al. in order to achieve the device properties.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811