Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/23/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 10-13 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2019/0244944).
As for claim 10, Lee et al. disclose in Figs. 2A-2B and the related text a semiconductor package, comprising:
a substrate 100 including substrate pads 110 provided on a top surface thereof;
substrate connection terminals 120 provided on a bottom surface of the substrate (Fig. 2B);
semiconductor structures 200 stacked on the substrate, the semiconductor structures comprising chip pads P1/P2/310 on top surfaces of the semiconductor structures (Fig. 2B);
bonding wires 150/350 connecting the substrate pads to the chip pads (Fig. 2B); and
a mold layer 800 provided on the substrate to cover the semiconductor structures (Fig. 2B),
wherein each of the semiconductor structures comprises:
a lower structure 200;
an upper structure 300 disposed on the lower structure, the lower structure exposing a portion of a bottom surface of the upper structure (Fig. 2B); and
an insulating layer 700 provided on an exposed portion of the bottom surface of the upper structure to be in (thermally/electrically) contact with at least a portion of side surfaces of the lower structure (Fig. 2B),
wherein the semiconductor package further comprises a supporter 710, which is disposed between a side surface of the insulating layer and one (left) of the side surfaces of the lower structure and is buried in the insulating layer (Fig. 2B),
wherein a material of the insulating layer 700 is different from a material of the mold layer 800 (fig. 2B, [0036] and [0038]).
As for claim 11, Lee et al. disclose the semiconductor package of claim 10, wherein an area of the lower structure 200 is smaller than an area of the upper structure 300, when viewed in a plan view (Fig. 2A).
As for claim 12, Lee et al. disclose the semiconductor package of claim 10, wherein the side surface of the insulating layer 700 is vertically aligned to a side surface of the upper structure 300 (Fig. 2B).
As for claim 13, Lee et al. disclose the semiconductor package of claim 10, wherein the insulating layer 700 is provided to cover the side surfaces of the lower structure 200 (Fig. 2B).
As for claim 16, Lee et al. disclose the semiconductor package of claim 10, wherein each of the semiconductor structures is offset from another one of the semiconductor structures disposed thereunder in a first direction parallel to a top surface of the substrate (Fig. 2B).
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2 and 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 9,859,245) in view of Lee et al. (US 2019/0244944).
As for claim 1, Chen et al. disclose in Fig. 1A-1J and the related text a semiconductor package, comprising:
semiconductor structures 130b/170 stacked in a stepwise manner,
wherein each of the semiconductor structures comprises:
a lower structure 130;
an upper structure 170 on the lower structure (Fig. 1J); and
an insulating layer 140/150 provided on a bottom surface of the upper structure 170 to be in (thermally) contact with at least a portion of side surfaces of the lower structure 130b (Fig. 1J); and
a mold layer 240 being around a periphery of the semiconductor structures (Fig. 1J),
wherein an area of the lower structure 130 is smaller than an area of the upper structure 170 (Fig. 1J); and
wherein a (upper) side surface of the insulating layer 140/150 is vertically aligned to a (lower) side surface of the upper structure (Fig. 1J),
wherein a material of insulating layer is different from a material of the mold layer (Fig. 1J, col. 3 lines 14-15, col. 7 lines 6-8).
Chen et al. do not disclose an area of the lower structure is smaller than an area of the upper structure, when viewed in a plan view.
Lee et al. teach in Figs. 2A-2B and the related text an area of the lower structure 200 is smaller than an area of the upper structure 300, when viewed in a plan view (Fig. 2A).
Chen et al. and Lee et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Chen et al. to include the limitations as taught by Lee et al., in order to achieved device properties.
As for claim 2, Chen et al. disclose the semiconductor package of claim 1, wherein the insulating layer 140/150 is provided to enclose the side surfaces of the lower structure 102 (Fig. 2).
As for claim 4, Chen et al. disclose the semiconductor package of claim 1, further comprising a supporter (another 130), which is provided between the side surface of the insulating layer 140/150 and one of the side surfaces of the lower structure adjacent thereto and is buried in the insulating layer (Fig. 1J).
As for claim 5, Chen et al. disclose the semiconductor package of claim 1, wherein the insulating layer comprises a material whose thermal expansion coefficient is substantially equal to or lower than that of the upper structure (col. 3 lines 14-15, col. 3 lines 54-67, and col. 4 lines 1-14).
As for claim 6, Chen et al. disclose the semiconductor package of claim 1, wherein the insulating layer comprises a material whose thermal conductivity is higher than that of the upper structure (col. 3 lines 14-15, col. 3 lines 54-67, and col. 4 lines 1-14).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Lee et al. and further in view of Chang et al. (12,362,323 as disclosed in previous office action).
As for claims 7-8, Chen et al. disclose the semiconductor package of claim 1, wherein the lower structure 130 comprises a first chip pad 138 provided on a top surface of the lower structure, the upper structure 170 comprises a second chip pad 178.
Chen et al. do not teach the second chip pad provided on a bottom surface of the upper structure, and the first and second chip pads are in contact with each other to form a single element; and the upper structure 104 comprises a cell array structure, and the lower structure comprises a peripheral circuit structure.
Chang et al. teach in Fig. 2 and 5B an upper structure comprises a second chip pad 328 provided on a bottom surface of the upper structure 104, and the first and second chip pads are in contact with each other to form a single element (Fig. 2, 5B), wherein the upper structure 104 comprises a cell array structure (Col. 8 lines 60-64), and the lower structure 102 comprises a peripheral circuit structure (Fig. 2 and 5B, Col. 8 lines 60-64).
Chen et al. and Chang et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Chen et al. to include the limitations as taught by Chang et al. in order to improve bonding characteristics of packaging devices.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Lee et al. and further in view of Nam et al. (US 2014/0167291, as disclosed in previous office action).
As for claim 9, Lee et al. disclose the semiconductor package of claim 1, further comprising: a substrate 230, on which the semiconductor structures are disposed (Fig. 1A-1J);
Chen et al. do not disclose bonding wires provided to connect a substrate pad and chip pads, which are respectively disposed on a top surface of the substrate and top surfaces of the semiconductor structures, to each other.
Nam et al. teach in Fig. 1 and the related text bonding wires 41/43 provided to connect a substrate pad 33/31 and chip pads (pads/portion connect to 43), which are respectively disposed on a top surface of the substrate and top surfaces of the semiconductor structures, to each other (Fig. 1).
Chen et al. and Nam et al. are analogous art because they both are directed packaging structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Chen et al. to include the limitations as taught by Nam et al. in order to improve interconnections.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. in view of Ye et al. (US 2016/0148918, as disclosed in previous office action).
As for claim 15, Lee et al. disclose semiconductor package of claim 10, except the upper structure comprises a cell array structure, and the lower structure comprises a peripheral circuit structure.
Ye et al. teach in Fig. 4 and the related text an upper structure 108a comprises a cell array structure [0016], and the lower structure 106 comprises a peripheral circuit structure [0012].
Lee et al. and Ye et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Lee et al. to include the limitations as taught by Ye et al., in order to achieve greater storage capacity.
Claim(s) 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. in view of Hu (US 2023/0065535).
As for claims 17 and 20, Lee et al. disclose in Figs. 2A-2B and the related text a semiconductor package, comprising:
semiconductor structures 200/300/400 stacked in a stepwise manner, and
a mold layer 800 being around a periphery of the semiconductor structures (Fig. 2B),
wherein each of the semiconductor structures comprises:
a cell array structure 300/400 [0030];
a peripheral circuit structure 200 [0022] disposed on the cell array structure (fig. 2B); and
an insulating layer 700 provided on a top (lower) surface of the cell array structure to be in (electrically/thermally) contact with at least a portion of side surfaces of the peripheral circuit structure to enclose a side surface of the peripheral circuit structure (fig. 2B), wherein a material of the insulating layer 700 is different from a material of the mold layer 800 (fig. 2B, [0036] and [0038]).
Lee et al. do not disclose the cell array structure comprises: electrode layers stacked on a first substrate; a channel region provided to vertically penetrate the electrode layers; a first interlayer insulating layer covering the electrode layers and the channel region; and first chip pads, which are exposed to an outside of the first interlayer insulating layer and are connected to the electrode layers and the channel region, wherein the peripheral circuit structure comprises: at least one transistor provided on a second substrate; a second interlayer insulating layer covering the at least one transistor; and second chip pads, which are exposed to an outside of the second interlayer insulating layer and are connected to the transistor, wherein the first and second chip pads are in contact with each other to form a single element; and wherein the cell array structure further comprises a memory cell array, and the memory cell array comprises: cell strings including memory cells; word lines connected to the memory cells, respectively; bit lines connected to the cell strings; and a ground selection line connected to the cell strings.
Hu disclose in Figs. 1-4 and the related text a cell array structure 200B comprises:
electrode layers 234 stacked on a first substrate 248;
a channel region 236 provided to vertically penetrate the electrode layers (Fig. 2);
a first interlayer insulating layer 242 covering the electrode layers and the channel region (Fig. 2); and
first chip pads 238/240, which are exposed to an outside of the first interlayer insulating layer 242 and are connected to the electrode layers and the channel region (Fig. 2),
wherein the peripheral circuit structure 200A comprises:
at least one transistor 204/206 provided on a second substrate 202;
a second interlayer insulating layer (inner 222) covering the at least one transistor (Fig. 2); and
second chip pads 228b/228c, which are exposed to an outside of the second interlayer insulating layer and are connected to the transistor (Fig. 2),
wherein the first and second chip pads 238/240/228b/228c are in contact with each other to form a single element (Fig. 2),
wherein the cell array structure 200B further comprises a memory cell array [0044], and the memory cell array comprises: cell strings including memory cells; word lines connected to the memory cells, respectively; bit lines connected to the cell strings; and a ground selection line connected to the cell strings (Fig. 1-2).
Lee et al. and Hu are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Lee et al. to include the limitations as taught by Hu, in order to achieve greater storage capacity of memory device (Hu: [0002]).
As for claim 18, Lee et al. disclose the semiconductor package of claim 17, wherein an area of the cell array structure 300/400 is larger than an area of the peripheral circuit structure 200, when viewed in a plan view (Fig. 2A).
As for claim 19, Lee et al. disclose the semiconductor package of claim 17, wherein a side surface of the insulating layer 700 is vertically aligned to the side surface of the peripheral circuit structure 200 (fig. 2B).
Response to Arguments
Applicant’s arguments with respect to claim(s) above have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811
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