DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement of Amendment
Applicant amendment filed 04/28/26 has been acknowledged.
Applicant submitted a few replacement figures and amended a few paragraphs of the specification to overcome objections to the drawings and specification presented by the Non-Final Rejection mailed 01/28/26. Applicant further amended Claims 1, 5, 14, and 20.
Status of Claims
Claims 1-20 are examined on merits herein.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 4 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
In re Claim 4: Claim 4 recites: “the one or more coils comprise a plurality of coils”. The recitation is unclear, since the current application does not teach one coil comprising a plurality of coils.
In accordance with MPEP 2173.03 Correspondence Between Specification and Claims [R-07.2022], inconsistence of the claim with the specification makes the claim indefinite, even though the terms of a claim may appear to be definite: see In re Cohn 438 F.2d 989, 169 USPQ 95 (CCPA 1971).
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited recitation of Claim 4 was interpreted as: “the inductive loop comprises a plurality of coils”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
As far as Claim 4 is understood, Claims 1-5 and 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi et al. (US 2003/0127704) in view of Kamath et al. (US 2013/0063234).
In re Claim 1, Kobayashi teaches a semiconductor die, comprising (Figs. 15-16 paragraph 0123):
a first surface – as a top surface of layer 45,
a second surface – as a bottom surface of layer 41, and
a depth (inherently existing) between the first and second surfaces;
a contact pad 21 (paragraph 0126) formed in the first surface of the semiconductor die (e.g., “formed in an upper part of the semiconductor die”, in accordance with the claim interpretation);
a through silicon via 48 (paragraph 0125) formed through the second surface of the semiconductor die extending through the depth toward the first surface; and
an inductive loop 20 (paragraph 0123) formed in the depth of the semiconductor die, the inductive loop 20 comprising:
one or more coils of spirally wound electrically conductive material (e.g., copper, paragraph 0077),
a first end of the inductive loop coupled to the contact pad 21 (paragraph 0126), and
a second end of the inductive loop coupled to the through silicon via 48 (paragraph 0125), wherein
signals transmitted between the contact pad and the through silicon via pass through the inductive loop, as Fig. 15 clearly shows.
Kobayashi does not teach a first electrical connector electrically coupling the first end of the inductive loop to the contact pad and does not teach a second electrical connector electrically coupling the second end of the inductive loop to the through silicon via, since the inductor of Kobayashi does not have any connectors coupled to its ends.
Kamath teaches (paragraph 0018) that a planar inductor can comprise first and second connectors, in addition, to the planar inductor itself, where the first and second connectors are used for electrical connection of the inductor and are, obviously, coupled to the first and second ends of the inductor.
Kobayashi and Kamath teach analogous arts directed to planar inductors, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Kobayashi semiconductor die in view of the Kamath teaching, since they are from the same field of endeavor, and Kamath created a successfully operated inductor.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Kobayashi semiconductor die by substituting its inductor comprising no first and second electrical connectors coupled to the first and second ends of the inductor - with the inductive coop comprised first and second electrical connectors coupled to the loop first and second ends and coupling these ends to the contact pad and the through via, accordingly, creating by that a structure the inductive loop of which comprises the first electrical connector FC and the second electrical connector SC, as shown in Annotated Fig. 15, wherein the manufacturer prefers using the inductive loop having first and second electrical connectors. See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
Annotated Fig. 15
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In re Claim 2, Kobayashi/Kamath teaches the semiconductor die of Claim 1 as cited above.
Kobayashi further teaches (as Figs. 15-16 show) the one or more coils are planar.
In re Claim 3, Kobayashi/Kamath teaches the semiconductor die of Claim 1 as cited above.
Kobayashi further teaches (Fig. 16) that the semiconductor die comprises a metallization layer, wherein the inductive loop 20 is formed in the metallization layer of the semiconductor die.
For the embodiment of Figs. 15-16, Kobayashi does not teach that the semiconductor die comprises metallization layers (e.g., more than one metallization layer). However, Kobayashi teaches another embodiment (Fig. 6, paragraphs 0096-0098) in which an inductive loop comprises electrically connected coils disposed in two different metallization layers.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Kobayashi/Kamath die of Fig. 16 by substituting its single metallization layer with a plurality of metallization layers and an inductor disposed in these metallization layers (the inductor, obviously, comprised first and second electrical connectors), wherein it is desirable having an inductor with a higher inductance (Kobayashi, paragraph 0098). See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 4, Kobayashi/Kamath teaches the semiconductor die of Claim 1 as cited above.
Kobayashi teaches (Fig. 16) that the semiconductor die comprises a metallization layer in which the coils 20 is formed.
For the embodiment of Figs. 15-16, Kobayashi does not teach a plurality of metallization layers, wherein the inductor is disposed in these metallization layers. However, Kobayashi teaches another embodiment (Fig. 6, paragraphs 0096-0098) comprised two stacked metallization layers and an inductor comprising electrically connected coils 20A, 20B disposed in these different metallization layers.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Kobayashi embodiment of Figs. 15-16 by substituting its single metallization layer with a single coil with a plurality of metallization layers and an inductor disposed in the metallization layers, wherein it is desirable having an inductor with a higher inductance (Kobayashi, paragraph 0098). See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 5, Kobayashi/Kamath teaches the semiconductor die of Claim 1 as cited above, including the contact pad, the inductance loop, and the first and second electrical connectors, as shown in Annotated Fig. 15.
Based on Annotated Fig. 15, the inductance loop is positioned to the side of the contact pad.
In re Claim 10, Kobayashi/Kamath teaches the semiconductor die of Claim 1 as cited above.
Kobayashi further teaches (Fig. 16) that the inductive loop 20 is positioned at a depth that is equal to a depth of a base of the through silicon via 48.
In re Claim 11, Kobayashi/Kamath teaches the semiconductor die of Claim 1 as cited above.
Kobayashi further teaches (Fig. 16) that the inductance loop 20 is positioned at a depth that is greater than a depth of the contact pad 21 and less than a depth of a base of the TSV 48.
In re Claim 12, Kobayashi/Kamath teaches the semiconductor die of Claim 1 as cited above.
Kobayashi/Kamath further teaches (Annotated Fig. 15) that the first electrical connector FC comprises one or more of a conductive trace and a via – based on Annotated Fig. 15, it comprised a trace.
In re Claim 13, Kobayashi/Kamath teaches the semiconductor die of Claim 1 as cited above.
Kobayashi/Kamath further teaches (Annotated Fig. 15) that the second electrical connector SC comprises one or more of a conductive trace and a via – based on Annotated Fig. 15, SC comprises a trace.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi/Kamath in view of Kabir et al. (US 2023/0260935).
In re Claim 6, Kobayashi/Kamath teaches the semiconductor die of Claim 1 as cited above, including first and second electrical connectors of the inductive loop (as shown in Annotated Fig. 15), which make it unclear whether or not the inductance loop 20 is positioned beneath the contact pad.
Kabir teaches (Fig. 2C) a semiconductor die in which an inductor coil 256 (paragraph 0040) is position beneath a contact pad 240 (paragraph 0032).
Kobayashi/Kamath and Kabir teach analogous arts directed to semiconductor dies comprised inductors electrically connected to contact pads through electrical connectors, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Kobayashi/Kamath die in view of the Kabir die, since they are from the same field of endeavor, and Kabir created a successfully operating die.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Kobayashi/Kamath semiconductor die of Claim 1 by positioning the inductance loop beneath the contact pad, if such disposition of the pad and the loop is desirable. Note that in accordance with MPEP 2144.04 VI. C: Rearrangement of Parts, the court has held that rearrangement of parts (in the particular case, changing the position of the package at 90o) that would not modify the device operation is unpatentable because it requires only ordinary skill in the art: In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi/Kamath in view of Yen et al. (US 2011/0291232).
In re Claim 7, Kobayashi/Kamath teaches the semiconductor die of Claim 1 as cited above, wherein inductance loop 20 comprises a spiral.
Kobayashi/Kamath does not teach that the inductance loop 20 of Figs. 15-16 comprises a center-tap spiral comprised a plurality of coils.
Yen teaches (Figs. 3A-3B, paragraphs 0031-0032) an inductance loop being a center-tap spiral comprised a plurality of coils (one comprised a half of ring 80a and another comprised a half of ring 80b), and where portions of each coil are disposed in different metal levels – such as in metallization layer 40 and a metallization layer 82, and in a metallization layer 83.
Kobayashi/Kamath and Yen teach analogous arts directed to inductance loops, including inductance loops disposed in multiple metallization layers, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Kobayashi/Kamath semiconductor die in view of the Yen teaching, since they are from the same field of endeavor, and Yen created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Kobayashi/Kamath semiconductor die of Claim 1 by substituting its inductance loop with the inductance loop of Yen (with added first and second electrical connectors), if a structure Yen inductance loop is preferred by the manufacturer: See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 8, Kobayashi/Kamath/Yen teaches the semiconductor die of Claim 7 as cited above, wherein, as shown for Claim 7, portions of the plurality of coils are positioned at different depths (at different metallization layers/levels) within the semiconductor die.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi/Kamath in view of Ito et al. (US 2010/0078790).
In re Claim 9, Kobayashi/Kamath teaches the semiconductor die of Claim 1 as cited above, including the inductance loop and the contact pad, but does not teach that the inductance loop is positioned at a depth that is less than or equal to a depth of the contact pad.
Ito teaches a semiconductor die (Fig. 8) comprised an inductor 17 (paragraph 0034) that is positioned at a depth that is equal to a depth of a contact pad 16 (paragraph 0033).
Kobayashi/Kamath and Ito teach analogous arts directed to semiconductor dies comprised an inductor and a contact pad, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Kobayashi/Kamath die in view of the Ito teaching, since they are from the same field of endeavor, and Ito created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Kobayashi/Kamath semiconductor die of Claim 1 by positioning the inductance loop at the same depth as the contact pad (per Ito), while electrically connecting the inductor loop with the contact pad (per Kobayashi), if such dispositions of the contact pad and the inductor loop is preferred for the manufacturer. Note that in accordance with MPEP 2144.04 VI. C: Rearrangement of Parts, the court has held that rearrangement of parts (in the particular case, changing the position of the package at 90o) that would not modify the device operation is unpatentable because it requires only ordinary skill in the art: In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Saraswat et al. (US 2014/0183691) in view of Ito.
In re Claim 20, Saraswat teaches a semiconductor die, comprising (Fig. 3 and Annotated Part of Fig. 3, where the die is represented by a top die of a stack of two dies):
a contact pad – Pad (as in Annotated Part of Fig. 3) - formed over a first surface (which is a top surface of 335) of the semiconductor die, wherein the contact pad comprises a high frequency signal pad used for input/output signal transfer (paragraph 0031);
Annotated Part of Fig. 3
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a through silicon via – TSV (as in Annotated Part of Fig. 3) formed through a second surface (which is a bottom surface) of the semiconductor die, opposed to the first surface, the through silicon via TSV extending through a depth of the semiconductor die toward the first surface, and
means – such as an inductor 380 (paragraph 0033) - electrically coupled to the contact pad and through silicon via, for storing current in a magnetic field (which is inherent for any inductor) to distribute capacitance within the semiconductor die – inherently: A limitation: “to distribute capacitance within the semiconductor die” is a functional language limitation, while the structure of Saraswat, incorporating a capacitor in its via - has all claimed elements. In accordance with MPEP 2112.01 Composition, Product, and Apparatus Claims. I. PRODUCT AND APPARATUS CLAIMS — WHEN THE STRUCTURE RECITED IN THE REFERENCE IS SUBSTANTIALLY IDENTICAL TO THAT OF THE CLAIMS, CLAIMED PROPERTIES OR FUNCTIONS ARE PRESUMED TO BE INHERENT: “
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Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977), wherein
signals transmitted between the contact pad and the through silicon via pass through the means for storing current (e.g., through the inductor, as Annotated Fig. 3 shows).
Saraswat does not teach that the contact pad is formed in a first surface of the semiconductor die, e.g., in accordance with the claim interpretation. – is formed in an upper part of the semiconductor die.
Ito teaches (Fig. 8, paragraph 0033) a contact pad 16 formed in an upper part of a semiconductor die 100a.
Saraswat and Ito teach analogous arts directed to a semiconductor die comprised an inductor and a contact pad, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Saraswat die in view of Ito die, since they are from the same field of endeavor, and Ito created a successfully operating die.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Saraswat die by disposing the contact pad in the upper part of the semiconductor die (not over the die), wherein such modification is beneficial for mechanical reliability of attachment between the contact pad and other parts of the die.
Response to Arguments
Applicant’ arguments (REMARKS, filed 04/28/26) have been fully considered.
Examiner agrees with the amendments to the drawings and specification (REMARKS, pages 12-13).
Examiner agrees with Applicant (REMARKS, page 13) that amendments to most of the claims removed grounds for rejections under 35 U.S.C. 112(b), except for Claim 14. The current Office Action shows an alternative language to be used for potential amendment to Claim 4.
Examiner disagrees that new limitations to Claims 1 and 20 remove grounds for rejection of these independent Claims under 35 U.S.C. 103 using the same prior arts that were used by the Non-Final Rejection and, accordingly, disagrees with allowability of claims dependent on Claim 1, as the current Office Action shows (REMARKS, pages 13-17). However, the amended Claim 14 and claims dependent on Claim 14 are patentable.
Allowable Subject Matter
Claims 14-19 are allowed.
Reason for Indicating Allowable Subject Matter
Re Claim 14: The prior arts of record fail(s) to anticipate or render obvious such combination of limitations, as interpreted, as: “the through silicon via of a first semiconductor die of the plurality of semiconductor dies is physically and electrically coupled with the contact pad of a second semiconductor die positioned immediately below the first semiconductor die” and: “each semiconductor die comprising a contact pad formed at an upper part of the semiconductor die, a through silicon via formed through a second surface of the semiconductor die, opposite to the first surface”… and “an inductive loop formed in the depth of the semiconductor die”:
Examiner found no prior arts of record anticipating Claim 14, and, although there are combinations of prior arts of record teaching, in combination, all limitations of the claim, there is no motivation for combining these prior arts. As such, a combination of references of Kobayashi and Kamath teaches all limitations related to a semiconductor die, as shown for Claim 1, but these prior arts do not teach a stack of semiconductor dies with the above-cited first limitation. Ito teaches a stack of semiconductor dies united together using pads and vias, but there is no motivation combining Kobayashi and Ito, since the Kobayashi reference is related to miniaturizing a semiconductor die (with no motivation of combining multiple dies), while the Ito reference is related to a large-scale integration. Moreover, a combination of Saraswat, Kamath, and Ito also teaches all limitations of Claim 14. However, it is impossible to modify the Saraswat/Kamath die to comply with the limitation related to connection of TSV and pads of different dies, since such modification would prevent the TSV of Saraswat to function as a capacitor, violating by that operation of each Saraswat die. Other prior arts of record, cited by the current Office Action earlier, as well as the prior arts of record listed below, do not cure the above deficiency, where the other prior arts include: Jang et al. (US 2023/0420439), Marek et al. (US 2020/0295727), Chen et al. (US 2016/0035670), and Bakalski et al. (US 2015/0311922).
Re Claims 15-19: Claims 15-19 are allowed due to dependency on Claim 14.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 06/01/26
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