DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are examined on merits herein.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the feature(s) canceled from the claim(s).
“metallization layers”, cited by Claims 3, 4.
“inductance loop is positioned at a depth… greater than or equal to a depth of a base of the through silicon via”, as Claim 10 claims.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a) because they fail to show TSV (through silicon vias) 120 as described in the specification with respect to Figs. 5A and 5B (see paragraphs 0033-0034 of a published application US 2024/0213151). Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Paragraphs 0033 and 0034 of the published application, describing Figs. 5A and 5B, refers to a TSV 120. However, Figs. 5A and 5B show no TSV 120.
Paragraph 0035 identifies by number 130 a bit bus box and a TSV, while other paragraphs associate TSVs with number 120.
Specification is contradictory with respect to inductor loops, traces (connectors), and vias. As such, paragraph 0035 of the published application states that a bit bus box 130 contains an inductive loop 110 and electrical connections 140, 160, and 180 (which are elements not including into 110). But paragraph 0038 states that the inductance loop 110 includes coils (which is obvious), as well as traces 114, 118, and vias 116. Paragraph 0036 of the published application states that coils of the inductance loop are coupled to the contact pad 108 with a trace 114; paragraph 0037 has a statement similar to that of paragraph 0036. Paragraph 0059 states that an inductive loop comprises coils and two electrical connectors for coupling to a contact pad and to a TSV, accordingly.
Appropriate corrections/clarifications are required.
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Claim 1 recites (line 4): “a contact pad formed in the first surface of the semiconductor die”, which is not supported by the specification of the current application, teaching (paragraph 0036 of the published application), with the reference to Fig. 6, that the contact pad has a depth, while it is known that a surface does not have a depth.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
In re Claim 1: Claim 1 recites (line 4): “a contact pad formed in the first surface of the semiconductor die”. The recitation is unclear, since conflicts with the specification of the application, teaching (paragraph 0036 of the published application, referring to Fig. 6) that a contact pad has a depth, while it is known that a surface does not have a depth – this is a two-dimensional element and a pad is a three-dimensional element.
In accordance with MPEP 2173.03 Correspondence Between Specification and Claims [R-07.2022], inconsistence of the claim with th7e specification makes the claim indefinite, even though the terms of a claim may appear to be definite: see In re Cohn 438 F.2d 989, 169 USPQ 95 (CCPA 1971).
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited recitation was interpreted as: “a contact pad formed in an upper part of the semiconductor die”.
In re Claim 1: Claim 1 recites (lines 8-11): “the inductive loop comprising: one or more coils of spirally wound electrically conductive material, a first electrical connector electrically coupling a first end of the inductive loop to the contact pad, and a second electrical connector electrically coupling a second end of the inductive loop to the through silicon via”. The recitation is unclear with respect to first and second electrical connectors, since paragraph 0035 of the published application, teaches, as is shown in the objection to the specification, that the inductive loop has only coils.
In accordance with MPEP 2173.03 Correspondence Between Specification and Claims [R-07.2022], inconsistence of the claim with the specification makes the claim indefinite, even though the terms of a claim may appear to be definite: see In re Cohn 438 F.2d 989, 169 USPQ 95 (CCPA 1971).
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited recitation of Claim 1 was interpreted as originally filed, e.g., in compliance with paragraph 0038 of the published application (and in the assumption that paragraph 0035 will be appropriately corrected).
In re Claim 4: Claim 4 recites: “the one or more coils comprise a plurality of coils”. The recitation is unclear, since the current application does not teach one coil comprising a plurality of coils.
In accordance with MPEP 2173.03 Correspondence Between Specification and Claims [R-07.2022], inconsistence of the claim with the specification makes the claim indefinite, even though the terms of a claim may appear to be definite: see In re Cohn 438 F.2d 989, 169 USPQ 95 (CCPA 1971).
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited recitation of Claim 4 was interpreted as: “the one or more coils belong to a plurality of coils”.
In re Claim 5: Claim 5 recites: “the inductance loop is positioned to the side of the contact pad”. There is a lack of antecedent basis for citing “side” with an article “the”, since “side” of the contact pad was not cited earlier by Claim 5 or by Claim 1 (on which Claim 5 depends).
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited limitation was interpreted as: “the inductance loop is positioned to a side of the contact pad”.
In re Claims 2 and 6-13: Claims 2 and 6-13 are rejected under 35 U.S.C. 112(b) due to dependency on Claim 1.
In re Claim 14: Line 3 of Claim 14 has a same issue as line 4 of Claim 1, and lines 8-12 of Claim 14 has a same issue as lines 8-11 of Claim 1; for this Office Action, the above-cited recitations of Claim 14 were interpreted similar to the corresponding interpretations of Claim 1.
In re Claims 15-19: Claims 15-19 are rejected under 35 U.S.C. 112b due to dependency on Claim 14.
In re Claim 20: Line 2 of Claim 20 has a same issue as line 4 of Claim 1, and for this Office Action, it was interpreted similar to interpretation of line 4 of Claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
As far as the claims are understood, Claims 1-5 and 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi et al. (US 2003/0127704) in view of Kamath et al. (US 2013/0063234).
In re Claim 1, Kobayashi teaches a semiconductor die, comprising (Figs. 15-16 paragraph 0123):
a first surface – as a top surface of layer 45,
a second surface – as a bottom surface of layer 41, and
a depth (inherently existing) between the first and second surfaces;
a contact pad 21 (paragraph 0126) formed in the first surface of the semiconductor die (e.g., “formed in an upper part of the semiconductor die”, in accordance with the claim interpretation);
a through silicon via 48 (paragraph 0125) formed through the second surface of the semiconductor die extending through the depth toward the first surface; and
an inductive loop 20 (paragraph 0123) formed in the depth of the semiconductor die, the inductive loop 20 comprising:
one or more coils of spirally wound electrically conductive material (e.g., copper, paragraph 0077),
a first end of the inductive loop coupled to the contact pad 21 (paragraph 0126), and
a second end of the inductive loop coupled to the through silicon via 48 (paragraph 0125).
Kobayashi does not teach a first electrical connector electrically coupling the first end of the inductive loop to the contact pad and does not teach a second electrical connector electrically coupling the second end of the inductive loop to the through silicon via, since the inductor of Kobayashi does not have any connectors coupled to its ends.
Kamath teaches (paragraph 0018) that a planar inductor can comprise first and second connectors, in addition, to the planar inductor itself, where the first and second connectors are used for electrical connection of the inductor and are, obviously, coupled to the first and second ends of the inductor.
Kobayashi and Kamath teach analogous arts directed to planar inductors, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Kobayashi semiconductor die in view of the Kamath teaching, since they are from the same field of endeavor, and Kamath created a successfully operated inductor.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Kobayashi semiconductor die by substituting its inductor comprising no first and second electrical connectors coupled to the first and second ends of the inductor - with the inductive coop comprised first and second electrical connectors coupled to the loop first and second ends and coupling these ends to the contact pad and the through via, accordingly, creating by that a structure the inductive loop of which comprises the first electrical connector FC and the second electrical connector SC, as shown in Annotated Fig. 15, wherein the manufacturer prefers using the inductive loop having first and second electrical connectors. See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
Annotated Fig. 15
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In re Claim 2, Kobayashi/Kamath teaches the semiconductor die of Claim 1 as cited above.
Kobayashi further teaches (as Figs. 15-16 show) the one or more coils are planar.
In re Claim 3, Kobayashi/Kamath teaches the semiconductor die of Claim 1 as cited above.
Kobayashi further teaches (Fig. 16) that the semiconductor die comprises a metallization layer, wherein the inductive loop 20 is formed in the metallization layer of the semiconductor die.
For the embodiment of Figs. 15-16, Kobayashi does not teach that the semiconductor die comprises metallization layers (e.g., more than one metallization layer). However, Kobayashi teaches another embodiment (Fig. 6, paragraphs 0096-0098) in which an inductive loop comprises electrically connected coils disposed in two different metallization layers.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Kobayashi/Kamath die of Fig. 16 by substituting its single metallization layer with a plurality of metallization layers and an inductor disposed in these metallization layers (the inductor, obviously, comprised first and second electrical connectors), wherein it is desirable having an inductor with a higher inductance (Kobayashi, paragraph 0098). See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 4, Kobayashi/Kamath teaches the semiconductor die of Claim 1 as cited above.
Kobayashi teaches (Fig. 16) that the semiconductor die comprises a metallization layer in which the coils 20 is formed.
For the embodiment of Figs. 15-16, Kobayashi does not teach a plurality of metallization layers, wherein the inductor is disposed in these metallization layers. However, Kobayashi teaches another embodiment (Fig. 6, paragraphs 0096-0098) comprised two stacked metallization layers and an inductor comprising electrically connected coils 20A, 20B disposed in these different metallization layers.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Kobayashi embodiment of Figs. 15-16 by substituting its single metallization layer with a single coil with a plurality of metallization layers and an inductor disposed in the metallization layers, wherein it is desirable having an inductor with a higher inductance (Kobayashi, paragraph 0098). See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 5, Kobayashi/Kamath teaches the semiconductor die of Claim 1 as cited above, including the contact pad, the inductance loop, and the first and second electrical connectors, as shown in Annotated Fig. 15.
Based on Annotated Fig. 15, the inductance loop is positioned to the side of the contact pad.
In re Claim 10, Kobayashi/Kamath teaches the semiconductor die of Claim 1 as cited above.
Kobayashi further teaches (Fig. 16) that the inductive loop 20 is positioned at a depth that is equal to a depth of a base of the through silicon via 48.
In re Claim 11, Kobayashi/Kamath teaches the semiconductor die of Claim 1 as cited above.
Kobayashi further teaches (Fig. 16) that the inductance loop 20 is positioned at a depth that is greater than a depth of the contact pad 21 and less than a depth of a base of the TSV 48.
In re Claim 12, Kobayashi/Kamath teaches the semiconductor die of Claim 1 as cited above.
Kobayashi/Kamath further teaches (Annotated Fig. 15) that the first electrical connector FC comprises one or more of a conductive trace and a via – based on Annotated Fig. 15, it comprised a trace.
In re Claim 13, Kobayashi/Kamath teaches the semiconductor die of Claim 1 as cited above.
Kobayashi/Kamath further teaches (Annotated Fig. 15) that the second electrical connector SC comprises one or more of a conductive trace and a via – based on Annotated Fig. 15, SC comprises a trace.
As far as the claims are understood, Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi/Kamath in view of Kabir et al. (US 2023/0260935).
In re Claim 6, Kobayashi/Kamath teaches the semiconductor die of Claim 1 as cited above, including first and second electrical connectors of the inductive loop (as shown in Annotated Fig. 15), which make it unclear whether or not the inductance loop 20 is positioned beneath the contact pad.
Kabir teaches (Fig. 2C) a semiconductor die in which an inductor coil 256 (paragraph 0040) is position beneath a contact pad 240 (paragraph 0032).
Kobayashi/Kamath and Kabir teach analogous arts directed to semiconductor dies comprised inductors electrically connected to contact pads through electrical connectors, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Kobayashi/Kamath die in view of the Kabir die, since they are from the same field of endeavor, and Kabir created a successfully operating die.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Kobayashi/Kamath semiconductor die of Claim 1 by positioning the inductance loop beneath the contact pad, if such disposition of the pad and the loop is desirable. Note that in accordance with MPEP 2144.04 VI. C: Rearrangement of Parts, the court has held that rearrangement of parts (in the particular case, changing the position of the package at 90o) that would not modify the device operation is unpatentable because it requires only ordinary skill in the art: In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950).
As far as the claims are understood, Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi/Kamath in view of Yen et al. (US 2011/0291232).
In re Claim 7, Kobayashi/Kamath teaches the semiconductor die of Claim 1 as cited above, wherein inductance loop 20 comprises a spiral.
Kobayashi/Kamath does not teach that the inductance loop 20 of Figs. 15-16 comprises a center-tap spiral comprised a plurality of coils.
Yen teaches (Figs. 3A-3B, paragraphs 0031-0032) an inductance loop being a center-tap spiral comprised a plurality of coils (one comprised a half of ring 80a and another comprised a half of ring 80b), and where portions of each coil are disposed in different metal levels – such as in metallization layer 40 and a metallization layer 82, and in a metallization layer 83.
Kobayashi/Kamath and Yen teach analogous arts directed to inductance loops, including inductance loops disposed in multiple metallization layers, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Kobayashi/Kamath semiconductor die in view of the Yen teaching, since they are from the same field of endeavor, and Yen created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Kobayashi/Kamath semiconductor die of Claim 1 by substituting its inductance loop with the inductance loop of Yen (with added first and second electrical connectors), if a structure Yen inductance loop is preferred by the manufacturer: See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 8, Kobayashi/Kamath/Yen teaches the semiconductor die of Claim 7 as cited above, wherein, as shown for Claim 7, portions of the plurality of coils are positioned at different depths (at different metallization layers/levels) within the semiconductor die.
As far as the claims are understood, Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi/Kamath in view of Ito et al. (US 2010/0078790).
In re Claim 9, Kobayashi/Kamath teaches the semiconductor die of Claim 1 as cited above, including the inductance loop and the contact pad, but does not teach that the inductance loop is positioned at a depth that is less than or equal to a depth of the contact pad.
Ito teaches a semiconductor die (Fig. 8) comprised an inductor 17 (paragraph 0034) that is positioned at a depth that is equal to a depth of a contact pad 16 (paragraph 0033).
Kobayashi/Kamath and Ito teach analogous arts directed to semiconductor dies comprised an inductor and a contact pad, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Kobayashi/Kamath die in view of the Ito teaching, since they are from the same field of endeavor, and Ito created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Kobayashi/Kamath semiconductor die of Claim 1 by positioning the inductance loop at the same depth as the contact pad (per Ito), while electrically connecting the inductor loop with the contact pad (per Kobayashi), if such dispositions of the contact pad and the inductor loop is preferred for the manufacturer. Note that in accordance with MPEP 2144.04 VI. C: Rearrangement of Parts, the court has held that rearrangement of parts (in the particular case, changing the position of the package at 90o) that would not modify the device operation is unpatentable because it requires only ordinary skill in the art: In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950).
As far as the claim is understood, Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Saraswat et al. (US 2014/0183691) in view of Ito.
In re Claim 20, Saraswat teaches a semiconductor die, comprising (Fig. 3 and Annotated Part of Fig. 3, where the die is represented by a top die of a stack of two dies):
Annotated Part of Fig. 3
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a contact pad – Pad (as in Annotated Part of Fig. 3) - formed over a first surface (which is a top surface of 335) of the semiconductor die, wherein the contact pad comprises a high frequency signal pad used for input/output signal transfer (paragraph 0031);
a through silicon via – TSV (as in Annotated Part of Fig. 3) formed through a second surface (which is a bottom surface) of the semiconductor die, opposed to the first surface, the through silicon via TSV extending through a depth of the semiconductor die toward the first surface, and
means – such as an inductor 380 (paragraph 0033) - electrically coupled to the contact pad and through silicon via, for storing current in a magnetic field (which is inherent for any inductor) to distribute capacitance within the semiconductor die – inherently: A limitation: “to distribute capacitance within the semiconductor die” is a functional language limitation, while the structure of Saraswat, incorporating a capacitor in its via - has all claimed elements. In accordance with MPEP 2112.01 Composition, Product, and Apparatus Claims. I. PRODUCT AND APPARATUS CLAIMS — WHEN THE STRUCTURE RECITED IN THE REFERENCE IS SUBSTANTIALLY IDENTICAL TO THAT OF THE CLAIMS, CLAIMED PROPERTIES OR FUNCTIONS ARE PRESUMED TO BE INHERENT: “
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Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Saraswat does not teach that the contact pad is formed in a first surface of the semiconductor die, e.g., in accordance with the claim interpretation. – is formed in an upper part of the semiconductor die.
Ito teaches (Fig. 8, paragraph 0033) a contact pad 16 formed in an upper part of a semiconductor die 100a.
Saraswat and Ito teach analogous arts directed to a semiconductor die comprised an inductor and a contact pad, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Saraswat die in view of Ito die, since they are from the same field of endeavor, and Ito created a successfully operating die.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Saraswat die by disposing the contact pad in the upper part of the semiconductor die (not over the die), wherein such modification is beneficial for mechanical reliability of attachment between the contact pad and other parts of the die.
Allowable Subject Matter
As far as the claim is interpreted, Claim 14 contains allowable subject matter.
Reason for Indicating Allowable Subject Matter
Re Claim 14: The prior arts of record fail(s) to anticipate or render obvious such combination of limitations, as interpreted, as: “the through silicon via of a first semiconductor die of the plurality of semiconductor dies is physically and electrically coupled with the contact pad of a second semiconductor die positioned immediately below the first semiconductor die” and: “each semiconductor die comprising a contact pad formed in an upper part of the semiconductor die, a through silicon via formed through a second surface of the semiconductor die, opposite to the first surface”… and an inductive loop formed in the depth of the semiconductor die”: Examiner found no prior arts of record anticipating Claim 14, and, although there are combinations of prior arts of record teaching, in combination, all limitations of the claim, there is no motivation for combining these prior arts. As such, a combination of references of Kobayashi and Kamath teaches all limitations related to a semiconductor die, as shown for Claim 1, but these prior arts do not teach a stack of semiconductor dies with the above-cited first limitation. Ito teaches a stack of semiconductor dies united together using pads and vias, but there is no motivation combining Kobayashi and Ito, since the Kobayashi reference is related to miniaturizing a semiconductor die (with no motivation of combining multiple dies), while the Ito reference is related to a large-scale integration. Moreover, a combination of Saraswat, Kamath, and Ito also teaches all limitations of Claim 14. However, it is impossible to modify the Saraswat/Kamath die to comply with the limitation related to connection of TSV and pads of different dies, since such modification would prevent the TSV of Saraswat to function as a capacitor, violating by that operation of each Saraswat die. Other prior arts of record, cited by the current Office Action earlier, as well as the prior arts of record listed below, do not cure the above deficiency, where the other prior arts include: Jang et al. (US 2023/0420439), Marek et al. (US 2020/0295727), Chen et al. (US 2016/0035670), and Bakalski et al. (US 2015/0311922).
Conclusion
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 11/09/25