DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 01/16/2025 and 09/24/2025 have been considered.
Drawings
The drawings filed on 07/17/2023 are acceptable.
Specification
The abstract of the disclosure and the specification filed on 07/17/2023 are acceptable.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang US 2020/0411484 in view of McElrea US 2008/0303131.
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Regarding claim 1, Jang (US 2020/0411484) discloses:
A semiconductor die stack comprising:
a first semiconductor die (110, ¶0021), comprising:
a first surface (the first surface includes RDL 120, ¶0021), a second surface opposed to the first surface, an edge (110b, ¶0022) extending between the first and second surfaces, and a first group of conductive pads (CP2, ¶0022) distributed across the first surface, the first group of conductive pads (CP2) configured to flip chip mount to a host device (via external terminals 130, ¶0025);
a second semiconductor die (210, ¶0026), comprising:
a third surface (the third surface includes RDL 220, ¶0026), a fourth surface opposed to the third surface, and a second group of conductive pads (PAD1, ¶0028) in a row on the third surface adjacent an edge of the second semiconductor die (210), wherein the second surface of the first semiconductor die (110) is affixed to the third surface of the second semiconductor die (210) with an offset leaving the second group of conductive pads (PAD1) on the third surface exposed; and
a plurality of conductive elements (BW1, ¶0081) electrically coupling like channels of conductive pads in the first (CP2) and second groups of conductive pads (PAD1), a conductive element of the plurality of conductive elements comprising: a first portion affixed to the first surface of the first semiconductor die (110), and a third portion affixed to a conductive pad of the second group of conductive pads and the third surface of the second semiconductor die (210)..
Jang does not disclose “a plurality of conductive traces electrically coupling like channels of conductive pads in the first and second groups of conductive pads, a conductive trace of the plurality of conductive traces comprising: a first portion affixed to the first surface of the first semiconductor die, a second portion affixed to the edge between the first and second surfaces of the first semiconductor die, and a third portion affixed to a conductive pad of the second group of conductive pads and the third surface of the second semiconductor die”.
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In a similar device, however, McElrea (US 2008/0303131) discloses a semiconductor die stack comprising a first die (lowest chip 42 in figures 4a-7) comprising a first surface, a second surface opposed to the first surface, an edge (49, ¶0071) extending between the first and second surfaces, and a first group of conductive pads (48, ¶0071), a second semiconductor die (42 above the lowest chip 42) comprising a third surface and a second group of conductive pads (48) in a row on the third surface adjacent an edge of the second semiconductor die (42, ¶0071), wherein the second surface of the first semiconductor die is affixed to the third surface of the second semiconductor die with an offset leaving the second group of conductive pads (42) on the third surface exposed, a plurality of conductive traces (62, 72 ¶0080) electrically coupling like channels of conductive pads (48) in the first (48) and second groups of conductive pads (48) a conductive trace of the plurality of conductive traces comprising a first portion affixed to the first surface of the first semiconductor die, a second portion affixed to the edge between the first and second surfaces of the first semiconductor die, and a third portion affixed to a conductive pad of the second group of conductive pads and the third surface of the second semiconductor die (¶0079)”. McElrea discloses that a device as taught provides an assembly with improved stacking arrangements (¶0070). Therefore, it would have been obvious to one having skill in the art before the effective filing date of the claimed invention to modify the device of Jang, including providing a conductive trace of the plurality of conductive traces comprising a first portion affixed to the first surface of the first semiconductor die, a second portion affixed to the edge between the first and second surfaces of the first semiconductor die, and a third portion affixed to a conductive pad of the second group of conductive pads and the third surface of the second semiconductor die in order to provide an improved stacking arrangement as taught by McElrea.
Regarding claim 2, the modification of McElrea further discloses:
wherein the first portion of the conductive trace (72) are directly affixed to the first surface of the first semiconductor die (pad 48 is on the first surface of chip 42).
Regarding claim 3, the modification of McElrea further discloses:
the first semiconductor die further comprising:
a third group of conductive pads (CP2)in a row on the first surface adjacent the edge of the first semiconductor die, and a redistribution layer (SP2, ¶0023) electrically coupling the first group of conductive pads (CP2) distributed across the first surface to the third group of conductive pads in the row at the edge of the first surface.
Regarding claim 4, the modification of McElrea further discloses:
wherein the first portion of the conductive trace (72) is physically coupled to what would be a conductive pad in the third group of conductive pads of Jang.
Regarding claim 5, the modification of McElrea further discloses:
A molding compound encapsulating at least portions of the first semiconductor die, the molding compound leaving exposed the first group of conductive pads on the first surface (¶0090).
Regarding claim 6, the modification of McElrea further discloses:
wherein the conductive trace (72) has a width less than or equal to a width of a conductive pad of the first group of conductive pads (figure 6a, figure 7).
Regarding claim 7, Jang further discloses:
a plurality of conductive bumps (130, ¶0025) applied to the first group of conductive pads (CP1), wherein the plurality of conductive bumps enable flip chip mounting of the first group of conductive pads to the host device (¶0025).
Regarding claim 8, the modification of McElrea further discloses:
wherein the plurality of conductive traces are formed by additive manufacturing (¶0079).
Regarding claim 9, the modification of McElrea further discloses:
wherein the plurality of conductive traces are formed by screen printing (¶0018).
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Regarding claim 10, Jang discloses:
A semiconductor device comprising:
one or more semiconductor die stacks, each semiconductor die stack of the one or more semiconductor dies stacks comprising:
a first semiconductor die (110), comprising:
a first surface, a second surface opposed to the first surface, a first edge extending between the first and second surfaces, and a first group of conductive pads distributed across the first surface, the first group of conductive pads (122, ¶0022) configured to flip chip mount to a host device (‘external device”, ¶0022);
one or more second semiconductor dies (210), a second semiconductor die of the one or more second semiconductor dies comprising: a third surface, a fourth surface opposed to the third surface, a second edge extending between the third and fourth surfaces, a second group of conductive pads (222) in a row on the third surface adjacent an edge of the second semiconductor die, wherein the second surface of the first semiconductor die is affixed to the third surface of the second semiconductor die with an offset leaving the second group of conductive pads (222) on the third surface exposed; and
a plurality of conductive elements (BW1) electrically coupling like channels of conductive pads in the first (122) and second groups (222) of conductive pads a conductive element of the plurality of conductive elements comprising: a first portion affixed to the first surface of the first semiconductor die (122), and a third portion affixed to a conductive pad (222) of the second group of conductive pads and the third surface of the second semiconductor die”.
.Jang does not disclose “a plurality of conductive traces electrically coupling like channels of conductive pads in the first and second groups of conductive pads, a conductive trace of the plurality of conductive traces comprising: a first portion affixed to the first surface of the first semiconductor die, a second portion affixed to the edge between the first and second surfaces of the first semiconductor die, and a third portion affixed to a conductive pad of the second group of conductive pads and the third surface of the second semiconductor die”.
In a similar device, however, McElrea (US 2008/0303131) discloses a semiconductor die stack comprising a first die (lowest chip 42 in figures 4a-7) comprising a first surface, a second surface opposed to the first surface, an edge (49, ¶0071) extending between the first and second surfaces, and a first group of conductive pads (48, ¶0071), a second semiconductor die (42 above the lowest chip 42) comprising a third surface and a second group of conductive pads (48) in a row on the third surface adjacent an edge of the second semiconductor die (42, ¶0071), wherein the second surface of the first semiconductor die is affixed to the third surface of the second semiconductor die with an offset leaving the second group of conductive pads (42) on the third surface exposed, a plurality of conductive traces (62, 72 ¶0080) electrically coupling like channels of conductive pads (48) in the first (48) and second groups of conductive pads (48) a conductive trace of the plurality of conductive traces comprising a first portion affixed to the first surface of the first semiconductor die, a second portion affixed to the edge between the first and second surfaces of the first semiconductor die, and a third portion affixed to a conductive pad of the second group of conductive pads and the third surface of the second semiconductor die (¶0079)”. McElrea discloses that a device as taught provides an assembly with improved stacking arrangements (¶0070). Therefore, it would have been obvious to one having skill in the art before the effective filing date of the claimed invention to modify the device of Jang, including providing a conductive trace of the plurality of conductive traces comprising a first portion affixed to the first surface of the first semiconductor die, a second portion affixed to the edge between the first and second surfaces of the first semiconductor die, and a third portion affixed to a conductive pad of the second group of conductive pads and the third surface of the second semiconductor die in order to provide an improved stacking arrangement as taught by McElrea.
Regarding claim 11, Jang further discloses:
a third group of conductive pads (CP2) in a row on the first surface adjacent the edge of the first semiconductor die, and a redistribution layer (SP2) electrically coupling the first group of conductive pads distributed across the first surface to the third group of conductive pads in the row at the edge of the first surface.
Regarding claim 12, the modification of McElrea further discloses:
the first portion of the conductive trace is physically coupled to a conductive pad in what would be the third group of conductive pads Of Jang.
Regarding claim 13, Jang further discloses:
wherein the one or more semiconductor die stacks comprise two or more semiconductor die stacks (figure 10).
Regarding claim 14, Jang further discloses:
wherein the one or more one second semiconductor dies comprise a single second semiconductor die (210, figure 1a).
Regarding claim 15, Jang further discloses:
wherein the one or more second semiconductor dies (210) comprise two or more second semiconductor dies (figure 3a, ¶0050).
Regarding claim 16, the modification of McElrea further discloses:
wherein the electrically conductive trace (72) is coupled to like channel conductive pads on each of what would be the second semiconductor dies of the two or more second semiconductor dies of Jang.
Regarding claim 17, the modification of McElrea further discloses:
wherein the first portion of the conductive trace (72) is directly affixed to the first surface of the first semiconductor die (42).
Regarding claim 18, the modification of McElrea further discloses:
wherein the second portion of the conductive trace (72) is directly affixed to the edge of the first semiconductor die between the first and second surfaces (¶0079).
Regarding claim 19, the modification of McElrea further discloses:
wherein the third portion of the conductive trace (72) is directly affixed to the third surface of the second semiconductor die (¶0079).
Regarding claim 20, Jang discloses:
A semiconductor die stack comprising:
a first semiconductor die (110), comprising: a first surface, a second surface opposed to the first surface, an edge extending between the first and second surfaces, and a first group of conductive pads (122) distributed across the first surface, the first group of conductive pads (122) configured to flip chip mount to a host device;
a second semiconductor die (220), comprising: a third surface, a fourth surface opposed to the third surface, and a second group of conductive pads (222) in a row on the third surface adjacent an edge of the second semiconductor die, wherein the second surface of the first semiconductor die (110) is affixed to the third surface of the second semiconductor die (220) with an offset leaving the second group of conductive pads (222) on the third surface exposed; and
conductive means (BW1) for electrically coupling like channels of conductive pads in the first and second groups of conductive pads, the conductive means affixed to the first surface of the first semiconductor die (110) and the third surface of the second semiconductor die (220).
Jang does not disclose “conductive means for electrically coupling like channels of conductive pads in the first and second groups of conductive pads, the conductive means affixed to the first surface of the first semiconductor die, the edge of the first semiconductor die between the first and second surfaces, and the third surface of the second semiconductor die” in a similar device, however, McElrea discloses a conductive means (72) for electrically coupling like channels of conductive pads in the first and second groups of conductive pads (48), the conductive means (72) affixed to the first surface of the first semiconductor die, the edge of the first semiconductor die between the first and second surfaces, and the third surface of the second semiconductor die (¶0079).
McElrea discloses that a device as taught provides an assembly with improved stacking arrangements (¶0070). Therefore, it would have been obvious to one having skill in the art before the effective filing date of the claimed invention to modify the device of Jang, including providing conductive means for electrically coupling like channels of conductive pads in the first and second groups of conductive pads, the conductive means affixed to the first surface of the first semiconductor die, the edge of the first semiconductor die between the first and second surfaces, and the third surface of the second semiconductor die in order to provide an improved stacking arrangement as taught by McElrea.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM.
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/WILLIAM A HARRISTON/ Primary Examiner, Art Unit 2899