DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is response to Applicant’s election filed on 05/07/2026. Claims 1-20 are pending in the office action.
Claims 1-8, 16-18, and 20 are elected for consideration.
Claims 9-15 and 19 are withdrawn from consideration.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8, 16-18, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claim 1: recited “a plurality of first threshold voltage devices” which unclear whether “a plurality of first threshold voltage devices” belong to “a first cell”; also unclear the relationship between “a first cell” and “at least one first device” and/or at least one second device.
Similar to the limitation “at least one second threshold voltage device” which unclear whether “second threshold voltage device belong to “a second cell”?
As per claim 16: similar issue as per claim 1.
Claims 2-8, 17-18, and 20 are also rejected because are depended directly or indirectly from claims 1 and 16.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 16-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Macdonald et al., (U.S. Pat. 9,165,102) in view of Liaw (U.S. Pub. 2021/0367037).
As per claim 1: Macdonald teaches an integrated circuit comprising:
a first cell disposed in a first row and a second row (‘102, fig. 2, multi-height routing cell 185 (first cell) on first row and second row), the first row and the second row being adjacent to each other and extending in a first direction (‘102, fig. 2, shown first row (between 210 and 215) and second row (between 215 and 220) are adjacent each other and extent in a first direction); and
at least one second cell disposed adjacent to the first cell in at least one of the first row and the second row (‘102, fig. 2, either cell 230 or 240 (second cell) are adjacent to multi-height routing cell 185 (first cell) in the first row (cell 230) and second row (cell 240)).
Macdonald does not teach:
a plurality of first threshold voltage devices,
at least one second threshold voltage device,
wherein the plurality of first threshold voltage devices comprise:
at least one first device configured to perform a first function in the first row; and
at least one second device configured to perform a second function, which is independent of the first function, in the second row.
Liaw teaches a first circuit 201 (‘037, fig. 3B, 201) has a threshold voltage (i.e., first threshold voltage) is different from a threshold voltage of the second circuit 202 (‘037, fig. 3B, 201 and also see par. [0054] and par. [0059]). The FinFET devices have multiple threshold voltages in the first, second, and third circuits 201, 202, 203 (i.e., a plurality of first threshold voltage devices (i.e., FinFETs have plurality threshold voltage) and at least one second threshold voltage device (i.e., FinFETs have second threshold voltage) (‘037, fig. 3B and par. [0054]).
The first conductive gate material 250a (i.e., at least one first device in first row (cell 202)) includes a p-type work function metal (p-metal) for forming a PMOS over the N-type well region 160 (i.e., at least one first device configured to perform a first function in the first row (cell 201)) and the second conductive gate material 251b (i.e., at least one second device in second row (cell 201)) includes an n-type work function metal (n-metal) for forming an NMOS over the P-type well region 162 (i.e., at least one second device configured to perform a second function, which is independent of the first function, in the second row (i.e., cell 201)) (‘037, fig. 3B and par. [0055] and fig. 4A 250a as at least one first device in first row (cell 202)) and fig. 4B, 251b as at least one second device in second row (cell 201)).
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of claimed invention to combine Liaw and Macdonald to use Liaw’s multiple threshold voltages FinFET to modify Macdonald’s circuit cell to service for high speed and lower standby power application simultaneously (‘037, par. [0035]).
As per claim 2: Macdonald and Liaw teach the integrated circuit of claim 1, wherein the first cell has a certain length in the first direction (‘037, fig. 3A, 202 and also see fig. 4A-4B has certain length in the y-direction (i.e., first direction).
As per claim 3: Macdonald and Liaw teach the integrated circuit of claim 1, wherein the first row has a first height in a second direction perpendicular to the first direction, and wherein the second row has a second height, which is smaller than the first height, in the second direction (‘037, fig. 3A, as taking cell 202 as a first row has first height (space 202) in a second direction (x-direction) per perpendicular to the first direction (y-direction), and as taking cell 201 as second row has a second height, which is smaller than the first height 202 in x-direction (second direction)).
As per claim 4: Macdonald and Liaw teach the integrated circuit of claim 3, wherein the at least one second device comprise a device of a first-polarity type disposed in a first region of the second row and a device of a second-polarity type disposed in a second region of the second row (‘037, fig. 3B, PMOS over N-type well region 160 and NMOS over P-type well region 162),
wherein the first region has a first width in the second direction perpendicular to the first direction (‘037, fig. 3B, N-type well region has a first width in x-direction of cell 202, perpendicular to the first direction (y direction)), and
wherein the second region has a second width smaller than the first width in the second direction (‘037, fig. 3B, P-type well region has a second width in x-direction (second direction) of cell 201 smaller than the first width in cell 202).
As per claim 5: Macdonald and Liaw teach the integrated circuit of claim 1, wherein the first cell comprises at least one first gate electrode extending in a second direction perpendicular to the first direction (‘037, fig. 3B, gate electrode 251, par. [0056] and fig. 4B),
wherein the at least one second cell comprises at least one second gate electrode extending in the second direction (‘037, fig. 3B, gate electrode 25, par. [0056] and fig. 4A), and
wherein a pitch of the at least one first gate electrode is the same as a pitch of the at least one second gate electrode (‘037, par. [0061]).
As per claim 6: Macdonald and Liaw teach the integrated circuit of claim 1, wherein the at least one first device is configured to generate at least one first output signal from at least one first input signal, based on the first function (‘037, fig. 3A, NAND and also see fig. 3B, 202), and wherein the at least one second device is configured to generate at least one second output signal from at least one second input signal, based on the second function (‘037, fig. 3A, inverter and also see fig. 3B, 201).
As per claim 7: Macdonald and Liaw teach the integrated circuit of claim 1, wherein the first cell further comprises a conductive pattern extending in the first direction along a boundary between the first row and the second row and configured to receive a supply voltage for supplying power to the plurality of first threshold voltage devices (‘102, fig. 2, 210, 215, and 220; and ‘037, fig. 3B, 252, par. [0067], provide electrical connectivity).
As per claim 8: Macdonald and Liaw teach the integrated circuit of claim 1, wherein each of the plurality of first threshold voltage devices and the at least one second threshold voltage device comprises at least one of a fin field-effect transistor (FinFET), a gate-all-around field-effect transistor (GAAFET), a multi-bridge channel field-effect transistor (MBCFET), and a vertical field- 29 effect transistor (VFET) (‘037, fig. 3B, FinFET 210 and also see fig. 4A-4B).
As per claim 16: Macdonald teaches a method of designing an integrated circuit comprising a plurality of cells, the method comprising:
obtaining a netlist defining the plurality of cells (‘102, fig. 1, standard cell library 180, fig. 2, 230, 240, and 185 and fig. 4, netlist 405); and
placing the plurality of cells in a plurality of rows extending in a first direction, based on the netlist (‘102, fig. 2, cells 230, 240, and 185 are placed in plurality of row in first direction top-down/vertical, and also see fig. 4, place standard cells on design floorplan 410), and the first cell 185 is placing abut with second cell 240 at a boundary extending in a second direction perpendicular to the first direction (‘102, fig. 2).
Macdonald does not teach at least one first cell comprising a first threshold voltage device and at least one second cell comprising a second threshold voltage device.
Liaw teaches a first circuit 201 (‘037, fig. 3B, 201) has a threshold voltage (i.e., first threshold voltage) is different from a threshold voltage of the second circuit 202 (‘037, fig. 3B, 201 and also see par. [0054] and par. [0059]). The FinFET devices have multiple threshold voltages in the first, second, and third circuits 201, 202, 203 (i.e., a plurality of first threshold voltage devices (i.e., FinFETs have plurality threshold voltage) and at least one second threshold voltage device (i.e., FinFETs have second threshold voltage) (‘037, fig. 3B and par. [0054]).
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of claimed invention to combine Liaw and Macdonald to use Liaw’s multiple threshold voltages FinFET to modify Macdonald’s circuit cell to service for high speed and lower standby power application simultaneously (‘037, par. [0035]).
As per claim 17: Macdonald and Liaw teach the method of claim 16, wherein the placing the at least one first cell and the at least one second cell comprises:
identifying a first single-height cell comprising a first threshold voltage device, based on the netlist (‘102, fig. 2, inv_1 230/240 has single-height; ‘037, fig. 3B, 201);
identifying a multi-height cell from a cell library, based on the first single-height cell (‘102, fig. 2, multi-height routing cell 185 compared to single-height inv_1 230/240); and
placing the multi-height cell in a first row and a second row adjacent to each other (‘102, fig. 2, multi-height routing cell 185, first row between 210 and 215 and second row between 215 and 220), and
wherein the multi-height cell comprises a structure of the first single-height cell ((‘102, fig. 2, multi-height routing cell 185; ‘037, fig. 3A-3B, structure of 202 includes the structure of 201).
As per claim 18: Macdonald and Liaw teach the method of claim 17, wherein the identifying the multi-height cell comprises:
identifying a second single-height cell comprising a first threshold voltage device, based on the netlist (‘102, fig. 1, single-height inv_1 230/240); and
identifying the multi-height cell from the cell library, based on the first single-height cell and the second single-height cell (‘102, fig. 2, multi-height routing cell 185 compared to single-height inv_1 230/240).
As per claim 20: Macdonald and Liaw teach the method of claim 16, further comprising:
generating layout data defining the plurality of cells (‘102, fig. 4, 450);
fabricating at least one mask, based on the layout data (‘102, fig. 4, 455-460, mask generation); and
manufacturing the integrated circuit, based on the at least one mask (‘102, fig. 4, 465).
Conclusion
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NGHIA M. DOAN
Primary Examiner
Art Unit 2851
/NGHIA M DOAN/Primary Examiner, Art Unit 2851
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