DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments (hereinafter: “arguments”), see pages 8-9, filed 8/22/2025, with respect to the rejection(s) of claim(s) 1, 8 and 15 under 35 USC 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of CN 114586101 A to He (“He”), and further in view of US 20220230695 to Park et al. (“Park”) and US 20220293186 to Lee et al. (“Lee”).
The arguments allege that the teachings found in previously cited reference to Oh do not teach “memory blocks that are able to operate in a single bit per cell (SLC) mode and in a multiple bits per cell mode.” Paragraph [0029] in Oh, previously cited, discloses: “The migration operation means an operation of rapidly programming data output from the host by using a single level cell (SLC) method and then reprogramming the data by using a multi-level cell (MLC)-or-more method” (emphasis added). That is, interpretation of this clearly can lead one of ordinary skill in the art to conclude that a give data is programmed using SLC method, and the same data is reprogrammed using MLC method. The goal is to free up blocks of memory: “through the migration operation, data programmed in a plurality of memory blocks by using the SLC method may be reprogrammed in one memory block by the MLC-or-more method, which makes the storage efficiency of the memory blocks greater.” That is, for example, if two (2) blocks of memory are used in the SLC programming method, one (1) block of memory may be used in the MLC reprogramming method. Any clearer cannot be.
Nevertheless, relevantly and in complete agreement, the teachings of He include, as found in at least [0085]: “In some embodiments, NAND flash memory can be configured to operate in a single-level cell flash memory (single-level cell, SLC) mode. In order to increase the storage capacity, the NAND flash memory can be configured in a multi-level cell flash memory (MLC) mode, a three-level cell flash memory (triple-level cell, TLC) mode, Four-layer cell flash memory (quad-level cell, QLC) mode or a combination of any of these modes is operated” (emphasis added). That is, the NAND flash memory can be configured in either an SLC mode or at least an MLC mode, and in MLC mode or TLC mode or QLC mode, the storage capacity is increased. This is precisely the same argument the teachings of Oh provide for having a memory that can “migrate” from programming in SLC mode to reprogramming in MLC mode.
The arguments also allege that the teachings in the previously cited reference to Oh do not include “setting an SLC programming voltage to a level based on the determination of the zone of the selected word line.” The teachings of Oh may not expressly include setting an SLC programming voltage to a level based on the determination of the zone of the selected word line; yet, the teachings of Park and Lee, above cited, make it abundantly clear: “determining which zone within the selected hybrid memory block the selected word line is located in, setting an SLC programming voltage to a level based on the determination of the zone of the selected word line, and applying a programming pulse at the SLC programming voltage to the selected word line to program the memory cells of the selected word line.” While Oh and He provide clear and explicit teachings of memory that can operate in SLC or MLC modes, Park further provides teachings of “determining which zone within the selected hybrid memory block the selected word line is located in, setting an SLC programming voltage to a level based on the determination of the zone of the selected word line, and applying a programming pulse at the SLC programming voltage to the selected word line to program the memory cells of the selected word line.” As found in at least FIG. 6, a memory block is partitioned into “zones” that are associated with programming voltage levels VPGM1-VPGM7, which are in turn associated with word lines WL12-WL00. Each zone having an association with a number of word lines; for example, zone VPGM1 is associated with word lines WL12-WL11; while zone VPGM2 is associated with word lines WL10-WL08. Therefore, in order to program a memory cell in with VPGM1 it is clear its word line zone must be identified, must be determined: it is WL12-WL11. Thus, determination of a zone is performed, a programming voltage is selected and it is applied to a word line in the zone. At least paragraphs [0067]-[0068] provide relevant teachings thereof. Additionally, and complementarily, Lee in at least FIGS. 10A-10B and at least [0172] discloses teachings that are substantially the same: different zones in a memory block include different word lines and these word lines are applied different programming voltages. Moreover, Lee in at least [0035] also teaches that memory 100 may operate in SLC mode and/or MLC mode, TLC mode or QLC mode.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 20220214807 to Oh et al. (“Oh”) in view of CN 114586101 A to He (“He”), and further in view of US 20220230695 to Park et al. (“Park”) and US 20220293186 to Lee et al. (“Lee”).
As to claim 1, Oh teaches Oh discloses a method of programming (see
para. 5, discussing an SLC method and an MLC or more method) a memory device (Fig. 1: 1000), comprising the steps of: preparing a memory device (Fig. 1: 1000) that includes a plurality of memory blocks (Fig. 3: BLK, showing multiple blocks) that each include a plurality of memory cells (Fig. 4: C, showing multiple memory cells) that are arranged in a plurality of word lines (Fig. 4: WL, showing multiple word lines), the plurality of memory blocks (Fig. 3: BLK) including a plurality of hybrid memory blocks (Fig. 5: SLC, MLC, TLC, QLC) that are able to operate in a single bit per memory cell (SLC) mode (Fig. 5: SLC) and a multiple bits per memory cell mode (Fig. 5: MLC, TLC, QLC, see para. 29 discussing a migration operation); programming a selected word line (Fig. 4: WL1) of the plurality of word lines (Fig. 4: WL) within a selected hybrid memory block (Fig. 5: MLC) to an SLC format (Fig. 5: SLC), the programming of the selected word line (Fig. 4: WL1) to the SLC format (Fig. 5: SLC).
Moreover, He teaches as found in at least [0085]: “In some embodiments, NAND flash memory can be configured to operate in a single-level cell flash memory (single-level cell, SLC) mode. In order to increase the storage capacity, the NAND flash memory can be configured in a multi-level cell flash memory (MLC) mode, a three-level cell flash memory (triple-level cell, TLC) mode, Four-layer cell flash memory (quad-level cell, QLC) mode or a combination of any of these modes is operated” (emphasis added). That is, the NAND flash memory can be configured in either an SLC mode or at least MLC mode, and in MLC mode or TLC mode or QLC mode, the storage capacity is increased.
While Oh may not expressly teach determining which zone within the selected hybrid memory block the selected word line is located in, setting an SLC programming voltage to a level based on the determination of the zone of the selected word line, and applying a programming pulse at the SLC programming voltage to the selected word line to program the memory cells of the selected word line,
Park and Lee, relevantly and complementarily, teach determining which zone within the selected hybrid memory block the selected word line is located in, setting an SLC programming voltage to a level based on the determination of the zone of the selected word line, and applying a programming pulse at the SLC programming voltage to the selected word line to program the memory cells of the selected word line (While Oh and He provide clear and explicit teachings of memory that can operate in SLC or MLC modes, Park further provides teachings of “determining which zone within the selected hybrid memory block the selected word line is located in, setting an SLC programming voltage to a level based on the determination of the zone of the selected word line, and applying a programming pulse at the SLC programming voltage to the selected word line to program the memory cells of the selected word line.” As found in at least FIG. 6, a memory block is partitioned into “zones” that are associated with programming voltage levels VPGM1-VPGM7, which are in turn associated with word lines WL12-WL00. Each zone having an association with a number of word lines; for example, zone VPGM1 is associated with word lines WL12-WL11; while zone VPGM2 is associated with word lines WL10-WL08. Therefore, in order to program a memory cell in with VPGM1 it is clear its word line zone must be identified, must be determined: it is WL12-WL11. Thus, determination of a zone is performed, a programming voltage is selected and it is applied to a word line in the zone. At least paragraphs [0067]-[0068] provide relevant teachings thereof. Additionally, and complementarily, Lee in at least FIGS. 10A-10B and at least [0172] discloses teachings that are substantially the same: different zones in a memory block include different word lines and these word lines are applied different programming voltages. Moreover, Lee in at least [0035] also teaches that memory 100 may operate in SLC mode and/or MLC mode, TLC mode or QLC mode).
Note: Section (2) above in this Office action is referenced herein fully and is made part integral of the claim rejection.
Oh and He and Park and Lee are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory devices that may include SLC and at least MLC modes of operation.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Oh as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Park and Lee also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: free up blocks of memory; data programmed in a plurality of memory blocks by using the SLC method may be reprogrammed in one memory block by the MLC-or-more method, which makes the storage efficiency of the memory blocks greater; increase the storage capacity, the memory can be configured in a multi-level cell flash memory (MLC) mode, a three-level cell flash memory (triple-level cell, TLC) mode, Four-layer cell flash memory (quad-level cell, QLC) mode or a combination of any of these modes is memory operated.
Therefore, it would have been obvious to combine Oh with He, Park and Lee to make the above modification.
As to claim 2, Oh discloses the plurality of memory blocks (Fig. 3: BLK)
further includes a plurality of dedicated SLC memory blocks (see abstract stating the first memory block operates as a single bit memory block) that are only configured to operate in the SLC mode (see abstract).
As to claim 3, Oh discloses the memory cells (Fig. 4: C) of the word lines (Fig. 4: WL) of the dedicated SLC memory blocks (see abstract stating the first memory block operates as a single bit memory block) are programmed with a programming pulse (Fig. 8: Vrd_S) at a VPGMSLC voltage (Fig. 8: P1, adjusted solid line).
As to claim 4, Oh discloses the step of setting the SLC programming
voltage (Figs. 5 & 8, showing a read programming voltage) includes determining a AVPGMSLC voltage (Fig. 8: P1, dotted line) based on which zone the selected word line (Fig. 4: WL1) is located in and setting the SLC programming voltage (Figs. 5 & 8, showing a read programming voltage) to a level that is equal to VPGMSLC (Fig. 8: P1, adjusted solid line) minus AVPGMSLC (Fig. 8: P1, dotted line).
As to claim 5, Oh discloses the method of programming (see para. 5,
discussing an SLC method and an MLC or more method) the memory device (Fig. 1: 1000) as set forth in claim 3 further including, during a background operation (Fig. 9: 1200, see para. 119), the step of programming any data written to SLC format (Fig. 5: SLC) in either the dedicated SLC memory blocks (see abstract stating the first memory block operates as a single bit memory block) or the hybrid memory blocks (Fig. 5: SLC, MLC, TLC, QLC) to a multiple bits per memory cell format (Fig. 5: MLC, TLC, QLC, see para. 29 discussing a migration operation).
As to claim 6, Oh discloses the multiple bits per memory cell format (Fig.
5: MLC, TLC, QLC, see para. 29 discussing a migration operation) includes at least three bits per memory cell (see para. 29 discussing a migration operation).
As to claim 7, Oh discloses the method of programming (see para. 5,
discussing an SLC method and an MLC or more method) the memory device (Fig. 1: 1000) as set forth in claim 1 further including the step of determining if the programming of the selected word line (Fig. 4: WL1) is to include multiple programming pulses (Fig 7. Pv1, Pv2, Pv3) and at least one verify operation (Fig. 2: Vop) or is to include only a single programming pulse (Fig. 8: Vrd_S) and no verify operations based on the determination of which zone the selected word line (Fig. 4: WL1) is located within.
As to claim 8, see rejection to at least claim 1; wherein the memory device is as found in at least FIGS. 1-2, 9, 11A-11B in Oh; FIG. 1 in He; FIGS. 1-2, 11 in Park; FIGS. 1-2, 14 in Lee.
Note: Section (2) above in this Office action is referenced herein fully and is made part integral of the claim rejection.
As to claim 9, Oh discloses the plurality of memory blocks (Fig. 3: BLK)
further includes a plurality of dedicated SLC memory blocks (see abstract stating the first memory block operates as a single bit memory block) that are only configured to operate in the SLC mode (see abstract).
As to claim 10, Oh discloses the control circuitry (Fig. 2: 1200) of the
memory device (Fig. 1: 1000) is configured to program the memory cells (Fig. 4: C) of the word lines (Fig. 4: WL) of the dedicated SLC memory blocks (see abstract stating the first memory block operates as a single bit memory block) with a programming pulse (Fig. 8: Vrd_S) at a VPGMSLC voltage (Fig. 8: P1, adjusted solid line).
As to claim 11, Oh discloses wherein while setting the SLC programming
voltage (Figs. 5 & 8, showing a read programming voltage), the control circuitry (Fig. 2: 1200) is configured to determine a AVPGMSLC voltage (Fig. 8: P1, dotted line) based on which zone the selected word line (Fig. 4: WL1) is located in and set the SLC programming voltage (Figs. 5 & 8, showing a read programming voltage) to a level that is equal to VPGMSLC (Fig. 8: P1, adjusted solid line) minus AVPGMSLC (Fig. 8: P1, dotted line).
As to claim 12, Oh discloses the control circuitry (Fig. 2: 1200) is
configured to, during a background operation (Fig. 9: 1200, see para. 119), program any data written to SLC format (Fig. 5: SLC) in either the dedicated SLC memory blocks (see abstract stating the first memory block operates as a single bit memory block) or the hybrid memory blocks (Fig. 5: SLC, MLC, TLC, QLC) to a multiple bits per memory cell format (Fig. 5: MLC, TLC, QLC, see para. 29 discussing a migration operation).
As to claim 13, Oh discloses the multiple bits per memory cell format (Fig. 5: MLC, TLC, QLC) includes at least three bits per memory cell (see para. 29 discussing a migration operation).
As to claim 14, Oh discloses the control circuitry (Fig. 2: 1200) is further
configured to determine if the programming of the selected word line (Fig. 4: WL1) is to include multiple programming pulses (Fig 7. Pv1, Pv2, Pv3) and at least one verify operation (Fig. 2: Vop) or is to include only a single programming pulse (Fig. 8: Vrd_S) and no verify operations based on the determination of which zone the selected word line (Fig. 4: WL1) is located within.
As to claim 15, see rejection to at least claim 1; wherein the apparatus is found in at least FIGS. 1-2, 9, 11A-11B in Oh; FIG. 1 in He; FIGS. 1-2, 11 in Park; FIGS. 1-2, 14 in Lee.
Note: Section (2) above in this Office action is referenced herein fully and is made part integral of the claim rejection.
As to claim 16, Oh discloses the plurality of memory blocks (Fig. 3: BLK)
further includes a plurality of dedicated SLC memory blocks (see abstract stating the first memory block operates as a single bit memory block) that are only configured to operate in the SLC mode (see abstract).
As to claim 17, Oh discloses the programming means (see para. 5,
discussing an SLC method and an MLC or more method) is configured to program the memory cells (Fig. 4: C) of the word lines (Fig. 4: WL) of the dedicated SLC memory blocks (see abstract stating the first memory block operates as a single bit memory block) with a programming pulse (Fig. 8: Vrd_S) at a VPGMSLC voltage (Fig. 8: P1, dotted line).
As to claim 18, Oh discloses wherein while setting the SLC programming
voltage (Figs. 5 & 8, showing a read programming voltage), the programming means (see para. 5, discussing an SLC method and an MLC or more method) is configured to determine a AVPGMSLC voltage (Fig. 8: P1, dotted line) based on which zone the selected word line (Fig. 4: WL1) is located in and set the SLC programming voltage (Figs. 5 & 8, showing a read programming voltage) to a level that is equal to VPGMSLC (Fig. 8: P1, adjusted solid line) minus AVPGMSLC (Fig. 8: P1, dotted line).
As to claim 19, Oh discloses the programming means (see para. 5,
discussing an SLC method and an MLC or more method) is configured to, during a background operation (Fig. 9: 1200, see para. 119), program any data written to SLC format (Fig. 5: SLC) in either the dedicated SLC memory blocks (see abstract stating the first memory block operates as a single bit memory block) or the hybrid memory blocks (Fig. 5: SLC, MLC, TLC, QLC) to a multiple bits per memory cell format (Fig. 5: MLC, TLC, QLC).
As to claim 20, Oh discloses the programming means (see para. 5,
discussing an SLC method and an MLC or more method) is configured to determine if the programming of the selected word line (Fig. 4: WL1) is to include multiple programming pulses (Fig 7. Pv1, Pv2, Pv3) and at least one verify operation (Fig. 2: Vop) or is to include only a single programming pulse (Fig. 8: Vrd_S) and no verify operations based on the determination of which zone the selected word line (Fig. 4: WL1) is located within.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827
Prosecution Insights