DETAILED ACTION
Election/Restrictions
Applicant’s election of Species 1b and 2a, alleged to correspond to claims 1-3, 20 in the reply filed on 12/1/25 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Note that claim 4, and its dependent claim 5, are removed from the elected claim set because in elected figure 18 the TIM is in direct contact with the one or more thermally conductive layers. But claim 4 requires the TIM is spaced from the one or more thermally conductive layers at the edge of the heat conduction medium, which is not found in elected figure 18.
Further note that claim 15, and its dependent claims 16-17, are removed from the elected claim set because they refer to nonelected figure 14 and not elected figures 16 and 18.
Consequently, the examined claim set only includes 1-3, 6-14, and 18-20.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Line 1 of claim 12 recites “first and semiconductor”. This appears to be missing a word, specifically “second” therefore correction or clarification is requested. For examination purposes it will be assumed that it was intended to read “first and second semiconductor”.
Rejection over Kondo et al., US 2022/0059427
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-11, 13-14, and 18-20 is/are rejected under 35 U.S.C. 102a2 as being clearly anticipated by Kondo et al., US 2022/0059427.
Regarding claim 1, Kondo (figure 3) teaches a semiconductor storage device, comprising:
a heat conduction medium 12, comprising:
one or more thermally conductive layers 22/27 extending to an edge of the heat conduction medium 12;
one or more thermally conductive vias 23 configured to conduct heat to the one or more thermally conductive layers 22;
a semiconductor package 14 mounted on a surface of the heat conduction medium 12 by a plurality of solder balls 15, wherein the one or more thermally conductive vias 23 are positioned adjacent to a group of one or more solder balls 15 of the plurality of solder balls 15 to conduct heat from the semiconductor package 14 through the one or more solder balls 15; and
a thermal interface material (TIM) 32 mounted adjacent to the edge of the heat conduction medium 12, the one or more thermally conductive layers 22 configured to conduct heat to the TIM 32.
With respect to claim 2, Kondo (figure 3) teaches an enclosure 30 including a sidewall, the TIM 32 configured to conduct heat to the sidewall of the enclosure 32.
As to claim 3, Kondo (figure 3) teaches the TIM 32 is in direct contact with the one or more thermally conductive layers 22/27 at the edge of the heat conduction medium 12.
As to claim 6, Kondo (figure 2) teaches the TIM 32 is one of a plurality of TIMs along the edge of the heat conduction medium 12.
In re claim 7, Kondo (figure 3) teaches the one or more thermally conductive layers 22 comprise a first set of thermally conductive layers 22, the edge (left side of 12) comprises a first edge and the one or more thermally conductive vias 23 comprise a first set of thermally conductive vias 23 (on left side of 12), the heat conduction medium 12 further comprising:
a second set of one or more thermally conductive layers 22 extending to a second edge (right side of 12) of the heat conduction medium 12, and a second set of one or more thermally conductive vias 23 (on right side of 12) configured to conduct heat to the second set of one or more thermally conductive layers 22.
Concerning claim 8, Kondo (figure 2 teaches TIM 32 on all four edges) teaches the TIM 32 comprises a first TIM 32, the semiconductor storage device further comprising a second thermal interface material (TIM) 32 mounted adjacent to the second edge of the heat conduction medium 12, the second set of one or more thermally conductive layers 22 configured to conduct heat to the second TIM 32.
Pertaining to claim 9, wherein the group of one or more solder balls 15 of the semiconductor package 14 (the left 14) comprise a first group of one or more solder balls 15 (on the left), and wherein the second set of one or more thermally conductive vias 23 are configured to receive heat from a second group (on the right) of one or more solder balls 15 of the plurality of solder balls 15.
In claim 10, Kondo (figure 3) teaches a second semiconductor package (right 14) mounted on the surface of the heat conduction medium 12, the second semiconductor package (right 14) comprising a second plurality of solder balls 15 (on the right).
Regarding claim 11, Kondo (figure 3) teaches the first (left 14) semiconductor package is positioned adjacent to the first edge (left side of 12) and the second semiconductor package (right 14) is positioned adjacent to the second edge (right side of 12), and wherein the second group of one or more thermally conductive vias (right 23) are positioned adjacent to a second group of one or more solder balls (right 15) of the second plurality of solder balls (right 15) to conduct heat from the second semiconductor package (right 14) through the second group of one or more solder balls (right 15) to the second set of one or more thermally vias (right 23).
With respect to claim 12, Kondo (figure 3) teaches the first and “second” (sic) (right 14) semiconductor packages are positioned adjacent to the first edge, and wherein the first group of one or more thermally conductive vias are positioned adjacent to a second group of one or more solder balls of the second plurality of solder balls to conduct heat from the second semiconductor package through the second group of one or more solder balls to the first group of one or more thermally conductive vias.
As to claim 13, Kondo (figure 3) teaches the heat conduction medium 12 comprises a printed circuit board 60 comprising the one or more thermally conductive layers 61 interspersed with one or more dielectric layers (between each layer 61).
In re claim 14, Kondo (figure 3) teaches a semiconductor storage device, comprising:
a printed circuit board (PCB) 12, comprising:
one or more thermally conductive layers 22/27 exposed at an edge of the PCB 12;
one or more thermally conductive vias 23 configured to conduct heat to the one or more thermally conductive layers 22/27;
a semiconductor package 14 mounted on a surface of the PCB 12 by a plurality of solder balls 15, wherein the one or more thermally conductive vias 23 are positioned adjacent to a group of one or more solder balls 15 of the plurality of solder balls 15; and
a thermal interface material (TIM) 32 mounted at the edge of the PCB 12 in contact with the one or more thermally conductive layers 22/27;
wherein a thermal conduction path exists to conduct heat away from the semiconductor package 14 through the edge of the PCB 12, the thermal conduction path comprising the one or more solder balls 15, the one or more thermally conductive vias 23, the one or more thermally conductive layers 22/27 and the TIM 32.
Concerning claim 18, Kondo (figure 3) teaches an enclosure 30 including a sidewall 30S, the TIM 32 configured to conduct heat to the sidewall 30S of the enclosure 30.
Pertaining to claim 19, Kondo (figure 3) teaches the TIM 32 is in direct contact with the one or more thermally conductive layers 22/27 at the edge of the heat conduction medium 12.
In claim 20, Kondo (figure 3) teaches a semiconductor storage device, comprising:
a printed circuit board (PCB) 12, the PCB 12 having a surface and an edge adjacent to the surface;
a semiconductor package 14 mounted on the surface of the PCB 12 by a plurality of solder balls 15;
an enclosure 30 enclosing the PCB 12 and semiconductor package 14;
first means 22/23/27 for conducting heat from the semiconductor package 14, through the plurality of solder balls 15, to the edge of the PCB 12; and
second means 32 for conducting heat away from the edge of the PCB 12 to the enclosure 30.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kondo et al., US 2022/0059427, as applied to claim 1 above.
Regarding claim 12, though Kondo (figure 3) fails to teach the first and “second” (sic) (right 14) semiconductor packages are positioned adjacent to the first edge, and wherein the first group of one or more thermally conductive vias are positioned adjacent to a second group of one or more solder balls of the second plurality of solder balls to conduct heat from the second semiconductor package through the second group of one or more solder balls to the first group of one or more thermally conductive vias, it would have been obvious to one of ordinary skill in the art at the time of the invention to use multiple packages 14 on the first edge in the invention of Kondo because the mere duplication of parts has no patentable significance unless a new and unexpected result is produced (In re Harza, 124 USPQ 378 (CCPA 1960)).
Rejections over Hou et al., CN 103560117
Claim(s) 1-3, 6-14, and 18-20 is/are rejected under 35 U.S.C. 103 as being clearly anticipated by Hou et al., CN 103560117, in view of Kondo et al., US 2022/0059427.
Regarding claim 1. Hou (figures 2-3) teaches a semiconductor storage device, comprising:
a heat conduction medium 100, comprising:
one or more thermally conductive layers 102 extending to an edge of the heat conduction medium 100;
one or more thermally conductive vias 101 configured to conduct heat to the one or more thermally conductive layers 102;
a semiconductor package 201 mounted on a surface of the heat conduction medium 100, wherein the one or more thermally conductive vias 101 to conduct heat from the semiconductor package 201; and
a thermal interface material (TIM) 104 mounted adjacent to the edge of the heat conduction medium 100, the one or more thermally conductive layers 102 configured to conduct heat to the TIM 104.
Hou, which appears to teach using welding (paragraph 0026), fails to teach the semiconductor package 201 is mounted by a plurality of solder balls connected to the thermally conductive vias 101.
Kondo (figure 1) teaches semiconductor package 14 is mounted by a plurality of solder balls 15 connected to the thermally conductive vias 23.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the solder balls 15 of Kondo in the invention of Hou because solder balls are a conventionally known and used equivalent bonding technique. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950).
With respect to claim 2, Hou (figures 2-3) teaches an enclosure 700 including a sidewall, the TIM 104 configured to conduct heat to the sidewall of the enclosure 700.
As to claim 3, Hou (figures 2-3) teaches the TIM 104 is in direct contact with the one or more thermally conductive layers 102 at the edge of the heat conduction medium 100.
In re claim 6, Hou (figure 4) teaches the TIM 104 is one of a plurality of TIMs 104 along the edge of the heat conduction medium 100.
Concerning claim 7, Hou (figures 2-3) teaches the one or more thermally conductive layers 102 comprise a first set of thermally conductive layers 102, the edge comprises a first edge and the one or more thermally conductive vias 101 comprise a first set of thermally conductive vias 101, the heat conduction medium 100 further comprising: a second set of one or more thermally conductive layers 102 extending to a second edge of the heat conduction medium 100, and a second set of one or more thermally conductive vias 101 configured to conduct heat to the second set of one or more thermally conductive layers 102.
Pertaining to claim 8, Hou (figure 4) teaches the TIM comprises a first TIM , the semiconductor storage device further comprising a second thermal interface material (TIM) 104 mounted adjacent to the second edge of the heat conduction medium 100, the second set of one or more thermally conductive layers 102 configured to conduct heat to the second TIM 104.
In claim 9, Kondo (figure 1) teaches the group of one or more solder balls 15 of the semiconductor package 14 comprise a first group of one or more solder balls 15, and wherein the second set of one or more thermally conductive vias 23 are configured to receive heat from a second group of one or more solder balls 15 of the plurality of solder balls 15.
Regarding claim 10, Hou (figures 2-3) and Kondo combine to teach a second semiconductor package 201 mounted on the surface of the heat conduction medium 100, the second semiconductor package 201 comprising a second plurality of solder balls (taught by Kondo using solder balls 15).
With respect to claim 11, Hou (figures 2-3) and Kondo combine to teach the first semiconductor package (left 201) is positioned adjacent to the first edge (left side of 100) and the second semiconductor package (right 201) is positioned adjacent to the second edge (right side of 100), and wherein the second group of one or more thermally conductive vias 101 are positioned adjacent to a second group of one or more solder balls (15 of Kondo) of the second plurality of solder balls (15 of Kondo) to conduct heat from the second semiconductor package (right 201) through the second group of one or more solder balls (15 of Kondo) to the second set of one or more thermally vias 101.
As to claim 12, though Hou (figures 2-3) fails to teach the first and “second” (sic) semiconductor packages 201 are positioned adjacent to the first edge, and wherein the first group of one or more thermally conductive vias are positioned adjacent to a second group of one or more solder balls of the second plurality of solder balls to conduct heat from the second semiconductor package through the second group of one or more solder balls to the first group of one or more thermally conductive vias, it would have been obvious to one of ordinary skill in the art at the time of the invention to use multiple packages 14 on the first edge in the invention of Kondo because the mere duplication of parts has no patentable significance unless a new and unexpected result is produced (In re Harza, 124 USPQ 378 (CCPA 1960)).
In re claim 13, Hou (figures 2-3) teaches the heat conduction medium 100 comprises a printed circuit board comprising the one or more thermally conductive layers 102 interspersed with one or more dielectric layers 103.
Concerning claim 14, Hou (figures 2-3) teaches a semiconductor storage device, comprising:
a printed circuit board (PCB) 100, comprising:
one or more thermally conductive layers 102 exposed at an edge of the PCB 100;
one or more thermally conductive vias 101 configured to conduct heat to the one or more thermally conductive layers 102;
a semiconductor package 201 mounted on a surface of the PCB 100; and
a thermal interface material (TIM) 104 mounted at the edge of the PCB 100 in contact with the one or more thermally conductive layers 102;
wherein a thermal conduction path exists to conduct heat away from the semiconductor package 201 through the edge of the PCB 100, the thermal conduction path comprising the one or more thermally conductive vias 101, the one or more thermally conductive layers 102 and the TIM 104.
Hou fails teach solder balls connect the thermally conductive vias to the packages, wherein the one or more thermally conductive vias 101 are positioned adjacent to a group of one or more solder balls of the plurality of solder balls.
Kondo (figure 1) teaches solder balls 15 connect the thermally conductive vias 23 to the packages 14, wherein the one or more thermally conductive vias 23 are positioned adjacent to a group of one or more solder balls 15 of the plurality of solder balls 15.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the solder balls 15 of Kondo in the invention of Hou because solder balls are a conventionally known and used equivalent bonding technique. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950).
Pertaining to claim 18, Hou (figures 2-3) teaches an enclosure 700 including a sidewall, the TIM 104 configured to conduct heat to the sidewall of the enclosure 700.
In claim 19, Hou (figures 2-3) teaches the TIM 104 is in direct contact with the one or more thermally conductive layers 102 at the edge of the heat conduction medium 100.
Regarding claim 20, Hou (figures 2-3) teaches a semiconductor storage device, comprising:
a printed circuit board (PCB) 100, the PCB 100 having a surface and an edge adjacent to the surface;
a semiconductor package 201 mounted on the surface of the PCB 100;
an enclosure enclosing the PCB and semiconductor package;
first means 101/102 for conducting heat from the semiconductor package 201 to the edge of the PCB 100; and
second means 104 for conducting heat away from the edge of the PCB 100 to the enclosure 700.
Hou fails teach solder balls connect the package to the PCB.
Kondo (figure 1) teaches solder balls 15 connect the package 14 to the PCB 12.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the solder balls 15 of Kondo in the invention of Hou because solder balls are a conventionally known and used equivalent bonding technique. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950).
Conclusion
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/DAVID A ZARNEKE/ Primary Examiner, Art Unit 2891 2/17/26