DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 13-20 in the reply filed on 12/9/2025 is acknowledged.
Claims 1-12 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 13-16, 18, and 20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Ryu et al (U.S. Pub #2022/0223732).
With respect to claim 13, Ryu teaches a memory device, comprising:
a plurality of semiconductor bodies (Fig. 7, vertical portions130 and Paragraph 39) spaced apart from each other and extending along a first direction;
spacing portions (Fig. 7, portions including 140A/150A/114) between adjacent semiconductor bodies;
conductive connection portions (Fig. 7, 160A and Paragraph 59) connected to the semiconductor bodies along the first direction; and
spacer portions (Fig. 7, portions of 116) disposed on sides of the spacing portions along the first direction (Fig. 7, Z direction) and disposed around the conductive connection portions,
wherein the conductive connection portions and the spacing portions overlap along a second direction (Fig. 7, X direction) that is perpendicular to the first direction.
With respect to claim 14, Ryu teaches that the semiconductor bodies comprise drains, channels, and sources that are arranged along the first direction (Paragraph 38), and the sources are located on sides of the channels close to the conductive connection portions that are connected to the sources along the first direction (Paragraph 30, the bit line 120 is below the transistor, hence the drain S/D region is the lower region and the source S/D region is the upper region).
With respect to claim 15, Ryu teaches part of the spacing portions comprise gates (Fig. 7, 150a/150b and Paragraph 28) close to sides of the channels and gate insulation sub-portions (Fig. 7, 140a/140b and Paragraph 28) between the gates and the channels.
With respect to claim 16, Ryu teaches that ends of the conductive connection portions (Fig. 7 bottom surface portion of 160A/160B) close to the semiconductor bodies (Fig. 7, 130) and the spacing portions (Fig. 7, 114) overlap along the second direction, and ends of the conductive connection portions far away from the semiconductor bodies and the spacer portions (Fig. 7, 116) overlap along the second direction.
With respect to claim 18, Ryu teaches that widths of the conductive connection portions (Fig. 7, 160A) along the second direction are greater than widths of the semiconductor bodies (Fig. 7, 132 and/or 134) along the second direction (Fig. 7, X direction).
With respect to claim 20, Ryu teaches a memory system, comprising:
a memory device (Fig. 7 and Paragraph 75); and
a controller coupled to the memory device and configured to control the memory device to store data (Paragraph 71-72),
wherein the memory device comprises: a plurality of semiconductor bodies (Fig. 7, vertical portions130 and Paragraph 39) spaced apart from each other and extending along a first direction;
spacing portions (Fig. 7, portions including 140A/150A/114) between adjacent semiconductor bodies;
conductive connection portions (Fig. 7, 160A and Paragraph 59) connected to the semiconductor bodies along the first direction; and
spacer portions (Fig. 7, portions of 116) disposed on sides of the spacing portions along the first direction (Fig. 7, Z direction) and disposed around the conductive connection portions,
wherein the conductive connection portions and the spacing portions overlap along a second direction (Fig. 7, X direction) that is perpendicular to the first direction.
Claims 13, 14, 17, and 19 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Lee et al (U.S. Pub #2023/0055499).
With respect to claim 13, Lee teaches a memory device, comprising:
a plurality of semiconductor bodies (Fig. 5A-5C, vertical portions VCP1 and VCP2 and Paragraph 52) spaced apart from each other and extending along a first direction (Fig. 5A-5C, vertical direction);
spacing portions (Fig. 5A-5C, portions including Gox, WL, SP, and 153) between adjacent semiconductor bodies;
conductive connection portions (Fig. 5A-5C, LP and Paragraph 78) connected to the semiconductor bodies along the first direction; and
spacer portions (Fig. 5A-5C, portions of 165) disposed on sides of the spacing portions along the first direction (Fig. 7, vertical direction) and disposed around the conductive connection portions,
wherein the conductive connection portions and the spacing portions overlap along a second direction (Fig. 7, horizontal direction) that is perpendicular to the first direction.
With respect to claim 14, Lee teaches that the semiconductor bodies comprise drains, channels, and sources that are arranged along the first direction (Paragraph 56), and the sources are located on sides of the channels close to the conductive connection portions that are connected to the sources along the first direction (Paragraph 24, the source regions are the upper S/D regions).
With respect to claim 17, Lee teaches that widths of ends of the conductive connection portions (Fig. 5A-5C, LP) far away from the semiconductor bodies (Figs. 5A-5C, VCP) along the second direction are greater than widths of ends of the conductive connection portions close to the semiconductor bodies along the second direction.
With respect to claim 19, Lee teaches a barrier layer (Fig. 5A-5C, 155) disposed between the spacer portions (Fig. 5A-5C, 165) and the spacing portions (Fig. 5A-5C, 153).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN P SANDVIK whose telephone number is (571)272-8446. The examiner can normally be reached M-F: 10-6.
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/BENJAMIN P SANDVIK/Primary Examiner, Art Unit 2812