Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s arguments with respect to amended claim(s) 1-19 have been considered but are moot because of the new ground of rejection as disclosed below.
DETAILED ACTION
This action is responsive to application No. 18223117 filed on 7/18/2023.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Election/Restrictions
Applicant’s election without traverse of claims 1-19 in the reply filed on 9/29/2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chuang (US 2022/0005948) in view of Mehrotra (US 12,272,739).
Regarding independent claim 1, Chuang teaches a structure for an extended-drain metal-oxide-semiconductor device, the structure comprising:
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a semiconductor layer (Figs. 9-10, element 204, paragraph 0020) including a first sidewall and a top surface;
a source region (Figs. 9-10, element 408, paragraph 0024) including a first doped region in the semiconductor layer;
a drain region (Figs. 9-10, element 406, paragraph 0024) including a second doped region in the semiconductor layer;
a body (Figs. 9-10, element 404, paragraph 0024) including a third doped region in the semiconductor layer;
a drift region (Figs. 9-10, element 402, paragraph 0024) including a fourth doped region in the semiconductor substrate, the fourth doped region adjacent to the second doped region; and
a gate (Figs. 9-10, element 902, paragraph 0030) positioned between the source region and the drain region, the gate including a gate conductor layer,
a first gate dielectric layer (Figs. 9-10, element 702, paragraph 0026) having a first thickness, and
a second gate dielectric layer (Figs. 9-10, element 602, paragraph 0025) having a second thickness greater than the first thickness (Fig. 9),
the first gate dielectric layer on the top surface of the semiconductor layer (Figs. 9-10),
the second gate dielectric layer including a first section on the top surface of the semiconductor layer and a second section adjacent to and along the first sidewall of the semiconductor layer (Figs. 9-10), and
the gate conductor layer having an overlapping relationship with the first gate dielectric layer, the first section of the second gate dielectric layer, and the second section of the second gate dielectric layer (Figs. 9-10),
wherein the first doped region and the second doped region contain a concentration of an n- type dopant (paragraph 0029), the third doped region and the fourth doped region contain a concentration of a p-type dopant (paragraph 0029), the first dielectric layer overlaps with a portion of the third doped region and with a first portion of the fourth doped region (see annotated figure above), and the first section of the second gate dielectric layer overlaps with a second portion of the fourth doped region (see annotated figure above).
Chuang does not explicitly disclose the second doped region is disposed in a portion of the third doped layer.
Mehrotra teaches a LDMOS device comprising source region (Fig. 17, element 920) is disposed in a portion of the body layer (Fig. 17, element 910).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Chuang according to the teachings of Mehrotra with the motivation to provide low on-resistance and high blocking voltage.
Regarding claim 2, Chuang teaches a shallow trench isolation region (Figs. 9-10, element 306, paragraph 0022) in the semiconductor layer, wherein the second section of the second dielectric layer overlaps with the shallow trench isolation region.
Regarding claim 3, Chuang teaches a substrate (Figs. 9-10, element 202); and a dielectric layer (paragraph 0019 discloses SOI) on the substrate, wherein the semiconductor layer is disposed on the dielectric layer, and the shallow trench isolation region penetrates through the semiconductor layer to the dielectric layer (Fig 10 disclose the STI region 306 penetrating the semiconductor layer 204, accordingly it would be obvious to one of ordinary skill in the art that the STI region 306 would penetrate through the semiconductor layer 204 to the dielectric layer of the SOI structure).
Regarding claim 4, Chuang teaches wherein the semiconductor layer includes a device region (Fig. 10, the FinFET formed on the semiconductor layer 204) surrounded by the shallow trench isolation region (Fig. 10), and the device region includes a portion that projects above the shallow trench isolation region (Fig. 10).
Regarding claim 5, Chuang teaches wherein the first sidewall of the semiconductor layer extends from the shallow trench isolation region to the top surface of the semiconductor layer (Fig. 10).
Regarding claim 6, Chuang teaches wherein the first sidewall extends from the source region to the drain region (Figs. 6-10).
Regarding claim 7, Chuang teaches wherein the semiconductor layer includes a second sidewall, and the second gate dielectric layer includes a third section adjacent to the second sidewall of the semiconductor layer (Fig. 10).
Regarding claim 8, Chuang teaches wherein the first section of the second gate dielectric layer extends across the top surface of the semiconductor layer from the second section of the second gate dielectric layer to the third section of the second gate dielectric layer (Fig. 10).
Regarding claim 9, Chuang teaches wherein the first sidewall of the semiconductor layer is aligned parallel to the second sidewall of the semiconductor layer (Fig. 10).
Regarding claim 10, Chuang teaches wherein the first gate dielectric layer extends across the top surface of the semiconductor layer from the second section of the second gate dielectric layer to the third section of the second gate dielectric layer (Fig. 10).
Regarding claim 11, Chuang teaches wherein the second section of the second gate dielectric layer is disposed on the first sidewall of the semiconductor layer, and the third section of the second gate dielectric layer is disposed on the second sidewall of the semiconductor layer (Fig. 10).
Regarding claim 12, Chuang teaches wherein the second section of the second gate dielectric layer is laterally between the gate conductor layer and the semiconductor layer at the first sidewall, and the third section of the second gate dielectric layer is laterally between the gate conductor layer and the semiconductor layer at the second sidewall (Figs. 9-10).
Regarding claim 13, Chuang teaches wherein the gate conductor layer overlaps with a portion of the second section of the second gate dielectric layer, and the gate conductor layer overlaps with a portion of the third section of the second gate dielectric layer (Figs. 9-10).
Regarding claim 14, Chuang teaches wherein the second section of the second gate dielectric layer is disposed on the first sidewall of the semiconductor layer (Figs. 9-10).
Regarding claim 15, Chuang teaches wherein the second section of the second gate dielectric layer directly contacts the first sidewall of the semiconductor layer (Figs. 9-10).
Regarding claim 16, Chuang teaches wherein the gate conductor layer overlaps with a first portion of the second section of the second gate dielectric layer (Figs. 9-10).
Regarding claim 17, Chuang teaches wherein the second section of the second gate dielectric layer includes a second portion adjacent to the first doped region, and the second section of the second gate dielectric layer includes a third portion adjacent to the second doped region (Figs. 9-10).
Regarding claim 18, Chuang teaches wherein the second thickness of the second gate dielectric layer is in a range of about 100 nanometers to about 300 nanometers (paragraph 0023 discloses the claimed thickness range for a dielectric layer. Additionally, the thickness of a gate dielectric layer can be changed to optimize the threshold voltage. Therefore, the thickness is an art recognized variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thickness as the thickness is a result-effective variable. Furthermore, the applicant has not presented persuasive evidence that the claimed area is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed thickness)).
Regarding claim 19, Chuang teaches wherein the first section of the second gate dielectric layer is vertically between the gate conductor layer and the semiconductor layer, and the second section of the second gate dielectric layer is laterally between the gate conductor layer and the semiconductor layer at the first sidewall (Fig. 10).
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
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/SHAHED AHMED/Primary Examiner, Art Unit 2813
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