DETAILED ACTION
This action is responsive to the amendments filed May, 6, 2026. Claims 1-20 are pending. No claims have been amended. Claims 1, 10, and 20 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Applicant's amendment to para. 79 of the specification is acknowledged and accepted.
Claim Rejections - 35 USC § 112 - written description requirement
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding independent claims 1, 10, and 20, the claims recite: “the first dummy memory cell is a top dummy memory cell located next to the at least one top select gate without word lines in between". The claims further recite that this first dummy memory cell “is located adjacent to a plug between a first sub-string of the memory string penetrating through a select stack structure and a second sub-string of the memory string penetrating through a memory stack structure.”
The specification describes a memory string comprising a first sub-string that penetrates through a select stack structure (also referred to as the TSG deck) and a second sub-string that penetrates through a memory stack structure, with the two sub-strings connected by a plug (see para. [0077]–[0078] and [0099]). The specification states that the second sub-string includes the first dummy memory cell adjacent to the plug. The first sub-string is described as including a top select gate (see para. [0008], [0010], [0018], [0020], [0099], [0107], and [0108]).
However, the specification does not provide adequate written description support for the first dummy memory cell being “located next to” a top select gate. The relative physical placement of the top select gate within the first sub-string is not clearly described. While the specification states that the first sub-string “includes a top select gate,” it does not specify the exact location of that gate within the sub-string or its precise positional relationship to the plug and the first dummy memory cell in the second sub-string.
Moreover, the drawings are internally inconsistent regarding the structure labeled “TSG.” In Figs. 8 and 9, the structure labeled TSG appears to represent a conventional single top select gate having a thickness comparable to a word line or dummy layer. In contrast, Fig. 11 — the figure upon which Applicant primarily relies — depicts element 1101 (labeled “TSG”) as a thick, multi-layer structure whose vertical dimension is comparable to multiple word lines. The specification further refers to element 1101 as “the first sub-string of the memory string, which is TSG” (para. [0079]). This inconsistency creates ambiguity as to whether “top select gate” refers to a single gate electrode or to the entire upper sub-string.
Because there is no clear and consistent disclosure that the first dummy memory cell (located in the second sub-string adjacent to the plug) is positioned “next to” a top select gate in the first sub-string, a person skilled in the art would not have recognized that the inventor was in possession of the invention as now claimed. Claims 2–9 and 11–19 are rejected for the same reasons, as they depend from claims 1 and 10, respectively.
Response to Arguments
Applicant’s arguments on pg. 9 of Remarks, regarding the written description rejection under 35 U.S.C. § 112(a) have been fully considered but are not persuasive.
Applicant contends that the originally filed specification and drawings (particularly Figs. 8, 9, 11, 18, 19, and 20, along with paragraphs [0077]–[0078] and [0099]) provide adequate support for the limitation that the first dummy memory cell is “a top dummy memory cell located next to the at least one top select gate without word lines in between.” Applicant further argues that the structure inherently places the first dummy memory cell directly below the top select gate.
The Office disagrees. While certain figures (e.g., Figs. 8 and 9) may appear to show a conventional single top select gate positioned above the first dummy memory cell, other figures — most notably Fig. 11, upon which Applicant heavily relies — depict element 1101 (labeled “TSG”) as a thick, multi-layer structure whose vertical dimension is comparable to multiple word lines. The specification itself compounds this ambiguity by stating that element 1101 represents “the first sub-string of the memory string, which includes TSG” (¶ [0079]). This inconsistent use of the term “TSG” across the disclosure creates significant uncertainty as to whether the claimed “top select gate” refers to a single gate electrode or to the entire upper sub-string/deck.
Furthermore, the claims themselves remain internally inconsistent. Independent claims 1, 10, and 20 simultaneously require that the first dummy memory cell is (i) “located next to the at least one top select gate without word lines in between” and (ii) “located adjacent to a plug between a first sub-string of the memory string penetrating through a select stack structure and a second sub-string of the memory string penetrating through a memory stack structure.” The original disclosure consistently places the first dummy memory cell in the second sub-string, adjacent to the plug, while the top select gate resides in the first sub-string. The plug and associated isolation area are positioned between these sub-strings. The originally filed application therefore does not reasonably convey to a person of ordinary skill in the art that the inventor was in possession of a first dummy memory cell positioned “next to” a top select gate in the manner now claimed.
For at least these reasons, claims 1–20 remain rejected under 35 U.S.C. § 112(a) as failing to comply with the written description requirement.
Claim Rejections - 35 USC § 112 - definiteness requirement
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding independent claims 1, 10, and 20, the claims recite that the first dummy memory cell is “a top dummy memory cell located next to the at least one top select gate without word lines in between.” The claims further require that this first dummy memory cell “is located adjacent to a plug between a first sub-string of the memory string penetrating through a select stack structure and a second sub-string of the memory string penetrating through a memory stack structure.”
This claim language is unclear. The specification describes the memory string as having a first sub-string that penetrates the select stack structure (referred to as the TSG deck) and a second sub-string that penetrates the memory stack structure, with the two sub-strings connected by a plug. The first dummy memory cell is consistently described as being part of the second sub-string and adjacent to the plug (see para. [0077]–[0078] and [0099]). In contrast, the top select gate is described as being part of the first sub-string.
The specification does not clearly define the positional relationship between the first dummy memory cell and the top select gate. More importantly, the disclosure is internally inconsistent regarding the meaning of the term “TSG.” In Figs. 8 and 9, the structure labeled “TSG” appears to represent a conventional single top select gate. However, in Fig. 11 — the figure upon which Applicant primarily relies — element 1101 (labeled “TSG”) is depicted as a thick, multi-layer structure whose vertical height is comparable to multiple word lines. The specification itself refers to element 1101 as “the first sub-string of the memory string, which is TSG” (para. [0079]). This inconsistency renders it unclear whether the claimed “top select gate” refers to a single gate electrode or to the entire upper sub-string.
Because the claims require the first dummy memory cell to be both “located next to the at least one top select gate” and “located adjacent to a plug between a first sub-string and a second sub-string,” while the specification does not clearly or consistently define the relationship between these elements, one of ordinary skill in the art would not be able to ascertain the scope of the invention with reasonable certainty.
Claims 2–9 and 11–19 are rejected for the same reasons, as they depend from claims 1 and 10, respectively.
In the interests of compact prosecution, per MPEP 2173.06, the amended phrase “the first dummy memory cell is a top dummy memory cell located next to the at least one top select gate” of independent claims 1, 10 and 20, will be interpreted, consistent with applicant’s originally filed disclosure, to mean “the first dummy memory cell is a dummy memory cell located below the top deck.”
Response to Arguments
Applicant’s arguments on pg. 13 of Remarks, regarding the indefiniteness rejection under 35 U.S.C. § 112(b) have been fully considered but are not persuasive.
Applicant asserts that the claim language is clear when read in light of the specification and drawings, and that the term “next to” has a plain and ordinary meaning in the context of vertically stacked 3D memory structures.
The Office maintains that claims 1–20 remain indefinite. As discussed above in the response to the § 112(a) rejection, the disclosure is internally inconsistent regarding the meaning of “TSG.” Figs. 8 and 9 appear to depict a conventional single top select gate, while Fig. 11 shows element 1101 (labeled “TSG”) as a thick structure spanning the height of multiple word lines, with the specification referring to it as the entire first sub-string. This inconsistency renders it unclear what structure the claims are referring to when they require the first dummy memory cell to be “located next to the at least one top select gate without word lines in between.”
Additionally, the claims create further ambiguity by requiring the first dummy memory cell to be both “next to” a top select gate and “adjacent to a plug between a first sub-string and a second sub-string.” A person of ordinary skill in the art cannot reasonably ascertain the precise scope of the claimed positional relationship. Minor typographical inconsistencies in the specification, as noted by Applicant, are not the basis for the rejection; rather, it is the substantive inconsistency between the claim language and the originally filed disclosure that renders the claims indefinite under 35 U.S.C. § 112(b).
For at least these reasons, claims 1–20 remain rejected under 35 U.S.C. § 112(b) as being indefinite. In the interest of compact prosecution, the phrase “the first dummy memory cell is a top dummy memory cell located next to the at least one top select gate without word lines in between” is interpreted, consistent with the originally filed disclosure, to mean “the first dummy memory cell is a dummy memory cell located below the top deck.”
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-5, 8-14, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20200312413; “Wang” – of Record) in view of Jia et al. (US 10957408; “Jia” – of Record).
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Regarding independent claim 1, Notwithstanding the 112(a) new matter and 112(b) indefiniteness rejections above, Wang discloses a method of operating a memory device, comprising:
programming a first dummy memory cell in a memory string of the memory device (para. 45; "During the programming operation of 3D NAND memory device 300, a set of voltages are applied to each set of lower or upper dummy memory layers 304 or 306. As shown in FIG. 3A"),
wherein the first dummy memory cell is located adjacent to a plug (para. 40; "3D NAND memory string 210 may include two channel structures electrically connected by an inter-deck plug (not shown), which is also known as a dual-cell formation (DCF) structure") between a first sub-string of the memory string penetrating through a select stack structure and a second sub-string of the memory string penetrating through a memory stack structure (Fig. 2:204C dummy memory layers. See also para. 9; "a plurality of first dummy memory layers between the first and second memory decks in the vertical direction." It is noted that the term "select stack structure" appears to be defined in the instant application as "the select stack structure may be for example the afore-mentioned TSG deck" which is illustrated in Fig. 11 as simply the top deck of the dual deck stack which is analogous to Wang's top deck illustrated in Fig. 2:204B),
wherein the select stack structure comprises at least one top select gate (Fig. 3A: where it illustrates 316 drain select transistor at the top of the memory structure. It is well understood in the art that the term “top select gate” is analogous to “drain select transistor”),
and the first dummy memory cell is a top dummy memory cell located next to the at least one top select gate without word lines in between (Fig. 2: 240C. See also para. 9; "a plurality of first dummy memory layers between the first and second memory decks”. As noted in the 112(a) new matter rejection above, this limitation is interpreted to mean “the first dummy memory cell is a dummy memory cell located below the top deck”. It is further noted that there are no word lines between the dummy word cell 204C and the top deck 204B);
Wang is silent with respect to applying a negative voltage to the dummy word lines during the pre-charge stage.
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However, Jia teaches and applying a first bias voltage to a first dummy word line coupled to the first dummy memory cell in a pre-charge stage of a program operation of a memory cell close to the plug in the memory string, the first bias voltage being a negative voltage (Fig. 4 where it illustrates a negative voltage applied to the middle dummy layers (MDL) during the precharge period. See also col. 5, ln. 55-58; "Moreover, the negative pre-pulse signal VP_NDMY (e.g., −2.2 volts) is applied to the middle dummy memory cells MDMC1 to MDMCq disposed between the word line WL (p+1) during the pre-charge period").
Wang and Jia are from the same field of endeavor as applicant’s invention being directed to multi-deck 3D NAND memory. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wang’s poly plug between decks with Jia’s negative pre-charge voltage on the dummy lines. Doing so would reduce the programming interference effect associated with the use of the mid-deck plug thereby improving speed and data integrity.
Regarding claims 2 and 11, Wang and Jia disclose the limitations of claims 1 and 10 respectively. It is noted that the claimed peripheral circuit in the preamble of claim 11 is a component structurally connected with the memory string (see claim 10) and for examination purposes is considered analogous to Jia’s control circuit 20.
As applied, Jia further discloses further comprising:
if the first dummy memory cell is programmed, applying a second bias voltage to the first dummy word line in the pre-charge stage (Fig. 4 where it illustrates a negative voltage applied to the middle dummy layer (MDL) during the precharge period. See also col. 5, ln. 55-58; "Moreover, the negative pre-pulse signal VP_NDMY (e.g., −2.2 volts) is applied to the middle dummy memory cells. It is noted that the number of middle dummy memory cells is not limited and may be varied and designed in accordance with practical system demands and requirements (col. 4, ln 36-42), and therefore there may be only a first dummy memory cell. It is further noted that Jia's pre-charge period is defined as before programming (col. 4, ln. 43)); wherein
the first bias voltage is negative, and the second bias voltage is higher than the first bias voltage (Fig. 4 where it illustrates the second bias voltage on the dummy word line higher than the first bias voltage. It is noted that Jia's timing diagram of the dummy word line bias is analogous to the those of Fig. 16 & 17 in the instant application).
Regarding claims 3 and 12, Wang and Jia disclose the limitations of claims 1 and 10 respectively. It is also noted that the peripheral circuit in claim 12 is a component structurally connected with the memory string (see claim 10) and for examination purposes is considered analogous to Jia’s control circuit 20.
As applied, Jia further discloses further comprising:
in the pre-charge stage, applying a first turn-on voltage to a top select line coupled to the at least one top select gate (Fig. 4 where it shows a voltage of VP_TSG applied to the top select gate (TSG) in the pre-charge period. See also col. 5, ln. 11-13; "the signal waveforms in a pre-charge period are: a top select gate pre-pulse signal VP_TSG").
Regarding claims 4 and 13, Wang and Jia disclose the limitations of claims 1 and 10 respectively. It is also noted that the peripheral circuit in claim 13 is a component structurally connected with the memory string (see claim 10) and for examination purposes is considered analogous to Jia’s control circuit 20.
As applied, Jia further discloses further comprising:
in the pre-charge stage, applying a third bias voltage to a second dummy word line coupled to a second dummy memory cell in the second sub-string, wherein the third bias voltage is negative (Fig.3 where it illustrates a plurality of middle dummy word lines (MDL), and Fig. 4 where it illustrates a negative voltage applied to the middle dummy layer during the precharge period).
Regarding claims 5 and 14, Wang and Jia disclose the limitations of claims 3 and 12 respectively. It is also noted that the peripheral circuit in claim 14 is a component structurally connected with the memory string (see claim 10) and for examination purposes is considered analogous to Jia’s control circuit 20.
As applied, Jia further discloses further comprising:
in the pre-charge stage, applying a first pre-charge voltage to a bit line coupled to the memory string via the top select gate, wherein the first pre-charge voltage is positive (Fig. 4 where it illustrates the positive voltage BP_BL to bit line (BL) in the precharge period, and Fig. 3 where it shows the bit line (BL) coupled to the top select gate (TSG)).
Regarding claims 8 and 17, Wang and Jia disclose the limitations of claims 1 and 10 respectively. It is also noted that the peripheral circuit in claim 17 is a component structurally connected with the memory string (see claim 10) and for examination purposes is considered analogous to Jia’s control circuit 20.
As applied, Jia further discloses further comprising:
in the pre-charge stage, applying a fourth bias voltage to a word line coupled to one of a plurality of memory cells (Fig. 4 where it illustrates VP_SELWL at 0V applied to the selected word line during the precharge period. It is noted that in the instant application, the fourth bias voltage is defined to be 0V (Spec. para. 96)).
Regarding claims 9 and 18, Wang and Jia disclose the limitations of claims 1 and 10 respectively. It is also noted that the peripheral circuit in claim 18 is a component structurally connected with the memory string (see claim 10) and for examination purposes is considered analogous to Jia’s control circuit 20.
As applied, Jia further discloses further comprising:
in a programming stage of the program operation, applying a fourth pass voltage to an unselected word line coupled to an unselected memory cell in the memory string and to the first dummy word line; and applying a program voltage to a word line coupled to the memory cell (Fig. 4 where it illustrates, during the programming period, a 4th voltage on the unselected WL and the middle dummy line (MDL), and then ramping up to the program voltage on the selected word line).
Regarding independent claim 10, Notwithstanding the 112(a) new matter and 112(b) indefiniteness rejections above, Wang discloses a memory device, comprising:
a memory stack structure (Fig. 2:204 memory stack);
a select stack structure on the memory stack structure (Fig. 2:204B. It is noted that the term "select stack structure" appears to be defined in the instant application as "the select stack structure may be for example the afore-mentioned TSG deck" which is illustrated in Fig. 11 as simply the top deck of the dual deck stack which is analogous to Wang's top deck illustrated in Fig. 2:204B.)
and comprising at least one top select gate (Fig. 3A: where it illustrates 316 drain select transistor at the top of the memory structure. It is well understood in the art that the term “top select gate” is analogous to “drain select transistor”);
a memory string comprising (Fig. 2:210 memory string):
a first sub-string penetrating through the select stack structure, and a second sub-string penetrating through the memory stack structure (para. 40; "3D NAND memory string 210 may include two channel structures electrically connected by an inter-deck plug (not shown), which is also known as a dual-cell formation (DCF) structure"), and comprising:
a first dummy memory cell adjacent to a plug (Fig. 2:204C dummy memory layers. See also para. 9; "a plurality of first dummy memory layers between the first and second memory decks in the vertical direction."),
wherein the first dummy memory cell is a top dummy memory cell located next to the at least one top select gate without word lines in between (Fig. 2: 240C. See also para. 9; "a plurality of first dummy memory layers between the first and second memory decks”. As noted in the 112(a) new matter rejection above, this limitation is interpreted to mean “the first dummy memory cell is a dummy memory cell located below the top deck”. It is further noted that there are no word lines between the dummy word cell 204C and the top deck 204B),
and a plurality of memory cells (Fig. 2: 204B);
a peripheral circuit connected with the memory string (Fig. 1:104 peripheral circuit) and configured to:
program the first dummy memory cell (para. 45; "During the programming operation of 3D NAND memory device 300, a set of voltages are applied to each set of lower or upper dummy memory layers 304 or 306. As shown in FIG. 3A"),
Wang is silent with respect to applying a negative voltage to the dummy word lines during the pre-charge stage.
However, Jia teaches and apply a first bias voltage to a first dummy word line coupled to the first dummy memory cell in a pre-charge stage of a program operation of one of the plurality of memory cells close to the plug, wherein the first bias voltage is negative (Fig. 4 where it illustrates a negative voltage applied to the middle dummy layers (MDL) during the precharge period. See also col. 5, ln. 55-58; "Moreover, the negative pre-pulse signal VP_NDMY (e.g., −2.2 volts) is applied to the middle dummy memory cells MDMC1 to MDMCq disposed between the word line WL (p+1) during the pre-charge period").
Wang and Jia are from the same field of endeavor as applicant’s invention being directed to multi-deck 3D NAND memory. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wang’s poly plug between decks with Jia’s negative pre-charge voltage on the dummy lines. Doing so would reduce the programming interference effect associated with the use of the mid-deck plug thereby improving speed and data integrity.
Regarding claim 19, Wang and Jia disclose the limitations of claim 10.
As applied, Wang further discloses wherein the memory string is a NAND memory string (Fig. 3A:308 Nand memory string).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20200312413; “Wang” – of Record) in view of Jia et al. (US 10957408; “Jia” – of Record) and further in view of Wei et al. (US 20210125672; “Wei” – of Record).
Regarding independent claim 20, Notwithstanding the 112(a) new matter and 112(b) indefiniteness rejections above, Wang discloses a memory system comprising:
a memory device comprising:
a memory stack structure (Fig. 2:204 memory stack);
a select stack structure on the memory stack structure (Fig. 2:204B. It is noted that the term "select stack structure" appears to be defined in the instant application as "the select stack structure may be for example the afore-mentioned TSG deck" which is illustrated in Fig. 11 as simply the top deck of the dual deck stack which is analogous to Wang's top deck illustrated in Fig. 2:204B.)
and comprising at least one top select gate (Fig. 3A: where it illustrates 316 drain select transistor at the top of the memory structure. It is well understood in the art that the term “top select gate” is analogous to “drain select transistor”);
a memory string comprising (Fig. 2:210 memory string):
a first sub-string penetrating through the select stack structure, and a second sub-string penetrating through the memory stack structure (para. 40; "3D NAND memory string 210 may include two channel structures electrically connected by an inter-deck plug (not shown), which is also known as a dual-cell formation (DCF) structure"), and comprising
a first dummy memory cell adjacent to a plug, (Fig. 2:204C dummy memory layers. See also para. 9; "a plurality of first dummy memory layers between the first and second memory decks in the vertical direction.");
wherein the first dummy memory cell is a top dummy memory cell located next to the at least one top select gate without word lines in between (Fig. 2: 240C. See also para. 9; "a plurality of first dummy memory layers between the first and second memory decks”. As noted in the 112(a) new matter rejection above, this limitation is interpreted to mean “the first dummy memory cell is a dummy memory cell located below the top deck”. It is further noted that there are no word lines between the dummy word cell 204C and the top deck 204B),
and a plurality of memory cells (Fig. 2: 204B);
a peripheral circuit connected with the memory string (Fig. 1:104 peripheral circuit) and configured to:
program the first dummy memory cell (para. 45; "During the programming operation of 3D NAND memory device 300, a set of voltages are applied to each set of lower or upper dummy memory layers 304 or 306. As shown in FIG. 3A"),
Wang is silent with respect to applying a negative voltage to the dummy word lines during the pre-charge stage.
However, Jia teaches applying a first bias voltage to a first dummy word line coupled to the first dummy memory cell in a pre-charge stage of a program operation of a memory cell close to the plug (Fig. 4 where it illustrates a negative voltage applied to the middle dummy layers (MDL) during the precharge period. See also col. 5, ln. 55-58; "Moreover, the negative pre-pulse signal VP_NDMY (e.g., −2.2 volts) is applied to the middle dummy memory cells MDMC1 to MDMCq disposed between the word line WL (p+1) during the pre-charge period").
Wang and Jia combined are silent with respect to a specific memory controller coupled to the memory device.
However, Wei teaches a memory controller coupled to the memory device and configured to control the memory device through the peripheral circuit (Fig. 3:60 Controller)
Wang, Jia and Wei are from the same field of endeavor as applicant’s invention being directed to 3D NAND memory systems. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wang’s poly plug between decks with Jia’s pre-charge voltage on the dummy lines and further with Wei’s controller. Doing so would reduce the programming interference effect associated with the use of the mid-deck plug thereby improving system speed.
Claims 6-7, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20200312413; “Wang” – of Record) in view of Jia et al. (US 10957408; “Jia” – of Record) and further in view of Wan et al. (US 20220392550; “Wan” – of Record)
Regarding claims 6 and 15, Wang and Jia combined disclose the limitations of claims 1 and 10 respectively. It is noted that the peripheral circuit in claim 15 is a component structurally connected with the memory string (see claim 10) and for examination purposes is considered analogous to Jia’s control circuit 20.
As applied, Wang further discloses the second sub-string further comprises a bottom select gate (Fig. 4:420 source select gate and 410 lower memory deck);
the memory string is coupled to a source line via the bottom select gate (Fig. 1:110 memory string coupled to 114 same source line);
Wang and Jia are silent with respect to the voltage on the bottom select gate and the source line during the pre-charge stage.
However, Wan teaches and further comprising:
in the pre-charge stage, applying a second pass voltage to a bottom select line coupled to a bottom select gate in the second sub-string (Fig. 8:710 precharge period where it illustrates a positive voltage applied to the bottom select gate (BSG); and
applying a second pre-charge voltage to a source line coupled to the memory string via the bottom select gate, wherein the second pre-charge voltage is positive (Fig. 8:710 precharge period where it illustrates a positive voltage applied to the array common source (ACS). See also para. 81; "the first phase 710 can include step 711, in which the bottom select gates BSGs can be turned on, and the array common source ACS can be pre-charged to VDD. As such, the BSGs can be charged to the voltage V.sub.bsg-high, while the ACS can be charged to VDD, as shown in FIG. 8.").
Wang, Jia and Wan are from the same field of endeavor as applicant’s invention being directed to 3D NAND memory systems. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wang’s poly plug between decks with Jia’s pre-charge voltage on the dummy lines and further with Wan’s positive pre-charge on the bottom select gate. Doing so would reduce program disturb by array source coupling (Wan para. 2) and improve data integrity.
Regarding claims 7 and 16, Wang, Jia and Wan combined disclose the limitations of claims 6 and 15 respectively. It is noted that the peripheral circuit in claim 16 is a component structurally connected with the memory string (see claim 10) and for examination purposes is considered analogous to Jia’s control circuit 20.
As applied, Jia further discloses in the pre-charge stage, applying a third pass voltage to a third dummy memory cell between a plurality of memory cells and the bottom select gate (para. 9; "The control circuit 20 is configured to apply a dummy word line pre-pulse signal to the top dummy word lines TDL and the bottom dummy word lines BDL").
Response to Arguments
Applicant's arguments have been fully considered but are not persuasive. Applicant contends on pg. 15 of Remarks that the anticipation rejection of claims 1–5, 8–14, and 17–19 is improper because the cited references fail to disclose or suggest a first dummy memory cell that is a top dummy memory cell “located next to the at least one top select gate without word lines in between,” and that Jia only teaches applying a negative bias to middle dummy word lines (MDL) that are separated from the top select gate by multiple memory cell layers.
Wang discloses a multi-deck 3D NAND memory device having dummy memory layers (e.g., 204C) located at the interface between memory decks, with no word lines between the upper deck and these interface dummy layers. Jia teaches applying a negative pre-pulse voltage to dummy word lines during the pre-charge stage of a program operation to reduce program disturb by repelling electrons. A person of ordinary skill in the art would have been motivated to apply Jia’s negative bias technique to the dummy layers at the deck interface in Wang’s device in order to reduce electron accumulation and program disturb for memory cells located near the inter-deck plug.
Under the interpretation of the claims consistent with the originally filed disclosure (i.e., the first dummy memory cell is a dummy memory cell located below the top deck), the combination of Wang and Jia renders the claimed invention obvious. Applicant’s distinction regarding the precise location of Jia’s middle dummy layers does not overcome the rejection.
The rejections of claims 1–20 under 35 U.S.C. § 103 are therefore deemed proper and maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to James S. Wells whose telephone number is (703)756-1413. The examiner can normally be reached M-F 8:30-5.
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/James S. Wells/Examiner, Art Unit 2825 /Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825
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