DETAILED ACTION
This action is responsive to the amendments filed December 15, 2025. Claims 1-20 are pending. Claims 1, 10, and 20 have been amended. Claims 1, 10, and 20 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 15, 2025, has been entered.
Response to Amendment
Applicant’s Remarks regarding the 112(b) indefiniteness rejections of the prior final Office Action are acknowledged and the amendments to Figs. 11 and 20 accepted. It is noted however that the amendments to Figs. 11 and 20 do not address or cure the deficiency cited in the prior final Office Action. Further, the corresponding 112(a) new matter rejections appear to have been disregarded as it was not addressed in applicant’s Remarks and the reply is therefore not fully responsive. The omission of the response to the 112(a) new matter rejection was confirmed to be an inadvertent oversight in a telephone call with Wenchong Shu on January 20, 2026. As such, the reply is considered a bona fide attempt to respond, and the examiner will exercise discretion to accept as adequate as per MPEP 714.03.
The underlying issue of the claimed explicit physical placement of the “top select gate” within the top deck remains, and therefore both the 112(a) and 112(b) rejections are maintained and repeated herein.
Notwithstanding the repeated rejections below and to clarify further, Figs. 11 and 20 of the instant application appear to simply indicate element 1101 as a structure as which is labeled “TSG”, and which appears to be the entire top deck rather than merely a single gate. Additionally, the specification of the instant application does not elaborate on the location of the claimed feature of the top select gate other than “the first sub-string includes a top select gate” which implies that there are additional components or layers in the first sub-string. It does not set forth that the first sub-string is comprised entirely of, or only of, a top select gate. Likewise, the first sub-string is also referred to within the specification as a ‘stack’ which further implies multiple layers (components) just as in the ‘memory stack’ shown below it as element 1102 in Figs. 11 and 20.
So, for example, in light of the disclosure of the instant application, one of ordinary skill in the art could interpret that claimed top select gate could be at the top of the first sub-string, at the bottom of the first sub-string, or anywhere in between, and there could be other layers and structures in or around the claimed top select gate within the first sub-string.
To overcome the 112(a) and 112(b) rejections, it is suggested that applicant may wish to amend the claims to recite, as consistent with applicant’s originally filed disclosure, “the first dummy memory cell is a dummy memory cell located below the top deck.”
Claim Rejections - 35 USC § 112 - written description requirement
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding independent claims 1, 10, and 20, applicant has previously amended the claims to recite: “the first dummy memory cell is a top dummy memory cell located next to the at least one top select gate (emphasis added). However, also regarding the relative positioning of the first dummy memory cell, the claim further recites: “the first dummy memory cell is located adjacent to a plug between a first sub-string of the memory string penetrating through a select stack structure and a second sub-string of the memory string penetrating through a memory stack structure” (emphasis added). Therefore, the amended claims assert that the top dummy memory cell is both “next to” at least one top select gate AND “adjacent to” the plug between the two decks.
The relevant structural elements of the claim for this analysis are therefore as follows:
“first dummy memory cell”
“top select gate”
“a plug”
“select stack structure”
Paragraph 78 of applicant’s Specification defines the following claimed structural elements and their relative locations:
“…the select stack structure may be for example the afore-mentioned TSG deck”;
“the first sub-string penetrates through the select stack structure” – therefore the first sub-string is part of the TSG deck;
“a first sub-string and a second sub-string connected by a plug” – therefore the plug is between the TSG deck and the second sub-string (or second deck or lower deck); and
“the second sub-string includes a first dummy memory cell adjacent to the plug” – therefore, the first dummy memory cell is positionally adjacent to the plug which is positionally adjacent to the TSG deck
The above relative physical placement of structural elements is also depicted in Figures 11, 18, 19 and 20 of the instant application. It is additionally noted that paragraph 79 of applicant’s Specification further describes the relevant elements with respect to Figure 11: “Fig. 11, 1101 denotes the first sub-string of the memory string, which is TSG; 1102 denotes the second sub-string of the memory string, which includes the first dummy cell IDPDMY.”
Accordingly, determination of the physical placement of the only remaining relevant structural element claimed above is that of the actual “top select gate”. Applicant’s specification, however, uses the terms “top select gate” and “TSG” in three distinct contexts. First, to refer to TSG cuts (which are defined as isolation structures used to split memory blocks – spec. para. 03), and secondly to refer to TSG decks (which are defined as the top section of the stack of a 3D NAND structure – spec. para. 75) and thirdly, as simply the common top select gate (which is defined as a drain select gate (DSG 412) or upper selector – spec. para.67). For examination purposes, the relevant structural element claimed as “top select gate” will be understood using the broadest reasonable interpretation to mean the third context: that of the common top select gate, or drain select gate, or upper selector.
The relative physical placement of the top select gate is indicated in applicant’s Specification only as: “the first sub-string includes a top select gate” (para. 8, 10, 18, 20, 99, 107 and 108), but gives no further teaching as to its exact placement within the TSG deck. Turning to the drawings, Figure 4 includes a drain select gate 412 in schematic form, but none of the other relevant claimed elements in question. It is therefore not possible to evince a determined physical placement relative to the other claimed elements from that Figure. Figures 8 and 9 have an element labeled as TSG but paragraph 75 of applicant’s specification appears to indicate they are representations of the “TSG deck scheme” somehow and therefore not strictly just a “top select gate”. As noted above, Figures 16, 18, 19, and 20 show element 1101 labeled “TSG” but the specification discloses this element is “the first sub-string of the memory string” (para. 79) which is known from the above analysis to be the TSG deck and again, not just a “top select gate”.
Finally, the term “next to” is defined in Merriam-Webster dictionary as “immediately following or adjacent to”. Therefore, because there is no specific support for the location of a top select gate other than somewhere within the TSG deck, and yet the plug and the first dummy memory cell are demonstrably outside and below the TSG deck, even further, having also drawn isolation area between those structures, there is accordingly no support disclosed for the top select gate being next to the first dummy memory cell as amended. Since a person skilled in the art at the time the application was filed would not have recognized that the inventor was in possession of the invention as claimed in view of the disclosure of the application as filed, the claims are rejected for failing the written description requirement.
Claims 2-9 depend from claim 1 and claims 11-19 depend from claim 10. Accordingly, all dependent claims are rejected for at least the same reasons.
Claim Rejections - 35 USC § 112 - definiteness requirement
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
MPEP 2173.02(II) instructs examiners that “Definiteness of claim language must be analyzed, not in a vacuum, but in light of: (A) The content of the particular application disclosure; (B) The teachings of the prior art; and (C) The claim interpretation that would be given by one possessing the ordinary level of skill in the pertinent art at the time the invention was made.” MPEP 2173.03 instructs examiners as follows:
The specification should ideally serve as a glossary to the claim terms so that the examiner and the public can clearly ascertain the meaning of the claim terms. Correspondence between the specification and claims is required by 37 CFR 1.75(d)(1), which provides that claim terms must find clear support or antecedent basis in the specification so that the meaning of the terms may be ascertainable by reference to the specification. Glossaries of terms used in the claims are a helpful device for ensuring adequate definition of terms used in claims. If the specification does not provide the needed support or antecedent basis for the claim terms, the specification should be objected to under 37 CFR 1.75(d)(1). See MPEP § 608.01(o) and MPEP § 2181, subsection IV. Applicant will be required to make appropriate amendment to the description to provide clear support or antecedent basis for the claim terms provided no new matter is introduced, or amend the claim.
A claim, although clear on its face, may also be indefinite when a conflict or inconsistency between the claimed subject matter and the specification disclosure renders the scope of the claim uncertain as inconsistency with the specification disclosure or prior art teachings may make an otherwise definite claim take on an unreasonable degree of uncertainty. In re Moore, 439 F.2d 1232, 1235-36, 169 USPQ 236, 239 (CCPA 1971); In re Cohn, 438 F.2d 989, 169 USPQ 95 (CCPA 1971); In re Hammack, 427 F.2d 1378, 166 USPQ 204 (CCPA 1970). For example, a claim with a limitation of "the clamp means including a clamp body and first and second clamping members, the clamping members being supported by the clamp body" was determined to be indefinite because the terms "first and second clamping members" and "clamp body" were found to be vague in light of the specification which showed no "clamp member" structure being "supported by the clamp body." In re Anderson, 1997 U.S. App. Lexis 167 (Fed. Cir. January 6, 1997) (unpublished). In Cohn, a claim was directed to a process of treating an aluminum surface with an alkali silicate solution and included a further limitation that the surface has an "opaque" appearance. Id. The specification, meanwhile, associated the use of an alkali silicate with a glazed or porcelain-like finish, which the specification distinguished from an opaque finish. Cohn, 438 F.2d at 993, 169 USPQ at 98. Noting that no claim may be read apart from and independent of the supporting disclosure on which it is based, the court found that the claim was internally inconsistent based on the description, definitions and examples set forth in the specification relating to the appearance of the surface after treatment, and therefore indefinite. Id. In addition, inconsistencies in the meaning of terms or phrases between claims may render the scope of the claims to be uncertain. Tvngo Ltd. (BVI) v. LG Elecs. Inc., 861 Fed. Appx. 453, 459-60, 2021 USPQ2d 697 (Fed. Cir. 2021) ("The issue is not breadth of the dependent claims but their use of the disputed phrase in a way that contradicts the independent claims. The dependent claims state that 'said overlay activation criterion includes . . . a user command information,' which conflicts with the independent claim's use of this same phrase."). "When faced with this unknown and undefined phrase, a skilled artisan would look for clarification not only in the specification but also in '[o]ther claims of the patent in question,' which 'can also be valuable sources of enlightenment as to the meaning of a claim term.'" Id. at 460 (quoting Philips v. AWH Corp., 415 F.3d 1303, 1314, 75 USPQ2d 1321, 1327 (Fed. Cir. 2005)).
Regarding independent claims 1, 10, and 20, as indicated supra the written description requirement rejection, applicant does not have adequate written description to support the recent amendment of: “the first dummy memory cell is a top dummy memory cell located next to the at least one top select gate (emphasis added). The relative positioning of the first dummy memory cell is defined by the other claim limitations, such as: “the first dummy memory cell is located adjacent to a plug between a first sub-string of the memory string penetrating through a select stack structure and a second sub-string of the memory string penetrating through a memory stack structure” (emphasis added). Therefore, the amended claims assert that the top dummy memory cell is both “next to” at least one top select gate AND “adjacent to” the plug between the two decks.
The relevant structural elements of the claim for this analysis are therefore as follows:
“first dummy memory cell”
“top select gate”
“a plug”
“select stack structure”
Paragraph 78 of applicant’s Specification defines the following claimed structural elements and their relative locations:
“…the select stack structure may be for example the afore-mentioned TSG deck”
“the first sub-string penetrates through the select stack structure” – therefore the first sub-string is part of the TSG deck.
“a first sub-string and a second sub-string connected by a plug” – therefore the plug is between the TSG deck and the second sub-string (or second deck or lower deck).
“the second sub-string includes a first dummy memory cell adjacent to the plug” – therefore, the first dummy memory cell is positionally adjacent to the plug which is positionally adjacent to the TSG deck
The above relative physical placement of structural elements is also depicted in Figures 11, 18, 19 and 20 of the instant application. It is additionally noted that paragraph 79 of applicant’s Specification further describes the relevant elements with respect to Figure 11: “Fig. 11, 1101 denotes the first sub-string of the memory string, which is TSG; 1102 denotes the second sub-string of the memory string, which includes the first dummy cell IDPDMY.”
Accordingly, determination of the physical placement of the only remaining relevant structural element claimed above is that of the actual “top select gate”. Applicant’s specification unclearly uses the terms “top select gate” and “TSG” in three distinct contexts. First, to refer to TSG cuts (which are defined as isolation structures used to split memory blocks – spec. para. 03), and secondly to refer to TSG decks (which are defined as the top section of the stack of a 3D NAND structure – spec. para. 75) and thirdly, as simply the common top select gate (which is defined as a drain select gate (DSG 412) or upper selector – spec. para.67). For examination purposes, the relevant structural element claimed as “top select gate” will be understood using the broadest reasonable interpretation, consistent with applicant’s originally filed disclosure, to mean the third context: that of the common top select gate, or drain select gate, or upper selector.
The relative physical placement of the top select gate is indicated in applicant’s Specification only as: “the first sub-string includes a top select gate” (para. 8, 10, 18, 20, 99, 107 and 108), but gives no further teaching as to its exact placement within the TSG deck. Turning to the drawings, Figure 4 includes a drain select gate 412 in schematic form, but none of the other relevant claimed elements in question. It is therefore not possible to evince a determined physical placement relative to the other claimed elements from that Figure. Figures 8 and 9 have an element labeled as TSG but paragraph 75 of applicant’s specification appears to indicate they are representations of the “TSG deck scheme” somehow and therefore not strictly just a “top select gate”. As noted above, Figures 16, 18, 19, and 20 show element 1101 labeled “TSG” but the specification discloses this element is “the first sub-string of the memory string” (para. 79) which is known from the above analysis to be the TSG deck and again, not just a “top select gate”.
Finally, the term “next to” is defined in Merriam-Webster dictionary as “immediately following or adjacent to”. Therefore, because there is no specific support for the location of a top select gate other than somewhere within the TSG deck, and yet the plug and the first dummy memory cell are demonstrably outside and below the TSG deck, even further, having also drawn isolation area between those structures the amendment requiring the top select gate to be “next to” the first dummy memory cell is not consistent with the originally filed disclosure. Although the independent claims may appear clear on its face, the independent claims are inconsistent with the disclosure and thus are indefinite per MPEP 2173.03.
Claims 2-9 and 11-19 are rejected for the same reasons for inheriting the inconsistency between the independent claims and the originally filed disclosure.
In the interests of compact prosecution, per MPEP 2173.06, the amended phrase “the first dummy memory cell is a top dummy memory cell located next to the at least one top select gate” of independent claims 1, 10 and 20, will be interpreted, consistent with applicant’s originally filed disclosure, to mean “the first dummy memory cell is a dummy memory cell located below the top deck.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8-14, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20200312413; “Wang” – of Record) in view of Jia et al. (US 10957408; “Jia” – of Record).
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Regarding independent claim 1, Notwithstanding the 112(a) new matter and 112(b) indefiniteness rejections above, Wang discloses a method of operating a memory device, comprising:
programming a first dummy memory cell in a memory string of the memory device (para. 45; "During the programming operation of 3D NAND memory device 300, a set of voltages are applied to each set of lower or upper dummy memory layers 304 or 306. As shown in FIG. 3A"),
wherein the first dummy memory cell is located adjacent to a plug (para. 40; "3D NAND memory string 210 may include two channel structures electrically connected by an inter-deck plug (not shown), which is also known as a dual-cell formation (DCF) structure") between a first sub-string of the memory string penetrating through a select stack structure and a second sub-string of the memory string penetrating through a memory stack structure (Fig. 2:204C dummy memory layers. See also para. 9; "a plurality of first dummy memory layers between the first and second memory decks in the vertical direction." It is noted that the term "select stack structure" appears to be defined in the instant application as "the select stack structure may be for example the afore-mentioned TSG deck" which is illustrated in Fig. 11 as simply the top deck of the dual deck stack which is analogous to Wang's top deck illustrated in Fig. 2:204B),
wherein the select stack structure comprises at least one top select gate (Fig. 3A: where it illustrates 316 drain select transistor at the top of the memory structure. It is well understood in the art that the term “top select gate” is analogous to “drain select transistor”),
and the first dummy memory cell is a top dummy memory cell located next to the at least one top select gate without word lines in between (Fig. 2: 240C. See also para. 9; "a plurality of first dummy memory layers between the first and second memory decks”. As noted in the 112(a) new matter rejection above, this limitation is interpreted to mean “the first dummy memory cell is a dummy memory cell located below the top deck”. It is further noted that there are no word lines between the dummy word cell 204C and the top deck 204B);
Wang is silent with respect to applying a negative voltage to the dummy word lines during the pre-charge stage.
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However, Jia teaches and applying a first bias voltage to a first dummy word line coupled to the first dummy memory cell in a pre-charge stage of a program operation of a memory cell close to the plug in the memory string, the first bias voltage being a negative voltage (Fig. 4 where it illustrates a negative voltage applied to the middle dummy layers (MDL) during the precharge period. See also col. 5, ln. 55-58; "Moreover, the negative pre-pulse signal VP_NDMY (e.g., −2.2 volts) is applied to the middle dummy memory cells MDMC1 to MDMCq disposed between the word line WL (p+1) during the pre-charge period").
Wang and Jia are from the same field of endeavor as applicant’s invention being directed to multi-deck 3D NAND memory. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wang’s poly plug between decks with Jia’s negative pre-charge voltage on the dummy lines. Doing so would reduce the programming interference effect associated with the use of the mid-deck plug thereby improving speed and data integrity.
Regarding claims 2 and 11, Wang and Jia disclose the limitations of claims 1 and 10 respectively. It is noted that the claimed peripheral circuit in the preamble of claim 11 is a component structurally connected with the memory string (see claim 10) and for examination purposes is considered analogous to Jia’s control circuit 20.
As applied, Jia further discloses further comprising:
if the first dummy memory cell is programmed, applying a second bias voltage to the first dummy word line in the pre-charge stage (Fig. 4 where it illustrates a negative voltage applied to the middle dummy layer (MDL) during the precharge period. See also col. 5, ln. 55-58; "Moreover, the negative pre-pulse signal VP_NDMY (e.g., −2.2 volts) is applied to the middle dummy memory cells. It is noted that the number of middle dummy memory cells is not limited and may be varied and designed in accordance with practical system demands and requirements (col. 4, ln 36-42), and therefore there may be only a first dummy memory cell. It is further noted that Jia's pre-charge period is defined as before programming (col. 4, ln. 43)); wherein
the first bias voltage is negative, and the second bias voltage is higher than the first bias voltage (Fig. 4 where it illustrates the second bias voltage on the dummy word line higher than the first bias voltage. It is noted that Jia's timing diagram of the dummy word line bias is analogous to the those of Fig. 16 & 17 in the instant application).
Regarding claims 3 and 12, Wang and Jia disclose the limitations of claims 1 and 10 respectively. It is also noted that the peripheral circuit in claim 12 is a component structurally connected with the memory string (see claim 10) and for examination purposes is considered analogous to Jia’s control circuit 20.
As applied, Jia further discloses further comprising:
in the pre-charge stage, applying a first turn-on voltage to a top select line coupled to the at least one top select gate (Fig. 4 where it shows a voltage of VP_TSG applied to the top select gate (TSG) in the pre-charge period. See also col. 5, ln. 11-13; "the signal waveforms in a pre-charge period are: a top select gate pre-pulse signal VP_TSG").
Regarding claims 4 and 13, Wang and Jia disclose the limitations of claims 1 and 10 respectively. It is also noted that the peripheral circuit in claim 13 is a component structurally connected with the memory string (see claim 10) and for examination purposes is considered analogous to Jia’s control circuit 20.
As applied, Jia further discloses further comprising:
in the pre-charge stage, applying a third bias voltage to a second dummy word line coupled to a second dummy memory cell in the second sub-string, wherein the third bias voltage is negative (Fig.3 where it illustrates a plurality of middle dummy word lines (MDL), and Fig. 4 where it illustrates a negative voltage applied to the middle dummy layer during the precharge period).
Regarding claims 5 and 14, Wang and Jia disclose the limitations of claims 3 and 12 respectively. It is also noted that the peripheral circuit in claim 14 is a component structurally connected with the memory string (see claim 10) and for examination purposes is considered analogous to Jia’s control circuit 20.
As applied, Jia further discloses further comprising:
in the pre-charge stage, applying a first pre-charge voltage to a bit line coupled to the memory string via the top select gate, wherein the first pre-charge voltage is positive (Fig. 4 where it illustrates the positive voltage BP_BL to bit line (BL) in the precharge period, and Fig. 3 where it shows the bit line (BL) coupled to the top select gate (TSG)).
Regarding claims 8 and 17, Wang and Jia disclose the limitations of claims 1 and 10 respectively. It is also noted that the peripheral circuit in claim 17 is a component structurally connected with the memory string (see claim 10) and for examination purposes is considered analogous to Jia’s control circuit 20.
As applied, Jia further discloses further comprising:
in the pre-charge stage, applying a fourth bias voltage to a word line coupled to one of a plurality of memory cells (Fig. 4 where it illustrates VP_SELWL at 0V applied to the selected word line during the precharge period. It is noted that in the instant application, the fourth bias voltage is defined to be 0V (Spec. para. 96)).
Regarding claims 9 and 18, Wang and Jia disclose the limitations of claims 1 and 10 respectively. It is also noted that the peripheral circuit in claim 18 is a component structurally connected with the memory string (see claim 10) and for examination purposes is considered analogous to Jia’s control circuit 20.
As applied, Jia further discloses further comprising:
in a programming stage of the program operation, applying a fourth pass voltage to an unselected word line coupled to an unselected memory cell in the memory string and to the first dummy word line; and applying a program voltage to a word line coupled to the memory cell (Fig. 4 where it illustrates, during the programming period, a 4th voltage on the unselected WL and the middle dummy line (MDL), and then ramping up to the program voltage on the selected word line).
Regarding independent claim 10, Notwithstanding the 112(a) new matter and 112(b) indefiniteness rejections above, Wang discloses a memory device, comprising:
a memory stack structure (Fig. 2:204 memory stack);
a select stack structure on the memory stack structure (Fig. 2:204B. It is noted that the term "select stack structure" appears to be defined in the instant application as "the select stack structure may be for example the afore-mentioned TSG deck" which is illustrated in Fig. 11 as simply the top deck of the dual deck stack which is analogous to Wang's top deck illustrated in Fig. 2:204B.)
and comprising at least one top select gate (Fig. 3A: where it illustrates 316 drain select transistor at the top of the memory structure. It is well understood in the art that the term “top select gate” is analogous to “drain select transistor”);
a memory string comprising (Fig. 2:210 memory string):
a first sub-string penetrating through the select stack structure, and a second sub-string penetrating through the memory stack structure (para. 40; "3D NAND memory string 210 may include two channel structures electrically connected by an inter-deck plug (not shown), which is also known as a dual-cell formation (DCF) structure"), and comprising:
a first dummy memory cell adjacent to a plug (Fig. 2:204C dummy memory layers. See also para. 9; "a plurality of first dummy memory layers between the first and second memory decks in the vertical direction."),
wherein the first dummy memory cell is a top dummy memory cell located next to the at least one top select gate without word lines in between (Fig. 2: 240C. See also para. 9; "a plurality of first dummy memory layers between the first and second memory decks”. As noted in the 112(a) new matter rejection above, this limitation is interpreted to mean “the first dummy memory cell is a dummy memory cell located below the top deck”. It is further noted that there are no word lines between the dummy word cell 204C and the top deck 204B),
and a plurality of memory cells (Fig. 2: 204B);
a peripheral circuit connected with the memory string (Fig. 1:104 peripheral circuit) and configured to:
program the first dummy memory cell (para. 45; "During the programming operation of 3D NAND memory device 300, a set of voltages are applied to each set of lower or upper dummy memory layers 304 or 306. As shown in FIG. 3A"),
Wang is silent with respect to applying a negative voltage to the dummy word lines during the pre-charge stage.
However, Jia teaches and apply a first bias voltage to a first dummy word line coupled to the first dummy memory cell in a pre-charge stage of a program operation of one of the plurality of memory cells close to the plug, wherein the first bias voltage is negative (Fig. 4 where it illustrates a negative voltage applied to the middle dummy layers (MDL) during the precharge period. See also col. 5, ln. 55-58; "Moreover, the negative pre-pulse signal VP_NDMY (e.g., −2.2 volts) is applied to the middle dummy memory cells MDMC1 to MDMCq disposed between the word line WL (p+1) during the pre-charge period").
Wang and Jia are from the same field of endeavor as applicant’s invention being directed to multi-deck 3D NAND memory. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wang’s poly plug between decks with Jia’s negative pre-charge voltage on the dummy lines. Doing so would reduce the programming interference effect associated with the use of the mid-deck plug thereby improving speed and data integrity.
Regarding claim 19, Wang and Jia disclose the limitations of claim 10.
As applied, Wang further discloses wherein the memory string is a NAND memory string (Fig. 3A:308 Nand memory string).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20200312413; “Wang” – of Record) in view of Jia et al. (US 10957408; “Jia” – of Record) and further in view of Wei et al. (US 20210125672; “Wei” – of Record).
Regarding independent claim 20, Notwithstanding the 112(a) new matter and 112(b) indefiniteness rejections above, Wang discloses a memory system comprising:
a memory device comprising:
a memory stack structure (Fig. 2:204 memory stack);
a select stack structure on the memory stack structure (Fig. 2:204B. It is noted that the term "select stack structure" appears to be defined in the instant application as "the select stack structure may be for example the afore-mentioned TSG deck" which is illustrated in Fig. 11 as simply the top deck of the dual deck stack which is analogous to Wang's top deck illustrated in Fig. 2:204B.)
and comprising at least one top select gate (Fig. 3A: where it illustrates 316 drain select transistor at the top of the memory structure. It is well understood in the art that the term “top select gate” is analogous to “drain select transistor”);
a memory string comprising (Fig. 2:210 memory string):
a first sub-string penetrating through the select stack structure, and a second sub-string penetrating through the memory stack structure (para. 40; "3D NAND memory string 210 may include two channel structures electrically connected by an inter-deck plug (not shown), which is also known as a dual-cell formation (DCF) structure"), and comprising
a first dummy memory cell adjacent to a plug, (Fig. 2:204C dummy memory layers. See also para. 9; "a plurality of first dummy memory layers between the first and second memory decks in the vertical direction.");
wherein the first dummy memory cell is a top dummy memory cell located next to the at least one top select gate without word lines in between (Fig. 2: 240C. See also para. 9; "a plurality of first dummy memory layers between the first and second memory decks”. As noted in the 112(a) new matter rejection above, this limitation is interpreted to mean “the first dummy memory cell is a dummy memory cell located below the top deck”. It is further noted that there are no word lines between the dummy word cell 204C and the top deck 204B),
and a plurality of memory cells (Fig. 2: 204B);
a peripheral circuit connected with the memory string (Fig. 1:104 peripheral circuit) and configured to:
program the first dummy memory cell (para. 45; "During the programming operation of 3D NAND memory device 300, a set of voltages are applied to each set of lower or upper dummy memory layers 304 or 306. As shown in FIG. 3A"),
Wang is silent with respect to applying a negative voltage to the dummy word lines during the pre-charge stage.
However, Jia teaches applying a first bias voltage to a first dummy word line coupled to the first dummy memory cell in a pre-charge stage of a program operation of a memory cell close to the plug (Fig. 4 where it illustrates a negative voltage applied to the middle dummy layers (MDL) during the precharge period. See also col. 5, ln. 55-58; "Moreover, the negative pre-pulse signal VP_NDMY (e.g., −2.2 volts) is applied to the middle dummy memory cells MDMC1 to MDMCq disposed between the word line WL (p+1) during the pre-charge period").
Wang and Jia combined are silent with respect to a specific memory controller coupled to the memory device.
However, Wei teaches a memory controller coupled to the memory device and configured to control the memory device through the peripheral circuit (Fig. 3:60 Controller)
Wang, Jia and Wei are from the same field of endeavor as applicant’s invention being directed to 3D NAND memory systems. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wang’s poly plug between decks with Jia’s pre-charge voltage on the dummy lines and further with Wei’s controller. Doing so would reduce the programming interference effect associated with the use of the mid-deck plug thereby improving system speed.
Claims 6-7, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20200312413; “Wang” – of Record) in view of Jia et al. (US 10957408; “Jia” – of Record) and further in view of Wan et al. (US 20220392550; “Wan” – of Record)
Regarding claims 6 and 15, Wang and Jia combined disclose the limitations of claims 1 and 10 respectively. It is noted that the peripheral circuit in claim 15 is a component structurally connected with the memory string (see claim 10) and for examination purposes is considered analogous to Jia’s control circuit 20.
As applied, Wang further discloses the second sub-string further comprises a bottom select gate (Fig. 4:420 source select gate and 410 lower memory deck);
the memory string is coupled to a source line via the bottom select gate (Fig. 1:110 memory string coupled to 114 same source line);
Wang and Jia are silent with respect to the voltage on the bottom select gate and the source line during the pre-charge stage.
However, Wan teaches and further comprising:
in the pre-charge stage, applying a second pass voltage to a bottom select line coupled to a bottom select gate in the second sub-string (Fig. 8:710 precharge period where it illustrates a positive voltage applied to the bottom select gate (BSG); and
applying a second pre-charge voltage to a source line coupled to the memory string via the bottom select gate, wherein the second pre-charge voltage is positive (Fig. 8:710 precharge period where it illustrates a positive voltage applied to the array common source (ACS). See also para. 81; "the first phase 710 can include step 711, in which the bottom select gates BSGs can be turned on, and the array common source ACS can be pre-charged to VDD. As such, the BSGs can be charged to the voltage V.sub.bsg-high, while the ACS can be charged to VDD, as shown in FIG. 8.").
Wang, Jia and Wan are from the same field of endeavor as applicant’s invention being directed to 3D NAND memory systems. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wang’s poly plug between decks with Jia’s pre-charge voltage on the dummy lines and further with Wan’s positive pre-charge on the bottom select gate. Doing so would reduce program disturb by array source coupling (Wan para. 2) and improve data integrity.
Regarding claims 7 and 16, Wang, Jia and Wan combined disclose the limitations of claims 6 and 15 respectively. It is noted that the peripheral circuit in claim 16 is a component structurally connected with the memory string (see claim 10) and for examination purposes is considered analogous to Jia’s control circuit 20.
As applied, Jia further discloses in the pre-charge stage, applying a third pass voltage to a third dummy memory cell between a plurality of memory cells and the bottom select gate (para. 9; "The control circuit 20 is configured to apply a dummy word line pre-pulse signal to the top dummy word lines TDL and the bottom dummy word lines BDL").
Response to Arguments
Applicant argues the obviousness rejections of independent claims 1, 10, and 20 over the combination of Wang, Jia (and Wan in the case of claim 20) is improper because these references do not teach applying a negative voltage to “the first dummy memory cell [which] is a top dummy memory cell located next to the at least one top select gate without word lines in between” as cited. To support their argument, applicant asserts that Jia shows the middle dummy memory cell receives the negative voltage.
Applicant’s arguments have been fully considered but are not persuasive. Based upon applicant’s originally filed disclosure (see 112(a) written description requirement and 112(b) definiteness requirement rejections supra), the claimed positioning of “first dummy memory cell” does not distinguish from the applied prior art because of the language of the claim being inconsistent with the originally filed disclosure (MPEP 2173.03) and the claim interpretation applied that is consistent with the disclosure per MPEP 2111 and 2173.06.
The claimed “first dummy memory cell is a top dummy memory cell located next to the at least one top select gate” of independent claims 1, 10 and 20, is interpreted, consistent with applicant’s originally filed disclosure, to mean “the first dummy memory cell is a dummy memory cell located below the top deck” because applicant’s Specification paragraph 78 explains:
“…the select stack structure may be for example the afore-mentioned TSG deck”;
“the first sub-string penetrates through the select stack structure” – therefore the first sub-string is part of the TSG deck;
“a first sub-string and a second sub-string connected by a plug” – therefore the plug is between the TSG deck and the second sub-string (or second deck or lower deck); and
“the second sub-string includes a first dummy memory cell adjacent to the plug” – therefore, the first dummy memory cell is positionally adjacent to the plug which is positionally adjacent to the TSG deck.
Moreover, as interpreted above, the amended language “without word lines in between” is effectively meaningless in context of the top deck because the top deck necessarily starts directly above the dummy memory cells between the decks.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yan et al. (US 20220293626) – top dummy cells within a multi deck 3d nonvolatile memory device.
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/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825