Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-10, in the reply filed on December 19, 2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5, 8 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (US 2020/0027893).
Regarding claim 1, Yang discloses a three-dimensional (3D) memory device, comprising:
a first semiconductor structure having a core region (A1) and a non-array region (A2) [Figs. 2A and 3A and paragraphs 0053-0054], the first semiconductor structure comprising:
an array of channel structures (146c) in the core region [Figs. 2A and 3A and paragraph 0071];
a substrate layer (103) extending from the non-array region (A2) to the core region (A1) and being in contact with the array of channel structures (146c) [Fig. 3A];
an insulating structure (106) [ Fig. 3A and paragraph 0049], comprising a first portion extending along a lateral direction from the non-array region (A2) to the core region (A1) and a second portion extending along a vertical direction through the substrate layer (103) in the non-array region (A2) [ Fig. 3A and paragraph 0049], wherein the second portion of the insulating structure (106) surrounds the core region (A1) [Fig. 2A and paragraph 0054]; and
contact structures (183a) penetrating through the second portion of the insulating structure (106), wherein the contact structures are electrically insulated (106) from the substrate layer (103) by the insulating structure (106) [Fig. 3A].
Regarding claim 2, Yang discloses wherein the insulating structure insulates (106) the contact structures (183A) from one another, and a minimum lateral width of the contact structures (183A) is less than a minimum lateral distance between the contact structures and the substrate layer [Figs. 2A and 3A].
Regarding claim 5, Yang discloses wherein the insulating structure (106) comprises at least one of silicon oxide, silicon nitride, or silicon oxynitride [paragraph 0049].
Regarding claim 8, Yang discloses wherein the second portion of the insulating structure (106) extends vertically in the non-array region (A2), and the non-array region (A2) is located between multiple core regions (A1) [Figs. 2A and 3A, and paragraph 0054].
Regarding claim 10, Yang discloses a system, comprising a memory device (MA) and a memory controller (6),
wherein the memory device is configured to store data [Figs. 1A-1B], comprising:
a first semiconductor structure having a core region (A1) and a non-array region (A2), the first semiconductor structure comprising:
an array of channel structures (146c) in the core region [Fig. 3A];
a substrate layer (103) extending from the non-array region to the core region and being in contact with the array of channel structures (146c) [Fig. 3A];
an insulating structure (106), comprising a first portion extending along a lateral direction from the non-array region (A2) to the core region (A1) and a second portion extending along a vertical direction through the substrate layer (103) in the non-array region, wherein the second portion of the insulating structure (106) surrounds the core region (A1) [Figs. 2A and 3A and paragraphs 0049 and 0054]; and
contact structures (183a) penetrating through the second portion of the insulating structure [Fig. 3A],
wherein the contact structures (183a) are electrically insulated from the substrate layer by the insulating structure (106), and a minimum lateral width of the contact structures is less than a minimum lateral distance between the contact structures and the substrate layer (103) [Fig. 3A], and
a second semiconductor structure (50/80) bonded 1 with the first semiconductor structure, the second semiconductor structure comprising a transistor (PTR) [Fig. 3A],
wherein the memory controller is coupled to the memory device and configured to control the memory device [Fig. 1A].
Allowable Subject Matter
Claims 3-4, 6-7, and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday.
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/Jose R Diaz/Primary Examiner, Art Unit 2815
1 The method of forming the device as recited in the claim does not germane to the issue of patentability of the device itself. Therefore, this limitation has been given little patentable weight. Note that a "product by process" claim is directed to the product per se, no matter how actually made, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al, 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Note that applicant has the burden of proof in such cases, as the above case law makes clear.
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