DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (U.S. Publication No. 2021/0066279)
Regarding claim 1¸ Yu teaches a semiconductor package, comprising:
a first redistribution wiring layer (Fig. 16, first RDL 120B/130B) having first and second surfaces opposite to each other (top and bottom surfaces), the first redistribution wiring layer including a plurality of first redistribution wires (wires 134) and a plurality of landing pads (not specifically shown, but inherently connected to solder 140 in order for the device to function) electrically connected to the first redistribution wires, the plurality of landing pads exposed from the second surface (inherent that the pads would need to be exposed from the bottom of 130B in order to connect to solder 140);
a second redistribution wiring layer (second redistribution wiring layer at 130A/120A)) disposed on the first surface of the first redistribution wiring layer (Fig. 16), the second redistribution wiring layer including an insulating layer (insulating layer 120A), a logic semiconductor chip (logic chip LD1) provided in the insulating layer (Fig. 16), second redistribution wires (connectors 114) electrically connected to the logic semiconductor chip (Fig. 16), and third redistribution wires (wires 134 in 130A and unlabeled vias in 120A) electrically connected to the first redistribution wires, the third redistribution wires extending to penetrate the insulating layer (see Fig. 16);
a third redistribution wiring layer (third redistribution layer 150) disposed on the second redistribution wiring layer, the third redistribution wiring layer including fourth redistribution wires (fourth wires 154) electrically connected to the third redistribution wires (Fig. 16); and
a semiconductor substrate (substrate HC) disposed on an upper surface of the third redistribution wire layer (Fig. 16), the semiconductor substrate including at least one memory semiconductor chip (memory chip MD) electrically connected to the fourth redistribution wires (Fig. 16).
Regarding claim 2¸ Yu teaches the semiconductor package of claim 1, wherein the first redistribution wiring layer further includes a plurality of external connection bumps (bumps 140) that are disposed on the landing pads, respectively (Fig. 16).
Regarding claim 3¸ Yu teaches the semiconductor package of claim 1
wherein each of the third redistribution wires includes a redistribution line electrically connected to the first redistribution wire (see Fig. 16, wires in 130A connect to 130B through vias 206) and a redistribution via (via not labeled, but see in 120A) provided on the redistribution line, and
wherein the redistribution via penetrates at least a portion of the insulating layer to be electrically connected to the fourth redistribution wires (Fig. 16).
Regarding claim 4¸ Yu teaches the semiconductor package of claim 3, wherein the third redistribution wiring layer includes a chip mounting region (central region) in which the logic semiconductor chip is arranged, and a peripheral region surrounding the chip mounting region (peripheral region, see Fig. 16).
Regarding claim 5¸ Yu teaches the semiconductor package of claim 4, wherein the redistribution vias of the third redistribution wires are provided in the peripheral region (see Fig. 16).
Regarding claim 6¸ Yu teaches the semiconductor package of claim 1, wherein the second redistribution wiring layer further includes a chip mounting film (chip mounting film at top of LD1, labeled 112 in Fig. 1A) that bonds the third redistribution wiring layer to an upper surface of the logic semiconductor chip (Fig. 1A and 16).
Regarding claim 7¸ Yu teaches the semiconductor package of claim 1, wherein the logic semiconductor chip further includes a plurality of first chip pads (pads 114) that are arranged to face the first surface of the first redistribution wiring layer (Fig. 16, bottom pads 114), the plurality of first chip pads are electrically connected to the second redistribution wires, respectively (Fig. 16, connection not specifically shown, but inherent for functionality of the chip).
Regarding claim 8¸ Yu teaches the semiconductor package of claim 1, wherein the memory semiconductor chip further includes a plurality of second chip pads (pads at 166) that are electrically connected to at least some of the fourth redistribution wires (Fig. 16).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 11-12, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Kim et al. (U.S. Publication No. 2023/0260865)
Regarding claim 9¸ Yu teaches the semiconductor package of claim 1, wherein the semiconductor substrate includes:
a silicon substrate (silicon substrate HC) having a cavity in which the memory semiconductor chip is accommodated (see Fig. 16, central portion where chip is located); and
a molding member (molding 170) filling a gap between an inner surface of the cavity and an outer surface of the memory semiconductor chip (Fig. 16).
Yu does not specifically teach that the chip is accommodated in a cavity in a single substrate. However, Kim teaches that a similar heat spreader substrate can be a single sheet having a cavity in the middle where the chip(s) are accommodated (see Kim Fig. 3B and 3D). It would have been obvious to a person of skill in the art at the time of the effective filing date that the multiple heat spreader substrates of Yu could have been replaced by the single heat spreader substrate of Kim because this allows for a more complete heat conduction path around the entire chip, instead of isolated sections of heat conduction.
Regarding claim 11¸ Yu teaches a method of manufacturing a semiconductor package, the method comprising:
forming at least one cavity (Fig. 16, cavity where chips MD are located) vertically penetrating at least a portion of a semiconductor substrate (semiconductor substrate HC), the semiconductor substrate having upper and lower surfaces opposite to each other (Fig. 16);
arranging a memory semiconductor chip (memory chip MD) in the cavity such that second chip pads face the lower surface (Fig. 16, chip pads at 166);
forming a third redistribution wiring layer (third wiring layer 150) on the lower surface of the semiconductor substrate, the third redistribution wiring layer having fourth redistribution wires (wires 154) that are electrically connected to the second chip pads (Fig. 16);
arranging a logic semiconductor chip (LD1) on the third redistribution wiring layer such that a rear surface of the logic semiconductor chip faces the third redistribution wiring layer (Fig. 16);
forming a second redistribution wiring layer (120A/130A) on the third redistribution wiring layer, the second redistribution wiring layer having second redistribution wires (wires 134) and third redistribution wires (unlabeled vias in 120A), the third redistribution wires electrically connected to the fourth redistribution wires (Fig. 16), the second redistribution wires electrically connected to first chip pads (pads 114) that are exposed from a front surface of the logic semiconductor chip (Fig. 16); and
forming a first redistribution wiring layer (first wiring layer 120B/130B) having first redistribution wires (first wires 206/134) and landing pads (not labeled, but where solder 140 is attached) on the second redistribution wiring layer (Fig. 16), the first redistribution wires electrically connected to the second and third redistribution wires (Fig. 16), the landing pads electrically connected to the first redistribution wires and exposed from a bottom surface of the first redistribution wiring layer (Fig. 16, it is inherent that they would be exposed in order to connect to solder 140).
Yu does not specifically teach that the chip is accommodated in a cavity in a single substrate. However, Kim teaches that a similar heat spreader substrate can be a single sheet having a cavity in the middle where the chip(s) are accommodated (see Kim Fig. 3B and 3D). It would have been obvious to a person of skill in the art at the time of the effective filing date that the multiple heat spreader substrates of Yu could have been replaced by the single heat spreader substrate of Kim because this allows for a more complete heat conduction path around the entire chip, instead of isolated sections of heat conduction.
Regarding claim 12¸ Yu in view of Kim teaches the method of claim 11, wherein the arranging the memory semiconductor chip into the cavity further includes filling a gap between an inner surface of the cavity and an outer surface of the memory semiconductor chip with a molding member (Yu Fig. 16, molding member 170; see also Kim Fig. 3E, molding member 224).
Regarding claim 15¸ Yu in view of Kim teaches the method of claim 11,
wherein the third redistribution wiring layer includes a chip mounting region (region where LD1 is located) in which the logic semiconductor chip is arranged (Fig. 16), and a peripheral region surrounding the chip mounting region (Fig. 16), and
wherein the forming the third redistribution wiring layer further includes forming the fourth redistribution wires to be exposed from the peripheral region (Fig. 16, exposed from dielectric 120A where vias are located).
Regarding claim 16¸ Yu in view of Kim teaches the method of claim 15, wherein the arranging the logic semiconductor chip further includes arranging the logic semiconductor chip on the chip mounting region (Fig. 16).
Regarding claim 17¸ Yu in view of Kim teaches the method of claim 11, wherein the arranging the logic semiconductor chip further includes adhering the rear surface of the logic semiconductor chip on the third redistribution wiring layer through a chip mounting film (Fig. 1A, chip mounting film labeled 112).
Regarding claim 18¸ Yu in view of Kim teaches the method of claim 11, wherein the forming the first redistribution wiring layer further includes forming a plurality of external connection bumps (Fig. 16, bumps 140) on the landing pads, respectively.
Regarding claim 19¸ Yu in view of Kim teaches the method of claim 11, wherein each of the first to fourth redistribution wires include at least one of copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), molybdenum (Mo), gold (Au), silver (Ag), chromium (Cr), Tin (Sn) and Titanium (Ti) (paragraph [0034]).
Regarding claim 20¸ Yu teaches a semiconductor package, comprising:
a first redistribution wiring layer (Fig. 16, first redistribution wiring layer 130B/120B) having first and second surfaces opposite to each other (top and bottom), the first redistribution wiring layer including a plurality of first redistribution wires (wires 134/206) and a plurality of landing pads electrically connected to the first redistribution wires (pads not labeled, but at solder 140), the plurality of landing pads exposed from the second surface (it is inherent that they are exposed in order to connect to solder 140);
a second redistribution wiring layer (second layer 130A/120A) disposed on the first surface of the first redistribution wiring layer; the second redistribution wiring layer including an insulating layer (insulating layer 120A), a logic semiconductor chip (chip LD1) provided in the insulating layer (Fig. 16), second redistribution wires (wires 134) electrically connected to the logic semiconductor chip and the first redistribution wires (Fig. 16), and third redistribution wires (wires unlabeled, but see vias in 120A) electrically connected to the first redistribution wires and extending to penetrate the insulating layer (Fig. 16);
a third redistribution wiring layer (third layer 150) disposed on the second redistribution wiring layer, the third redistribution wiring layer having fourth redistribution wires (wires 154) that are electrically connected to the third redistribution wires (Fig. 16);
a chip mounting film (Fig. 1A, labeled 112) adhering the third redistribution wiring layer and an upper surface of the logic semiconductor chip (Fig. 16); and
a semiconductor substrate (semiconductor substrate HC) disposed on an upper surface of the third redistribution wiring layer, the semiconductor substrate including at least one memory semiconductor chip (chip MD) electrically connected to the fourth redistribution wires (Fig. 16), a cavity in which the memory semiconductor chip is accommodated therein (Fig. 16), a molding member (molding member 170) provided between the cavity and the memory semiconductor chip.
Yu does not specifically teach that the chip is accommodated in a cavity in a single substrate. However, Kim teaches that a similar heat spreader substrate can be a single sheet having a cavity in the middle where the chip(s) are accommodated (see Kim Fig. 3B and 3D). It would have been obvious to a person of skill in the art at the time of the effective filing date that the multiple heat spreader substrates of Yu could have been replaced by the single heat spreader substrate of Kim because this allows for a more complete heat conduction path around the entire chip, instead of isolated sections of heat conduction.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yu.
Regarding claim 10¸ Yu teaches the semiconductor package of claim 1, wherein a distance from the second surface of the first redistribution wiring layer to the upper surface of the third redistribution wiring layer is within a range of 0.85mm to 1mm.
Yu does not specifically teach the height of the third redistribution layer. However, it would have been obvious to a person of skill in the art at the time of the effective filing date that the non-critical distance could have been optimized through routine experimentation or calculation to be any value, including 0.85-1 mm, depending on the height of the chip. See MPEP 2144.05(II)(A).
Allowable Subject Matter
Claims 13-14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 13-14, the prior art, alone or in combination, fails to teach or suggest forming the second redistribution wires and the third redistribution wires in the through openings.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Evan G Clinton whose telephone number is (571)270-0525. The examiner can normally be reached Monday-Friday at 8:30am to 5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EVAN G CLINTON/Primary Examiner, Art Unit 2899