Prosecution Insights
Last updated: October 04, 2026
Application No. 18/224,110

SEMICONDUCTOR DEVICE HAVING SEGMENTED RESURF REGION ENTIRELY COVERING SUPER JUNCTION P-N PILLARS

Non-Final OA §103
Filed
Jul 20, 2023
Priority
Aug 30, 2019 — RE 10-2019-0107447 +1 more
Examiner
MAI, ANH D
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Power Master Semiconductor Co. Ltd.
OA Round
3 (Non-Final)
38%
Grant Probability
At Risk
3-4
OA Rounds
5m
Est. Remaining
47%
With Interview

Examiner Intelligence

Grants only 38% of cases
38%
Career Allowance Rate
267 granted / 709 resolved
-30.3% vs TC avg
Moderate +10% lift
Without
With
+9.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
39 currently pending
Career history
765
Total Applications
across all art units

Statute-Specific Performance

§101
1.9%
-38.1% vs TC avg
§103
45.1%
+5.1% vs TC avg
§102
21.8%
-18.2% vs TC avg
§112
30.0%
-10.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 709 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 13, 2026 has been entered. Status of the Claims Amendment filed July 26, 2026 is acknowledged. Claim 1 has been amended. Claims 1-10 are pending. Action on merits of claims 1-10 follows. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over SAITO et al. (US. Pub. No. 2007/0138543) of record, in view of TAMAKI et al. (US. Pub. No. 2011/0115033). With respect to claim 1, SAITO ‘543 teaches a semiconductor device substantially as claimed including: a first semiconductor layer (2) having an N-type of conductivity; and a second semiconductor layer (12) that is formed on the first semiconductor layer (2), and including an active region, a frame region, and a termination region, wherein the active region comprises a plurality of first P-pillars (34) and first N-pillars (33) formed between the plurality of first P-pillars (34), the frame region comprises an upper frame region (5) formed to extend in a first direction while having a P-type of conductivity, and a lower frame region that is formed below the upper frame region (5) and including a plurality of second P-pillars (34) and second N-pillars (33) formed between the plurality of second P-pillars (34), and the termination region comprises an upper termination region (17) that extends in the first direction while having the P-type of conductivity, a middle termination region having the N-type of conductivity and formed below the upper termination region (17), and a lower termination region formed below the middle termination region and including a plurality of third P-pillars (34) and third N-pillars (34) formed between the plurality of third P-pillars (34), wherein the upper termination region (17) comprises an area disposed within the upper termination region, wherein the area is disposed in the upper termination region (17) above the middle termination region and the lower termination region, and wherein the active region further comprises P body regions (5) and surface N regions (33) alternately arranged in the active region, each of the P body regions (5) includes an N+ region (6), and an outermost one of the surface N regions (33) is disposed between the N+ region (6) and the upper frame region (17) along the first direction. (See FIG. 20). Thus, SAITO is shown to teach all the features of the claim with the exception of explicitly disclosing the upper termination region comprises a plurality of segmentation area; and each of the P body regions includes a P+ region. However, TAMAKI teaches a semiconductor device including: a termination region (4b) comprises an upper termination region (8) that extends in the first direction while having the P-type of conductivity, a middle termination region having the N-type of conductivity and formed below the upper termination region (8), and a lower termination region formed below the middle termination region and including a plurality of third P-pillars (6b) and third N-pillars (1e) formed between the plurality of third P-pillars (6b), wherein the upper termination region (8) comprises a plurality of segmentation areas disposed within the upper termination region (8), the plurality of segmentation areas having a first segmentation area (8a), at least one intermediate segmentation are (8b), and a last segmentation area (8c) along the first direction, wherein the plurality of segmentation areas (8a-c) are disposed in the upper termination region (8) above the middle termination region, and wherein an impurity concentration of the first segmentation area (8a) is the highest, an impurity concentration of each of the at least one intermediate segmentation area (8b) is lower than that of the first segmentation area (8a), and an impurity concentration of the last segmentation area (8c) is the lowest, and wherein active region further comprises P body regions (7) and surface N regions (1e) alternately arranged in the active region, each of the P body regions (7) includes a P+ region (15) and an N+ region (21), and an outermost one of the surface N regions (1e) is disposed between the N+ region (21) and the upper frame region (8) along the first direction. (See FIG. 22). Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the upper termination region of SAITO comprising the plurality of segmentation area as taught by TAMAKI to prevent a variation in breakdown voltage caused by charge imbalance, and the P+ region to reduce contact resistance. With respect to claim 2, the entire lower termination region of SAITO is covered by the upper termination region (17). With respect to claim 3, the middle termination region and the upper termination region (17) of SAITO are sequentially formed on the third P-pillar (34). With respect to claim 4, the second P-pillar (34) of SAITO is connected to the top surface of the second semiconductor layer (12) through the upper frame region (5). With respect to claim 5, the third P-pillar (34) of SAITO is distanced from the top surface of the second semiconductor layer (12). With respect to claim 6, the top surface of the middle termination region of SAITO is distanced from the top surface of the second semiconductor layer (12). With respect to claim 7, the middle termination region of SAITO is connected with at least one of the plurality of third N-pillars (33) of the lower termination region. With respect to claim 8, the upper termination region (17) of SAITO is connected with the upper frame region (5). With respect to claim 9, the upper frame region (5) of SAITO is connected with at least one of the plurality of second P-pillars (34) of the lower frame region. With respect to claim 10, impurity concentration of the upper frame region (5) of SAITO is higher than that of the upper termination region (17). Response to Arguments Applicant’s arguments with respect to amended claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue A Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANH D MAI/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Jul 20, 2023
Application Filed
Sep 23, 2025
Non-Final Rejection mailed — §103
Dec 23, 2025
Response Filed
Jan 13, 2026
Final Rejection mailed — §103
Jul 13, 2026
Request for Continued Examination
Jul 17, 2026
Response after Non-Final Action
Aug 20, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
38%
Grant Probability
47%
With Interview (+9.6%)
3y 8m (~5m remaining)
Median Time to Grant
High
PTA Risk
Based on 709 resolved cases by this examiner. Grant probability derived from career allowance rate.

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