DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s amendment dated 02/11/2026 has been received and entered. By the amendment, claims 1-9 and newly added claims 10-14 are now pending in the application.
In view of the Applicant’s amendment to claims 7 and 9, the objection to the drawing and the 112 rejection are withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-5, 7 and 9-15 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Kikuchi et al., US 2020/0388637 A1.
Claim 1 is anticipated by Kikuchi et al. figures 1, 2A-2B and accompanying text which discloses a display device comprising:
. a transistor 20 comprising a semiconductor layer 7, a gate insulating layer 9, a gate electrode GE, a first conductive layer M1 and a second conductive layer PE
. a liquid crystal element comprising the second conductive layer PE, a third conductive layer CE and a liquid crystal (inherently forming in a liquid crystal display LCD panel)
. a first insulating layer 5 comprising a first side surface (lower side surface), wherein the first side surface is positioned over the first conductive layer M1, wherein the semiconductor layer 5 is in contact with a top surface (top side surface) of the first conductive layer M1 and the first side surface, wherein the gate insulating layer comprises a portion facing the first side surface with the semiconductor layer positioned between the gate insulating layer and the first side surface (fig. 2B)
. wherein the gate electrode GE comprises a portion facing the first side surface with the semiconductor layer 7 and the gate insulating layer 9 positioned between the gate electrode GE and the first side surface (fig. 2B)
. wherein the second conductive layer PE is positioned over the first insulating layer 5 and in contact with the semiconductor layer 7 (fig. 2B)
. wherein the third conductive layer CE is positioned over the first insulating layer 5 and comprises a portion overlapping with the second conductive layer PE in a plan view (fig. 2B)
. wherein the semiconductor layer 7 comprises an oxide semiconductor film ([0010])
. wherein the second conductive layer CE comprises an oxide conductive film ([0223]).
Re claim 2, Kikuchi et al. further disclose the first insulating layer comprising an opening (where the semiconductor 7 contact to the first conductive layer M1) and a first side surface positioned in the opening (fig. 2B).
Re claim 3, wherein the third conductive layer PE is positioned over the second conductive layer CE and comprises an oxide conductive film ([0223]), and wherein the gate insulating layer 9 comprises a portion positioned between the third conductive layer PE and the second conductive layer CE.
Re claim 4, wherein the third conductive layer PE is provided in contact with a top surface of the gate insulating layer (fig. 2B).
Re claim 5, Kikuchi et al. further disclose a second insulating layer 17 over the gate electrode GE, wherein the third conductive layer PE comprises a portion overlapping with the second conductive layer CE with the gate insulating layer, and the second insulating layer 17 positioned between the third conductive layer PE and the second conductive layer CE (fig. 2B).
Re claim 7, Kikuchi et al. further disclose a second insulating layer 17 over the third conductive layer CE, wherein the second conductive layer PE comprises a portion overlapping with the third conductive layer CE with the second insulating layer 17 positioned between the second conductive layer PE and the third conductive layer CE (fig 2B).
Re claim 9, wherein a second insulating layer 17 over the third conductive layer CE, wherein the second conductive layer PE comprises a portion overlapping with the third conductive layer CE with the second insulating layer 17 positioned between the second conductive layer and the third conductive layer (fig 2B).
Re claims 10 and 11, wherein the gate electrode GE comprises a portion overlapping with the first conductive layer M1 with the semiconductor layer 7 and the gate insulating layer 9 positioned between the gate electrode GE and the first conductive layer M1.
Re claims 12 and 13, wherein the gate electrode GE comprises a portion overlapping with the second conductive layer PE with the semiconductor layer 7 and the gate insulating layer 9 positioned between the gate electrode GE and the first conductive layer M1.
Re claims 14 and 15, wherein a second insulating layer 17 over the gate electrode GE, wherein the second insulating layer 17 is configured to function as a spacer (e.g., spacer between PE and CE).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Kikuchi et al., US 2020/0388637 A1.
Re claim 6, Kikuchi et al. disclose the claimed invention as described above except for the third conductive layer comprising a portion overlapping with the gate electrode. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ a third conductive layer having a portion overlapping a gate electrode, since it has been held that rearranging parts of an invention involves only routine skill in the display art. In re Japikse, 86 USPQ 70.
Re claim 8, Kikuchi et al. disclose the claimed invention as described above except for the gate insulating layer comprises a portion positioned between the third conductive layer and the second conductive layer. It would have been an obvious matter of design choice to employ a gate insulating layer having a portion positioned between pixel and common conductive layer, since the such insulating layer appears to perform equally well with any interlayer insulating layer between pixel and common electrodes for insulated purposes.
Response to Arguments
Applicant's arguments filed 02/11/2026 have been fully considered but they are not persuasive.
Applicant’s only argument is that Kikuchi et al. fail to teach a first insulating layer having a first side surface that meets all claim limitations. The Examiner respectfully disagrees with Applicant’s viewpoint. Particularly, Kikuchi et al. do disclose that the semiconductor layer 7 contacts a top surface of first conductive layer M1 (portion corresponding to SE/SL) and a first side surface (e.g. low/bottom surface) of layer 5, as required by claims 1 and 2. However, FIG. 2B fails to teach or suggest that the alleged gate insulating layer 9 comprises a portion facing the alleged first side surface of layer 5. Instead, the gate insulating layer 9 appears to only include a portion facing a top surface (of the first insulating layer 5)(see reproduce Kikuchi et al. figure 2B below, e.g., red line or dark line in black and white copy) with the semiconductor layer 7 positioned between the gate insulating layer 9 and the top surface as well as the gate electrode GE includes a portion facing the first side surface of layer 5 as shown in fig.2B as claimed.
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Accordingly, the rejection as stated above stand.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUNG T NGUYEN whose telephone number is (571)272-2297. The examiner can normally be reached 8:00 - 5:00.
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/DUNG T NGUYEN/Primary Examiner, Art Unit 2871
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