DETAILED ACTION
This action is responsive to communications dated 12/17/2025.
In the response filed, applicant amended claims 1, 8, and 15. Claims 2-5, 9-12, 16-18 were cancelled; no new claims added. Claims 1, 6-8, 13-15, and 19-20 are pending. Claims 1, 8, and 15 are independent.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/17/2025 has been entered.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) MPEP 2163 guidelines teach that drawing and specification must be examined to assess whether an originally-filed claim has adequate support in the written disclosure and/or the drawings. Possession may be shown by a clear depiction of the invention in detailed drawings. C) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Domestic Priority
4. See ADS for domestic priority details.
5. Applicant is requested to check other claim informality, language issues (e.g., antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 112
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
7. Claims 1, 6-8, 13-15, 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
MPEP 2173.02(II) instructs examiners that definiteness of claim language is determined, not in a vacuum, but in light of: (A) the content of the originally filed disclosure; (B) the prior art; and (C) the perspective of one having ordinary skill in the art. Further, the Federal Circuit explained that for definiteness requirement rejections, the USPTO initially issues a well-grounded rejection by "identifying ways in which language in a claim is ambiguous, vague, incoherent, opaque, or otherwise unclear in describing and defining the claimed invention." see In re Packard,751 F.3d 1307, 1311 (Fed. Cir. 2014). Also, Zletz, 893 F.2d at 322, 13 USPQ2d at 1322. For example, if the language of a claim, given its broadest reasonable interpretation, is such that a person of ordinary skill in the relevant art would read it with more than one reasonable interpretation, then a rejection under 35 U.S.C. 112(b) is appropriate.
Recited “…wherein, while concurrently applying the memory operation to the multiple memory planes, a starting time of the application of the memory operation with respect to one memory plane differs from a starting time of the application of the memory operation to another memory plane.…" in claim 1 (last 4 lines), claim 8 (last 4 lines) and claim 15 (last 4 lines) is undefined, vague and ambiguous in its use.
Applicant's disclosure only provides broad description for claim language to describe the limitation in Fig. 27, para [00129]- para [00131]. The limitation/ clause is unclear, vague and subject to multiple interpretation due to language:
It is not clear how two cited limitations are different “…concurrently applying the memory operation to the multiple memory planes, a starting time of the application of the memory operation …memory plane differs from a starting time of the application of the memory operation to another memory plane.…" since the limitations are tied to program application and claim does not clearly mention additional mechanism, steps placed in the method. The claim language appears to have contradicting limitations.
Fig. 27, para [00129]- para [00131] disclosure in view of language in claim itself can give rise to multiple interpretations and ambiguity: Some of the interpretations are as follows:
Applied Vpgm, Vpass application to the wordlines of blocks, planes are applied at the same time concurrently or, at different times (with timing difference).
Applied power supply (power up of planes) application to the planes (and blocks) are applied at the same time concurrently or, at different times (with timing difference).
Applied data loading or command/ address application, bit line bias to the planes (and blocks) are applied at the same time concurrently or, at different times (with timing difference).
Combination of the above
The claim language also does not further describe characteristics of this function/ limitation for a clear interpretation. In other words, the claims have unlimited scope on this limitation/ language leading to confusion, or zone of uncertainty. Thus, the claims are indefinite.
All dependent claims inclusive of Claims 1, 6-8, 13-15, 19-20 are rejected under this category.
For purposes of compact prosecution (see MPEP 2173.06), the clause is interpreted as concurrently powering up, applying multi-plane command; but VPGM application to plains are done at different times.
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
11. Claims 1, 7-8, 14-15, and 20 is/are rejected under 35 U.S.C. 103 as being obvious over Chin et al. (US 2019/0348127 A1), in view of KIM (US 2009/0196102 A1).
Regarding independent claim 1, Chin teaches a method for performing a multi-plane memory operation with respect to a multi-plane memory structure, wherein the multi-plane memory operation includes programming multiple memory planes in a same programming operation, (e.g., method for programming operation or reading operation for Fig. 9 memory system. See Fig. 14-Fig. 15. See also Fig. 1, Fig. 10-Fig. 15. Para [0103], Fig. 14: 702 “…simultaneously program memory cells connected to different word lines that are in different sub-blocks of different blocks in different planes of a die…”), the method comprising:
initiating a memory operation with respect to a memory system (initial program selection stage of Fig. 14, Fig. 15), wherein:
the memory system comprises a non-volatile memory structure (Fig. 9: 582) having a plurality of memory planes (Fig. 9: Plane A, Plane B. See para [0100]), with each memory plane comprising: (1) a plurality of memory blocks (Fig. 9: SB0, SB1 each taken as a block. See para [0100], Fig. 9: SB0, SB1 multiplied by number of “many blocks”), and (2) a plurality of word lines arranged in a serial order; (para [0100], Fig. 8: WL’s with SB0, WL’s with SB1 multiplied by number of “many blocks”),
and
electrically connected with each memory plane are: (1) a voltage bias source (Fig. 10: 602 voltage generator, see para [0105]), (2) at least one electronic switching component (Fig. 10: 604, 606 switch network, see para [0105]), and (3) at least one row decoder (row decoder and associated circuitry, see e.g., para [0042]);
with respect to each memory plane, selecting a respective memory block (Fig. 9: SB0/Block X, and SB1/Block Y) and a respective word line (Fig. 9: WL58/ SB0/Block X, and WL69/SB1/Block Y) for application of the memory operation (e.g., program selection step),
wherein: the memory operation has not yet been applied to the selected memory block and the selected word line (e.g., program address selection step);
the selected memory block (Fig. 9: SB0/Block X) of one memory plane (Fig. 9: Plane A) can be located in a different memory block group (Fig. 9: SB groups across planes along row direction which are located and distanced in y-direction) from the selected memory block of another memory plane (Fig. 9: SB1/Block Y); and
the selected word line of one memory plane can be in a different position within the serial order from a position of the selected word line of another memory plane (See Fig. 9: WL58 selected for SB0/Block X and WL69 selected for SB1/Block Y); and
using the voltage bias source, concurrently applying the memory operation to the respective selected memory blocks and to the respective selected word lines (Fig. 14, Fig. 15 in context of para [0111]. See also para [0109]),
wherein the voltage bias source comprises multiple voltage bias sources, wherein each voltage bias source is associated with a specific one of the memory planes (Fig. 10: 602 voltage generator and para [0105]: vpgm. Fig. 11 embodiment in context of para [0104]: Block X/ associated plane and Block Y/ associated plane have its own voltage generator).
Chin is implicit and silent with respect to remaining provisions of this claim regarding the details of the voltage application timing.
KIM teaches -
wherein, while concurrently applying the memory operation to the multiple memory planes (para [0163]: for planes 2, 4 “multi-plane program…operations…” and “multi-plane” command/ address application, powering up planes 2, 4 and data loading in page buffers of planes 2, 4), a starting time of the application of the memory operation with respect to one memory plane differs from a starting time of the application of the memory operation to another memory plane (para [0163], Fig. 24: planes 2, 4 program operation timing tPROG difference).
Chin and KIM are in the same field of endeavor of read/ write management scheme of memory planes (KIM Fig. 2B, Fig. C, Fig. 5 disclosure) and they are in analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine KIM’s circuitry and functionality into the method of Chin such that claimed function can be implemented in order to have high degree of flexibility in multi-plane operations and have benefits dynamic page configuration for faster operation and power saving (KIM Abstract).
Regarding claim 7, Chin and KIM teach the method according to claim 1. Chin teaches wherein a memory block group comprises all memory blocks located within a same memory array row. (See claim 20 rejection analysis since claims are substantially identical)
Regarding independent claim 8, Chin teaches a memory controller configured to perform a multi-plane memory operation in which multiple memory planes are programmed in a same programming operation (para [0018], Fig. 9 memory system. See also Fig. 1, Fig. 10-Fig. 15. Para [0103], Fig. 14: 702 “…simultaneously program memory cells connected to different word lines that are in different sub-blocks of different blocks in different planes of a die…”. See also Fig. 1: 120, see also Fig. 9: 580 control circuit), comprising:
a communication pathway configured to couple to a memory system (Fig. 1: buses coupled to controller, memory. See also Fig. 9), wherein:
the memory system comprises a non-volatile memory structure (Fig. 9: 582) having a plurality of memory planes (Fig. 9: Plane A, Plane B), with each memory plane comprising: (1) a plurality of memory blocks (Fig. 9: SB0, SB1 each taken as a block. See para [0100], Fig. 9: SB0, SB1 multiplied by number of “many blocks”), and (2) a plurality of word lines arranged in a serial order, (para [0100], Fig. 8: WL’s with SB0, WL’s with SB1 multiplied by number of “many blocks”), and
electrically connected with each memory plane are: (1) a voltage bias source (Fig. 10: 602 voltage generator, see para [0105]); (2) at least one electronic switching component (Fig. 10: 604, 606 switch network, see para [0105]), and (3) at least one row decoder (row decoder and associated circuitry, see e.g., para [0042]);
the memory controller is configured to:
initiate a memory operation with respect to the memory system (Fig. 14, Fig. 15 program operation);
with respect to each memory plane, select a respective memory block (Fig. 9: SB0/Block X, and SB1/Block Y) and a respective word line (Fig. 9: WL58/ SB0/Block X, and WL69/SB1/Block Y) for application of the memory operation (program selection),
wherein: the memory operation has not yet been applied to the selected memory block and the selected word line (program address selection step);
the selected memory block (Fig. 9: SB0/Block X) of one memory plane (Fig. 9: Plane A) can be located in a different memory block group (Fig. 9: SB groups across planes along row direction which are located and distanced in y-direction) from the selected memory block of another memory plane (Fig. 9: SB1/Block Y); and
the selected word line of one memory plane can be in a different position within the serial order from a position of the selected word line of another memory plane (See Fig. 9: WL58 selected for SB0/Block X and WL69 selected for SB1/Block Y); and
using the voltage bias source, concurrently apply the memory operation to the respective selected memory blocks and to the respective selected word lines (Fig. 14, Fig. 15 in context of para [0111]. See also para [0109]),
wherein the voltage bias source comprises multiple voltage bias sources, wherein each voltage bias source is associated with a specific one of the memory planes (Fig. 10: 602 voltage generator and para [0105]: vpgm. Fig. 11 embodiment in context of para [0104]: Block X/ associated plane and Block Y/ associated plane have its own voltage generator).
Chin is implicit and silent with respect to remaining provisions of this claim regarding the details of the voltage application timing.
KIM teaches -
wherein, while concurrently applying the memory operation to the multiple memory planes (para [0163]: for planes 2, 4 “multi-plane program…operations…” and “multi-plane” command/ address application, powering up planes 2, 4 and data loading in page buffers of planes 2, 4), a starting time of the application of the memory operation with respect to one memory plane differs from a starting time of the application of the memory operation to another memory plane (para [0163], Fig. 24: planes 2, 4 program operation timing tPROG difference).
Chin and KIM are in the same field of endeavor of read/ write management scheme of memory planes (KIM Fig. 2B, Fig. C, Fig. 5 disclosure) and they are in analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine KIM’s circuitry and functionality into the method of Chin such that claimed function can be implemented in order to have high degree of flexibility in multi-plane operations and have benefits dynamic page configuration for faster operation and power saving (KIM Abstract).
Regarding claim 14, Chin and KIM teach the memory controller according to claim 8. Chin teaches wherein a memory block group comprises all memory blocks located within a same memory array row. (See claim 17 rejection analysis since claims are substantially identical)
Regarding independent claim 15, Chin teaches a non-volatile memory system
configured to perform a multi-plane memory operation in which multiple memory planes are programmed in a same programming operation, comprising: (para [0018], Fig. 9 memory system. See also Fig. 1, Fig. 10-Fig. 15. Para [0103], Fig. 14: 702 “…simultaneously program memory cells connected to different word lines that are in different sub-blocks of different blocks in different planes of a die…”), comprising:
a memory structure (Fig. 9: 582) having a plurality of memory planes (Fig. 9: Plane A, Plane B), with each memory plane comprising: (1) a plurality of memory blocks (Fig. 9: SB0, SB1 each taken as a block. See para [0100], Fig. 9: SB0, SB1 multiplied by number of “many blocks”), and (2) a plurality of word lines arranged in a serial order (para [0100], Fig. 8: WL’s with SB0, WL’s with SB1 multiplied by number of “many blocks”),
electrically connected with each memory plane: (1) a voltage bias source (Fig. 10: 602 voltage generator, see para [0105]); (2) at least one electronic switching component (Fig. 10: 604, 606 switch network, see para [0105]), and (3) at least one row decoder (row decoder and associated circuitry, see e.g., para [0042]);
a memory controller (Fig. 9: 580 control circuit) coupled to the memory structure (Fig. 9: 582) and:
initiating a memory operation with respect to the memory system (Fig. 14, Fig. 15 program operation initial selection step);
with respect to each memory plane, selecting a respective memory block (Fig. 9: SB0/Block X, and SB1/Block Y) and a respective word line (Fig. 9: WL58/ SB0/Block X, and WL69/SB1/Block Y) for application of the memory operation (program selection), wherein:
the memory operation has not yet been applied to the selected memory block and the selected word line (program address selection step);
the selected memory block (Fig. 9: SB0/Block X) of one memory plane (Fig. 9: Plane A) can be located in a different memory block group (Fig. 9: SB groups across planes along row direction which are located and distanced in y-direction) from the selected memory block of another memory plane (Fig. 9: SB1/Block Y); and
the selected word line of one memory plane can be in a different position within the serial order from a position of the selected word line of another memory plane (See Fig. 9: WL58 selected for SB0/Block X and WL69 selected for SB1/Block Y); and
using the voltage bias source, concurrently applying the memory operation to the respective selected memory blocks and to the respective selected word lines (Fig. 14, Fig. 15 in context of para [0111]. See also para [0109]).
wherein the voltage bias source comprises multiple voltage bias sources, wherein each voltage bias source is associated with a specific one of the memory planes (Fig. 10: 602 voltage generator and para [0105]: vpgm. Fig. 11 embodiment in context of para [0104]: Block X/ associated plane and Block Y/ associated plane have its own voltage generator).
Chin is implicit and silent with respect to remaining provisions of this claim regarding the details of the voltage application timing.
KIM teaches -
wherein, while concurrently applying the memory operation to the multiple memory planes (para [0163]: for planes 2, 4 “multi-plane program…operations…” and “multi-plane” command/ address application, powering up planes 2, 4 and data loading in page buffers of planes 2, 4), a starting time of the application of the memory operation with respect to one memory plane differs from a starting time of the application of the memory operation to another memory plane (para [0163], Fig. 24: planes 2, 4 program operation timing tPROG difference).
Chin and KIM are in the same field of endeavor of read/ write management scheme of memory planes (KIM Fig. 2B, Fig. C, Fig. 5 disclosure) and they are in analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine KIM’s circuitry and functionality into the method of Chin such that claimed function can be implemented in order to have high degree of flexibility in multi-plane operations and have benefits dynamic page configuration for faster operation and power saving (KIM Abstract).
Regarding claim 20, Chin and KIM teach the non-volatile memory system according to claim 15. Chin teaches wherein a memory block group (Fig. 9: SB groups across planes along row direction which are located and distanced in y-direction) comprises all memory blocks (e.g., Fig. 9: SB0) located within a same memory array row (see Fig. 9).
12. Claims 6, 13, and 19 is/are rejected under 35 U.S.C. 103 as being obvious over Chin et al. (US 2019/0348127 A1) and KIM (US 2009/0196102 A1), in view of Shah et al. (US 9,792,995 B1).
Regarding claim 6, Chin, KIM and Shah teach the method according to claim 1, wherein the memory structure comprises a plurality of NAND-type memory cells, and: at least one of the memory blocks comprises a population of SLC-type memory cells; and at least one of the other memory blocks comprises a population of memory cells having a higher storage density than an SLC-type memory cell. (See claim 19 rejection analysis since claims are substantially identical)
Regarding claim 13, Chin, KIM and Shah teach the memory controller according to claim 8, wherein the memory structure comprises a plurality of NAND-type memory cells, and: at least one of the memory blocks comprises a population of SLC-type memory cells; and at least one of the other memory blocks comprises a population of memory cells having a higher storage density than an SLC-type memory cell. (See claim 19 rejection analysis since claims are substantially identical)
Regarding claim 19, Chin and KIM teach the non-volatile memory system according to claim 15, wherein the memory structure comprises a plurality of NAND-type memory cells (see e.g., Chin para [0048], Fig. 4F).
They are silent with respect to remaining provisions of this claim pertaining to storage density and cell type/
Shah teaches -
at least one of the memory blocks comprises a population of SLC-type memory cells; and at least one of the other memory blocks comprises a population of memory cells having a higher storage density than an SLC-type memory cell (col. 19, lines 62-67, and col. 20, lines 1-8 “…in a hybrid read mode in which SLC cells are read in one plane while multi-level cells are read in another plane…”. See Fig. 1B circuitry).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Shah’s circuitry and functionality into the apparatus of Chin and KIM such that claimed function can be implemented in order to have benefits “…reduces the worst case SLC read latency to one-third of its previous value while reducing the negative impact of hybrid SLC read mode on bit error rate and endurance…” (Shah col. 20, lines 5-8).
Response to Arguments
Applicant’s arguments 12/17/2025 with respect to claim(s) 1, 8, and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. See new rejection using KIM reference.
Applicant has not argued substantively against dependent claim specific limitation (or any other claim limitations) and previous rejections are being relied upon.
Previous 112b rejections are withdrawn based on new amendment. See new 112b rejections.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
Yang (US 2022032556 A1): Fig. 1-Fig. 12 applicable for all claims.
Park (US 2009/0244983 A1): Fig. 1-Fig. 20 applicable for all claims.
See also SANAD (US 2020/0194077 A1), Zhang (US 2023/0023618 A1).
It is suggested that applicant consider all prior arts made of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander George Sofocleous can be reached on (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825