DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Group -I (claim#1-14) in the reply filed on 11/24/2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 8-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Niimi; Hiroaki (US Pub: 2022/0109066 A1), herein after Niimi.
Regarding claim 1, Niimi teaches a multi-silicide semiconductor structure, in FIG. 1A-1Z, wherein the multi-silicide semiconductor structure comprises:
an NFET (101,);
a PFET (103);
an NFET silicide proximately connected to the NFET, wherein the NFET silicide is a first material (Paragraph [0006], [0017], a titanium silicide wrapped around the first n-type doped epitaxial semiconductor material); and
a PFET silicide proximately connected to the PFET, wherein the PFET silicide is a second material different than the first material (Paragraph[0006], [0020], [0021], Claim 17. A ruthenium silicide wrapped around the second p-type doped epitaxial semiconductor material.).
Regarding claim 2, Niimi teaches the multi-silicide semiconductor structure of claim 1, wherein the second material is Ru- silicide (Paragraph [0020], [0021], Claim 17).
Regarding claim 3, Niimi teaches the multi-silicide semiconductor structure of claim 1, wherein the first material is Ti-silicide (Paragraph [0006], [0017], Claim 17).
Regarding claim 4, Niimi teaches the multi-silicide semiconductor structure of claim 1, further comprising: a silicide contact for the PFET (Paragraph [0017]; and low-k dielectric sidewalls (118, low-k dielectric gate spacer layer) surrounding the silicide contact.
Regarding claim 5, Niimi teaches the multi-silicide semiconductor structure of claim 1, wherein the second material has a lower Schottky barrier height than the first material (Paragraph[0017], [0020], [0021], Claim 17. First material and second material are same. So, it is inherent that their properties will be same.).
Regarding claim 6, Niimi teaches the multi-silicide semiconductor structure of claim 1, wherein the NFET and the PFET are stacked transistors (Paragraph [0013], [0014], 0018], [0023].
Regarding claim 8, Niimi teaches the multi-silicide semiconductor structure of claim 1, further comprising a metal contact proximately connected to the NFET silicide (Paragraph [0023], Claim 9 and 10).
Regarding claim 9, Niimi teaches A system, wherein the system, , in FIG. 1A-1Z, comprises: a multi-silicide semiconductor structure, wherein the multi-silicide semiconductor structure comprises:
an NFET (101,);
a PFET (103);
an NFET silicide proximately connected to the NFET, wherein the NFET silicide is a first material (Paragraph [0006], [0017], a titanium silicide wrapped around the first n-type doped epitaxial semiconductor material);
a PFET silicide proximately connected to the PFET, wherein the PFET silicide is a second material different than the first material (Paragraph[0006], [0020], [0021], Claim 17. A ruthenium silicide wrapped around the second p-type doped epitaxial semiconductor material.); and
a silicide contact for the PFET (Paragraph [0023], Claims 9 and 10).
Regarding claim 10, Niimi teaches the system of claim 9, wherein the second material is Ru-silicide (Paragraph [0020], [0021], Claim 17).
Regarding claim 11, Niimi teaches the system of claim 9, wherein the first material is Ti-silicide (Paragraph [0006], [0017], Claim 17).
Regarding claim 12, Niimi teaches the system of claim 9, further comprising: low-k dielectric sidewalls surrounding the silicide contact (118, low-k dielectric gate spacer layer, Paragraph [0017]).
Regarding claim 13, Niimi teaches the system of claim 9, wherein the second material has a lower Schottky barrier height than the first material (Paragraph[0017], [0020], [0021], Claim 17. First material and second material are same. So, it is inherent that their properties will be same.).
Regarding claim 14, Niimi teaches the system of claim 9, further comprising a metal contact proximately connected to the NFET silicide (Paragraph [0023], Claim 9 and 10).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is are rejected under 35 U.S.C. 103 as being unpatentable over Niimi, in view of known arts like Niimi or Xi et al. (US Patent: 10236218 B1)
Regarding claim 7, Niimi does not explicitly teaches the multi-silicide semiconductor structure of claim 1, wherein the NFET and the PFET are nanosheet FETs.
However, this is known to the people skilled in the art to nanosheet or nanowire as hinted in Niimi in Paragraph [0003] and many others like Xie et al. (US Patent: 10236218 B1) in Column 5 line 1-48).
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Niimi’s multi-silicide semiconductor structure with nanosheet material teaching from known art in order to improved Source and drain contact resistivity and thereby improve performance of scaled FinFETs.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached on M-F, 8am-6pm EDT.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897
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