Prosecution Insights
Last updated: April 19, 2026
Application No. 18/224,734

DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME

Non-Final OA §102
Filed
Jul 21, 2023
Examiner
SENGDARA, VONGSAVANH
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
71%
Grant Probability
Favorable
1-2
OA Rounds
3y 5m
To Grant
90%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allow Rate
651 granted / 914 resolved
+3.2% vs TC avg
Strong +19% interview lift
Without
With
+19.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
73 currently pending
Career history
987
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
48.7%
+8.7% vs TC avg
§102
30.5%
-9.5% vs TC avg
§112
17.5%
-22.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 914 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species 1 FIG. 4 (Claims 1-14) in the reply filed on 11/21/2025 is acknowledged. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1- 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jang et al. 20210202675. PNG media_image1.png 431 489 media_image1.png Greyscale PNG media_image2.png 497 574 media_image2.png Greyscale Regarding claim 1, fig. 8 of Jang discloses a display device comprising: a substrate 10 comprising: a display area AA in which a plurality of emission areas displays an image (par [0138], [0345]); and a non-display area IA disposed around the display area; a light-emitting array layer 13 disposed in the display area on the substrate; an encapsulation structure 16 disposed on the substrate and covering the light-emitting array layer; PNG media_image3.png 393 497 media_image3.png Greyscale pads CVP (par [0072]) disposed in a pad area (area of CVP) which is a part of the non-display area on the substrate; a dam structure 15 disposed in the non-display area on the substrate and surrounding an edge of the display area; PNG media_image4.png 581 663 media_image4.png Greyscale an encapsulation auxiliary structure (structure combination of CE/ED/ES) corresponding to another part of the non-display area except the pad area, surrounding a part of the edge of the display area, and disposed between the dam structure and an edge of the substrate; and a first multilayer (CLL/CML) disposed between the substrate 10 and each of the dam structure 15 and the encapsulation auxiliary structure (CE/ED/ES), and comprising an undercut structure (see undercut of CLL) by two or more different metal materials (CML – par [0182] The conductive metal line CML, and CLL – see par [0146] - CLL can be formed of the same material along with the pixel electrode PE) which are stacked. Regarding claim 2, Jang discloses wherein the first multilayer comprises a first main layer CML, and a first cover layer CLL disposed on the first main layer, wherein the first main layer and the first cover layer comprise different metal materials (CML – par [0182] The conductive metal line CML, and CLL – see par [0146] - CLL can be formed of the same material along with the pixel electrode PE) from each other, and the undercut structure of the first multilayer is provided by the first cover layer including an edge protruding beyond the first main layer. Regarding claim 3, fig. 4 of Jang discloses wherein the encapsulation structure comprises: a first encapsulation layer 16a corresponding to an area of the substrate except the pad area, covering the light-emitting array layer, and comprising an inorganic insulating material; a second encapsulation layer 16b disposed on the first encapsulation layer, comprising an organic insulating material, and corresponding to a region surrounded by the dam structure; and a third encapsulation layer 16c disposed on the first encapsulation layer, covering the second encapsulation layer, and comprising the inorganic insulating material, wherein the first encapsulation layer contacts the first main layer of the first multilayer, and the first encapsulation layer and the third encapsulation layer contact each other in an area between the dam structure and the edge of the substrate in the non-display area. Allowable Subject Matter Claims 4-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 4 recites “a second multilayer disposed on the bank buffer layer, and comprising an undercut structure by two or more different metal materials which are stacked; a pixel defining layer disposed on the second multilayer; a first common layer disposed on the plurality of anode electrodes and the pixel defining layer; a plurality of light-emitting layers respectively corresponding to the plurality of emission areas and disposed on the first common layer; a second common layer disposed on the first common layer and covering the plurality of light-emitting layers; and a cathode electrode disposed on the second common layer and corresponding to the plurality of emission areas, wherein the first common layer, the second common layer, and the cathode electrode correspond to an area of the substrate except the pad area” is not taught by the reference of record. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, PURVIS A. Sue can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893
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Prosecution Timeline

Jul 21, 2023
Application Filed
Feb 21, 2026
Non-Final Rejection — §102
Apr 10, 2026
Interview Requested

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604622
DISPLAY SUBSTRATE AND DISPLAY DEVICE
2y 5m to grant Granted Apr 14, 2026
Patent 12598804
INTEGRATED CIRCUIT DEVICE
2y 5m to grant Granted Apr 07, 2026
Patent 12598779
Gate-All-Around Device with Protective Dielectric Layer and Method of Forming the Same
2y 5m to grant Granted Apr 07, 2026
Patent 12588424
NONVOLATILE MEMORY ELEMENT AND METHOD FOR MANUFACTURING THE SAME
2y 5m to grant Granted Mar 24, 2026
Patent 12581835
DISPLAY PANEL
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
71%
Grant Probability
90%
With Interview (+19.1%)
3y 5m
Median Time to Grant
Low
PTA Risk
Based on 914 resolved cases by this examiner. Grant probability derived from career allow rate.

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