DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to claims filed on 04/21/2026.
Claims 1-20 are pending.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention recites a judicial exception, is directed to that judicial exception, an abstract idea, as it has not been integrated into practical application and the claims further do not recite significantly more than the judicial exception. Examiner has evaluated the claims under the framework provided in the 2019 Patent Eligibility Guidance published in the Federal Register 01/07/2019 and has provided such analysis below.
Step 1: Claims 1-7 are directed to a processor and fall within the statutory category of machines. Claims 8-14 are directed to a system and fall within the statutory category of machines. Claims 15-20 are directed to a method and fall within the statutory category of processes. Therefore, “Are the claims to a process, machine, manufacture or composition of matter?” Yes.
In order to evaluate the Step 2A inquiry “Is the claim directed to a law of nature, a natural phenomenon or an abstract idea?” we must determine, at Step 2A Prong 1, whether the claim recites a law of nature, a natural phenomenon or an abstract idea and further whether the claim recites additional elements that integrate the judicial exception into a practical application.
Step 2A Prong 1:
Claims 1, 8, and 15: The limitations of “wherein to schedule the one or more instructions the one or more circuits are to: determine respective node labels assigned to one or more nodes of the plurality of nodes, each respective node label indicating a number of processors to be used for instructions scheduled to the node to which the label is assigned;”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can mentally determine respective node labels indicating a number of processors to be used for instructions scheduled for one or more nodes and can mentally assign these labels to the nodes. This may also be done with pencil and paper. Further, the limitations of “and select the two or more processors based, at least in part, on the respective node labels and latency of one or more interconnects between the two or more processors”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can observe latency of one or more interconnects between two or more processors and respective node labels, and based on these observations, can mentally select two or more processors. This may also be done with pencil and paper.
Therefore, Yes, claims 1, 8, and 15 recite a judicial exception.
Step 2A Prong 2:
Claims 1, 8, and 15: The judicial exception is not integrated into a practical application. In particular, the claims recite additional element recitations of “one or more circuits to schedule one or more instructions to be performed by two or more processors of a node of a plurality of nodes each comprising a respective plurality of processors,” which are merely recitations of generic computing components being used as a tool to apply the abstract idea (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application.
Therefore, “Do the claims recite additional elements that integrate the judicial exception into a practical application? No, these additional elements do not integrate the abstract idea into a practical application and they do not impose any meaningful limits on practicing the abstract idea. The claims are directed to an abstract idea.
After having evaluated the inquires set forth in Steps 2A Prong 1 and 2, it has been concluded that claims 1, 8, and 15 not only recite a judicial exception but that the claims are directed to the judicial exception as the judicial exception has not been integrated into practical application.
Step 2B:
Claims 1, 8, and 15: The claims do not include additional elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements amount to no more than generic computing components which do not amount to significantly more than the abstract idea.
Therefore, “Do the claims recite additional elements that amount to significantly more than the judicial exception? No, these additional elements, alone or in combination, do not amount to significantly more than the judicial exception.
Having concluded analysis within the provided framework, Claims 1, 8, and 15 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claims 2, 9, and 16, the claims recite additional element idea recitations of “wherein another node label assigned to at least one or more nodes is indicative of a maximum number of processors to perform instructions at the at least one node” which are merely recitations of technological environment/field of use (see MPEP § 2106.05(h)) which does not integrate a judicial exception into practical application. Further, claims 2, 9, and 16 do not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 2, 9, and 16 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fail Step 2B as not amounting to significantly more. Therefore, Claims 2, 9, and 16 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claims 3, 10, and 17, the claims recite additional abstract idea recitations of “wherein the latency of the one or more interconnects is based, at least in part, on proximity of the two or more processors within a non-uniform memory access (NUMA) domain”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, person can observe the latency of one or more interconnects based in part on proximity of the one or more processors, and based on these observations, can mentally schedule one or more instructions to be performed by the one or more processors. This may also be done with pencil and paper. Further, claims 3, 10, and 17 do not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 3, 10, and 17 also fail both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fail Step 2B as not amounting to significantly more. Therefore, Claims 3, 10, and 17 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claims 4 and 18, the claims recite additional element recitations of “wherein the latency of the one or more interconnects between the two or more processors is based, at least in part, on proximity of one processor performing the one or more instructions to another processor performing the one or more instructions” which are merely recitations of technological environment/field of use (see MPEP § 2106.05(h)) which does not integrate a judicial exception into practical application. Further, claims 4 and 18 do not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 4 and 18 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fail Step 2B as not amounting to significantly more. Therefore, Claims 4 and 18 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 5, the claim recites additional abstract idea recitations of “wherein the one or more circuits are to schedule the one or more instructions based, at least in part, on a constraint on placement of instructions performed by certain numbers of processors” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can observe a constraint on placement of instructions performed by certain numbers of processors, and based on these observations, can mentally schedule one or more instructions. This may also be done with pencil and paper. Further, claim 5 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 5 also fails both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 5 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 6, the claim recites additional abstract idea recitations of “wherein the one or more circuits are to schedule the one or more instructions based, at least in part, on a dynamic labeling of plurality of nodes” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can observe a dynamic labeling of plurality of nodes, and based on these observations, can mentally schedule one or more instructions. This may also be done with pencil and paper. Further, claim 6 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 6 also fails both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 6 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claims 7 and 13, the claims recite additional abstract idea recitations of “wherein the one or more circuits are to schedule a subsequent one or more instructions based, at least in part, on a second latency that is equivalent to the latency between the two or more processors” and “wherein the one or more processors are to schedule a second one or more instructions to be performed by a second one or more processors based, at least in part, on an equivalent latency of the latency of one or more interconnects” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can observe a latency that is equivalent to the latency of one or more interconnects or two or more processors, and based on these observations, can mentally schedule a second or subsequent one or more instructions. This may also be done with pencil and paper. Further, claims 7 and 13 do not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 7 and 13 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fail Step 2B as not amounting to significantly more. Therefore, Claims 7 and 13 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 11, the claim recites additional abstract idea recitations of “wherein the latency of the one or more interconnects is based, at least in part, on a socket domain”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, person can observe the latency of one or more interconnects based in part on a socket domain, and based on these observations, can mentally schedule one or more instructions to be performed by the one or more processors. This may also be done with pencil and paper. Further, claim 11 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 11 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 11 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 12, the claim recites additional abstract idea recitations of “wherein a dynamic label of processors changes based, at least in part, on completion of all instructions being performed by a plurality of processors on a node” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can observe completion of all instructions being performed by a plurality of processors on a node, and based on these observations, can mentally change a dynamic label of processors. This may also be done with pencil and paper. Further, claim 12 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 12 also fails both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 12 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 14, the claim recites additional element recitations of “wherein a percentage of one or more nodes assigned the first and second node label is configurable”, which are merely recitations of technological environment/field of use (see MPEP § 2106.05(h)) which does not integrate a judicial exception into practical application. Further, claim 14 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 14 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 14 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 19, the claim recites additional element recitations of “further comprising: performing the one or more instructions based, at least in part, on the latency of one or more interconnects coupled to the one or more processors”, which is merely a recitation of generically using a computer as a tool to implement the abstract idea (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application. Further, claim 19 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 19 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 19 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 20, the claim recites additional abstract idea recitations of “further comprising: generating a fitness score of a node that includes the one or more processors, the fitness score indicating a different value than a number of processors performing the one or more instructions;” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can mentally generate a fitness score of a node such that the fitness score indicates a different value than a number of processors performing the one or more instructions. This may also be done with pencil and paper. Further, the claim recites additional abstract idea recitations of “and scheduling a second one or more instructions to be performed by a different number of the one or more processors than the number of processors performing the one or more instructions” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can mentally schedule a second one or more instructions to be performed by a different number of the one or more processors than the number of processors performing the one or more instructions. This may also be done with pencil and paper. Further, claim 20 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 20 also fails both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 20 does not recite patent eligible subject matter under 35 U.S.C. § 101.
Therefore, Claims 1-20 do not recite patent eligible subject matter under U.S.C. §101.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 7-8, 10-11, 13, 15, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Merrifield (US 2023/0012606 A1) in view of Jiang (US 2023/0401082 A1) in view of Konik (US 2014/0173614 A1).
With regard to claim 1, Merrifield teaches:
A processor comprising: one or more circuits to schedule one or more instructions to be performed by two or more processors of a node of a plurality of nodes each comprising a respective plurality of processors, “As shown in FIG. 1A, NUMA system 100 includes a hypervisor 102 and one or more VMs (nodes) 104 in software, as well as a physical NUMA topology 106 comprising M physical NUMA nodes 108 (identified via indices 0 to M-1) in hardware” [Merrifield ¶ 15]. “Each physical NUMA node 108 is a logical grouping of a compute resource 110 and a physical memory 112 of NUMA system 100 that exhibits the property of "non-uniform memory access," which means that the compute resource is able access the physical memory of its NUMA node (referred to as local memory) faster-or in other words, with lower latency than the physical memories of other NUMA nodes (referred to as remote memories)” [Merrifield ¶ 15]. “This virtual NUMA topology includes one or more virtual NUMA nodes, each comprising a virtual CPU and associated memory, which the hypervisor "places"----or in other words, schedules for execution-on physical NUMA nodes of the system” [Merrifield ¶21].
a number of processors to be used for instructions scheduled to the node to which the label is assigned; “In a NUMA system like system 100 of FIGS. 1A and 1B, the hypervisor can choose to expose a virtual NUMA topology to the guest OS of a VM based on various factors (e.g., the number of virtual central processing units (CPUs) provisioned for the VM, the amount of memory provisioned for the VM, etc.). This virtual NUMA topology includes one or more virtual NUMA nodes, each comprising a virtual CPU and associated memory, which the hypervisor "places"----or in other words, schedules for execution-on physical NUMA nodes of the system. For example, FIG. 3 depicts a scenario 300 in which VM 104(1) of FIG. 1A is presented a virtual NUMA topology 302 comprising three virtual NUMA nodes 0, 1, and 2 (each with two virtual CPUs), which hypervisor 102 has placed on physical NUMA nodes 0, 1, and 2 respectively” [Merrifield ¶ 21].
based, at least in part, on the respective node labels and latency of one or more interconnects between the two or more processors. “Large memory and compute systems are typically designed with multiple processor sockets, each directly attached to a pool of local memory and indirectly attached to the local memories of other processor sockets (i.e., remote memories) via an interconnect or bus. This architecture is known as a Non-Uniform Memory Access (NUMA) architecture because each processor socket can access data in its local memory faster (i.e., with lower latency) than data in remote memory. A grouping of a processor socket and its local memory is referred to as a NUMA node. Due to the higher costs of remote memory accesses, it is important for system software to be aware of the memory topology of a NUMA system and the memory access latencies between NUMA nodes. Among other things, this allows the system software to make more informed task placement/memory allocation decisions and thus improve system performance. The Advanced Configuration and Power Interface (ACPI) specification defines a System Locality Information Table (SLIT) that system firmware can use to provide node-to-node latency information to system software” [Merrifield ¶ 2-3].
Merrifield fails to explicitly teach A processor comprising: one or more circuits to schedule one or more instructions to be performed by two or more processors of a node of a plurality of nodes each comprising a respective plurality of processors, and select the two or more processors.
However, Jiang teaches:
A processor comprising: one or more circuits to schedule one or more instructions to be performed by two or more processors of a node of a plurality of nodes each comprising a respective plurality of processors, “When executing this guest device driver, a processor of this particular endpoint device determines a task is ready for data transfer between two endpoint devices of the guest VM that utilizes a first hardware topology (block 902)” [Jiang ¶ 53]. “Referring to FIG. 8, a generalized diagram is shown of tables 800 used for scheduling tasks on multiple endpoint devices using virtual resources” [Jiang ¶ 49]. “Systems and methods for efficiently scheduling tasks to multiple endpoint devices are contemplated. In various implementations, multiple endpoint devices are placed in a computing system. The endpoint devices include one or more of a general-purpose microprocessor, a parallel data processor or processing unit, local memory, and one or more link or other interconnect interfaces for transferring data with other endpoint devices” [Jiang ¶ 17].
and select the two or more processors “In an implementation, the processor selects a pair of endpoint devices listed in the table that provide a smallest latency or smallest distance for data transfer based on the physical hardware topology. Following, the processor schedules the task on the selected pair of endpoint devices” [Jiang ¶ 18].
Jiang is considered to be analogous to the claimed invention because it is in the same field of task scheduling strategies. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Merrifield to incorporate the teachings of Jiang and include a processor comprising: one or more circuits to schedule one or more instructions to be performed by two or more processors of a node of a plurality of nodes each comprising a respective plurality of processors, and select the two or more processors. Doing so would allow for effectively scheduling tasks between multiple processors. “For example, the guest VM being executed by the processor of the endpoint device generates an operating system (OS) call to determine the latencies. These latencies rely on the latency information based on the guest VM topology, rather than the physical hardware topology. Therefore, when executing the device driver, the processor schedules tasks with mispredicted latencies between nodes of the computing system such as between two processors located in the computing system” [Jiang ¶ 2].
Merrifield in view of Jiang fails to explicitly teach wherein to schedule the one or more instructions the one or more circuits are to: determine respective node labels assigned to one or more nodes of the plurality of nodes, each respective node label indicating a number of processors to be used for instructions scheduled to the node to which the label is assigned; based, at least in part, on the respective node labels.
However, Konik teaches:
wherein to schedule the one or more instructions the one or more circuits are to: determine respective node labels assigned to one or more nodes of the plurality of nodes, each respective node label indicating a number of processors to be used for instructions scheduled to the node to which the label is assigned; “The virtual machines 150-1, 150-2, 150-3, 150-4, and 150-5 and the server computers 100-1 and 100-2 may send their respective virtual machine data 152-1 and 152-2 (or entries within the virtual machine data 152-1 and 152-2) to each other and receive the virtual machine data 152-1 and 152-2 (or entries) from each other” [Konik ¶ 36]. “The virtual machine data 152 comprises any number of entries, such as the example entries 302,304,306, and 308, each of which comprises an example virtual machine identifier (ID) field 312, an expiration time field 314, an assigned processors field 316, an allocated memory field 318, and an automatic extension field 320” [Konik ¶ 37]. “The assigned processors field 316, in each entry, specifies the number of the processors 101 or the amount of processor cycles or time slices of the processors 101 that are allocated to the virtual machine 150 identified by the virtual machine identifier field 312, in the same entry” [Konik ¶ 38].
based, at least in part, on the respective node labels “FIGS. 4 and 5 depict flowcharts of example processing for scheduling a task to a virtual machine, according to an embodiment of the invention” [Konik ¶ 39]. “Control then continues to block 415 where the first virtual machine 150 calculates an estimated time to perform the task, using the resources that are allocated to the first virtual machine 150 … In an embodiment, the first virtual machine 150 adjusts the estimated time from the past actual or average time in proportion to the ratio of the amount of resources allocated at the past times and the current time. For example, if the past assigned processors of the first virtual machine 150 were half has much as the current assigned processors 316 of the first virtual machine 150, then the first virtual machine 150 calculates the estimated time to be has half as long as the past actual time” [Konik ¶ 42]. “If the determination at block 505 is true, then a selected virtual machine exists with an estimated time that is before its expiration time 314, and the estimated time of the selected virtual machine is the smallest estimated time of all virtual machines, so control continues to block 510 where the first virtual machine 150 sends the request 156 to perform the task to the selected virtual machine, and the first virtual machine 150 halts the performance of the task. The selected virtual machine receives and performs the task…” [Konik ¶ 47].
Konik is considered to be analogous to the claimed invention because it is in the same field of task scheduling strategies. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Merrifield in view of Jiang to incorporate the teachings of Konik and include wherein to schedule the one or more instructions the one or more circuits are to: determine respective node labels assigned to one or more nodes of the plurality of nodes, each respective node label indicating a number of processors to be used for instructions scheduled to the node to which the label is assigned; based, at least in part, on the respective node labels. Doing so would allow for virtual machine data to be used in the scheduling process. “Control then continues to block 415 where the first virtual machine 150 calculates an estimated time to perform the task, using the resources that are allocated to the first virtual machine 150” [Konik ¶ 42].
With regard to claim 3, Merrifield in view of Jiang in view of Konik teaches the processor of claim 1, as referenced above. Merrifield further teaches wherein the latency of the one or more interconnects is based, at least in part, on proximity of the two or more processors within a non-uniform memory access (NUMA) domain. “As shown in FIG. 2, physical SLIT 200 specifies a latency (also known as "distance") value for every pair of physical NUMA nodes (i, j) that indicates the relative latency of performing a memory access from node i to node j” [Merrifield ¶ 20]. “Like nodes 0 and 1 of blade 114(1), physical NUMA nodes 2 and 3 are coupled via an inter-socket interconnect 116(2) that allows processor socket 110(3) of node 2 to remotely access DRAM 112(4) of node 3 (referred to as "on-blade remote DRAM" from the perspective of processor socket 110(3)/node 2), and allows processor socket 110(4) of node 3 to remotely access DRAM 112(3) of node 2 (referred to as "on-blade remote DRAM" from the perspective of processor socket 110( 4)/node 3)” [Merrifield ¶ 17]. “Large memory and compute systems are typically designed with multiple processor sockets, each directly attached to a pool of local memory and indirectly attached to the local memories of other processor sockets (i.e., remote memories) via an interconnect or bus. This architecture is known as a Non-Uniform Memory Access (NUMA) architecture because each processor socket can access data in its local memory faster (i.e., with lower latency) than data in remote memory. A grouping of a processor socket and its local memory is referred to as a NUMA node. Due to the higher costs of remote memory accesses, it is important for system software to be aware of the memory topology of a NUMA system and the memory access latencies between NUMA nodes. Among other things, this allows the system software to make more informed task placement/memory allocation decisions and thus improve system performance. The Advanced Configuration and Power Interface (ACPI) specification defines a System Locality Information Table (SLIT) that system firmware can use to provide node-to-node latency information to system software” [Merrifield ¶ 2-3].
With regard to claim 4, Merrifield in view of Jiang in view of Konik teaches the processor of claim 1, as referenced above. Merrifield fails to explicitly teach wherein the latency of the one or more interconnects between the two or more processors is based, at least in part, on proximity of one processor performing the one or more instructions to another processor performing the one or more instructions.
However, Jiang teaches wherein the latency of the one or more interconnects between the two or more processors is based, at least in part, on proximity of one processor performing the one or more instructions to another processor performing the one or more instructions. “In an implementation, the processor selects a pair of endpoint devices listed in the table that provide a smallest latency or smallest distance for data transfer based on the physical hardware topology. Following, the processor schedules the task on the selected pair of endpoint devices” [Jiang ¶ 18]. “Multiple endpoint devices are placed in a computing system. The endpoint devices include one or more processors, local memory, and one or more link or other interconnect interfaces for transferring data with other endpoint devices” [Jiang ¶ 52].
With regard to claim 5, Merrifield in view of Jiang in view of Konik teaches the processor of claim 1, as referenced above. Merrifield further teaches wherein the one or more circuits are to schedule the one or more instructions based, at least in part, on a constraint on placement of instructions performed by certain numbers of processors. “This virtual NUMA topology includes one or more virtual NUMA nodes, each comprising a virtual CPU and associated memory, which the hypervisor "places"----or in other words, schedules for execution-on physical NUMA nodes of the system. For example, FIG. 3 depicts a scenario 300 in which VM 104(1) of FIG. 1A is presented a virtual NUMA topology 302 comprising three virtual NUMA nodes 0, 1, and 2 (each with two virtual CPUs), which hypervisor 102 has placed on physical NUMA nodes 0, 1, and 2 respectively” [Merrifield ¶ 21]. “Hypervisor 102 can then expose a virtual SLIT to the VM that includes latency values from the physical SLIT in accordance with the mappings and can pin the virtual NUMA nodes to their mapped physical NUMA nodes, such that the virtual NUMA nodes remain in place throughout the VM's runtime (or in other words, are never migrated way from their mapped physical nodes)” [Merrifield ¶ 24].
With regard to claim 7, Merrifield in view of Jiang in view of Konik teaches the processor of claim 1, as referenced above. Merrifield further teaches:
wherein the one or more circuits are to schedule a subsequent one or more instructions “Within this first loop, hypervisor 102 can determine a mapping between virtual NUMA node i and a single physical NUMA node j based on various factors present at the time of workflow execution (e.g., current compute and memory loads on physical NUMA nodes) (block 606) … Finally, at block 620, hypervisor 102 can allow one or more virtual NUMA nodes of VM 104 to be migrated (subsequent) on a temporary basis to other physical NUMA nodes (i.e., nodes different from the one on which the virtual NUMA node is initially placed) throughout the VM's runtime” [Merrifield ¶ 44]. “Further, rather than strictly pinning each virtual NUMA node to its mapped physical NUMA node, hypervisor 102 can temporarily migrate each virtual NUMA node to different physical NUMA nodes on an as-needed basis” [Merrifield ¶ 28].
based, at least in part, on a second latency that is equivalent to the latency “The Advanced Configuration and Power Interface (ACPI) specification defines a System Locality Information Table (SLIT) that system firmware can use to provide node-to-node latency information to system software. In cases where a NUMA system serves as a virtualization host (i.e., is configured to run a hypervisor and virtual machines (VMs)), it is useful for the hypervisor to expose the system's physical SLIT, or at least some portion thereof, in the form of a "virtual SLIT" to the guest operating system (OS) of each VM. Like the system software of a bare-metal system, the guest OS can use this SLIT information to make intelligent task placement/memory allocation decisions in accordance with the system's underlying memory characteristics” [Merrifield ¶ 3-4]. “Finally, according to the third approach (referred to as "dynamic placement" and detailed in section (6) below), hypervisor 102 can build and expose a virtual SLIT to a VM's guest OS based on one-to-one mappings in a manner that is largely similar to one-to-one static placement approach. However, rather than determining these mappings based on a static user-provided configuration, hypervisor 102 can determine the mappings dynamically at the time of VM power-on based on various runtime factors (e.g., the current compute load on each physical NUMA node, the current memory load on each physical NUMA node, etc.)” [Merrifield ¶ 27].
Merrifield fails to explicitly teach between the two or more processors.
However, Jiang teaches between the two or more processors. “In some implementations, the indication of distance or latency is a non-uniform memory access (NUMA) distance between two nodes such as between two different processors, between a particular processor and a particular memory, or other” [Jiang ¶ 23].
With regard to claim 8, Merrifield teaches:
A system comprising: one or more circuits to schedule one or more instructions to be performed by two or more processors of a node of a plurality of nodes each comprising a respective plurality of processors, “As shown in FIG. 1A, NUMA system 100 includes a hypervisor 102 and one or more VMs (nodes) 104 in software, as well as a physical NUMA topology 106 comprising M physical NUMA nodes 108 (identified via indices 0 to M-1) in hardware” [Merrifield ¶ 15]. “Each physical NUMA node 108 is a logical grouping of a compute resource 110 and a physical memory 112 of NUMA system 100 that exhibits the property of "non-uniform memory access," which means that the compute resource is able access the physical memory of its NUMA node (referred to as local memory) faster-or in other words, with lower latency than the physical memories of other NUMA nodes (referred to as remote memories)” [Merrifield ¶ 15]. “This virtual NUMA topology includes one or more virtual NUMA nodes, each comprising a virtual CPU and associated memory, which the hypervisor "places"----or in other words, schedules for execution-on physical NUMA nodes of the system” [Merrifield ¶21].
a number of processors to be used for instructions scheduled to the node to which the label is assigned; “In a NUMA system like system 100 of FIGS. 1A and 1B, the hypervisor can choose to expose a virtual NUMA topology to the guest OS of a VM based on various factors (e.g., the number of virtual central processing units (CPUs) provisioned for the VM, the amount of memory provisioned for the VM, etc.). This virtual NUMA topology includes one or more virtual NUMA nodes, each comprising a virtual CPU and associated memory, which the hypervisor "places"----or in other words, schedules for execution-on physical NUMA nodes of the system. For example, FIG. 3 depicts a scenario 300 in which VM 104(1) of FIG. 1A is presented a virtual NUMA topology 302 comprising three virtual NUMA nodes 0, 1, and 2 (each with two virtual CPUs), which hypervisor 102 has placed on physical NUMA nodes 0, 1, and 2 respectively” [Merrifield ¶ 21].
based, at least in part, on the respective node labels and latency of one or more interconnects between the two or more processors. “Large memory and compute systems are typically designed with multiple processor sockets, each directly attached to a pool of local memory and indirectly attached to the local memories of other processor sockets (i.e., remote memories) via an interconnect or bus. This architecture is known as a Non-Uniform Memory Access (NUMA) architecture because each processor socket can access data in its local memory faster (i.e., with lower latency) than data in remote memory. A grouping of a processor socket and its local memory is referred to as a NUMA node. Due to the higher costs of remote memory accesses, it is important for system software to be aware of the memory topology of a NUMA system and the memory access latencies between NUMA nodes. Among other things, this allows the system software to make more informed task placement/memory allocation decisions and thus improve system performance. The Advanced Configuration and Power Interface (ACPI) specification defines a System Locality Information Table (SLIT) that system firmware can use to provide node-to-node latency information to system software” [Merrifield ¶ 2-3].
Merrifield fails to explicitly teach A processor comprising: one or more circuits to schedule one or more instructions to be performed by two or more processors of a node of a plurality of nodes each comprising a respective plurality of processors, and select the two or more processors.
However, Jiang teaches:
A processor comprising: one or more circuits to schedule one or more instructions to be performed by two or more processors of a node of a plurality of nodes each comprising a respective plurality of processors, “When executing this guest device driver, a processor of this particular endpoint device determines a task is ready for data transfer between two endpoint devices of the guest VM that utilizes a first hardware topology (block 902)” [Jiang ¶ 53]. “Referring to FIG. 8, a generalized diagram is shown of tables 800 used for scheduling tasks on multiple endpoint devices using virtual resources” [Jiang ¶ 49]. “Systems and methods for efficiently scheduling tasks to multiple endpoint devices are contemplated. In various implementations, multiple endpoint devices are placed in a computing system. The endpoint devices include one or more of a general-purpose microprocessor, a parallel data processor or processing unit, local memory, and one or more link or other interconnect interfaces for transferring data with other endpoint devices” [Jiang ¶ 17].
and select the two or more processors “In an implementation, the processor selects a pair of endpoint devices listed in the table that provide a smallest latency or smallest distance for data transfer based on the physical hardware topology. Following, the processor schedules the task on the selected pair of endpoint devices” [Jiang ¶ 18].
Jiang is considered to be analogous to the claimed invention because it is in the same field of task scheduling strategies. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Merrifield to incorporate the teachings of Jiang and include a processor comprising: one or more circuits to schedule one or more instructions to be performed by two or more processors of a node of a plurality of nodes each comprising a respective plurality of processors, and select the two or more processors. Doing so would allow for effectively scheduling tasks between multiple processors. “For example, the guest VM being executed by the processor of the endpoint device generates an operating system (OS) call to determine the latencies. These latencies rely on the latency information based on the guest VM topology, rather than the physical hardware topology. Therefore, when executing the device driver, the processor schedules tasks with mispredicted latencies between nodes of the computing system such as between two processors located in the computing system” [Jiang ¶ 2].
Merrifield in view of Jiang fails to explicitly teach wherein to schedule the one or more instructions the one or more circuits are to: determine respective node labels assigned to one or more nodes of the plurality of nodes, each respective node label indicating a number of processors to be used for instructions scheduled to the node to which the label is assigned; based, at least in part, on the respective node labels.
However, Konik teaches:
wherein to schedule the one or more instructions the one or more circuits are to: determine respective node labels assigned to one or more nodes of the plurality of nodes, each respective node label indicating a number of processors to be used for instructions scheduled to the node to which the label is assigned; “The virtual machines 150-1, 150-2, 150-3, 150-4, and 150-5 and the server computers 100-1 and 100-2 may send their respective virtual machine data 152-1 and 152-2 (or entries within the virtual machine data 152-1 and 152-2) to each other and receive the virtual machine data 152-1 and 152-2 (or entries) from each other” [Konik ¶ 36]. “The virtual machine data 152 comprises any number of entries, such as the example entries 302,304,306, and 308, each of which comprises an example virtual machine identifier (ID) field 312, an expiration time field 314, an assigned processors field 316, an allocated memory field 318, and an automatic extension field 320” [Konik ¶ 37]. “The assigned processors field 316, in each entry, specifies the number of the processors 101 or the amount of processor cycles or time slices of the processors 101 that are allocated to the virtual machine 150 identified by the virtual machine identifier field 312, in the same entry” [Konik ¶ 38].
based, at least in part, on the respective node labels “FIGS. 4 and 5 depict flowcharts of example processing for scheduling a task to a virtual machine, according to an embodiment of the invention” [Konik ¶ 39]. “Control then continues to block 415 where the first virtual machine 150 calculates an estimated time to perform the task, using the resources that are allocated to the first virtual machine 150 … In an embodiment, the first virtual machine 150 adjusts the estimated time from the past actual or average time in proportion to the ratio of the amount of resources allocated at the past times and the current time. For example, if the past assigned processors of the first virtual machine 150 were half has much as the current assigned processors 316 of the first virtual machine 150, then the first virtual machine 150 calculates the estimated time to be has half as long as the past actual time” [Konik ¶ 42]. “If the determination at block 505 is true, then a selected virtual machine exists with an estimated time that is before its expiration time 314, and the estimated time of the selected virtual machine is the smallest estimated time of all virtual machines, so control continues to block 510 where the first virtual machine 150 sends the request 156 to perform the task to the selected virtual machine, and the first virtual machine 150 halts the performance of the task. The selected virtual machine receives and performs the task…” [Konik ¶ 47].
Konik is considered to be analogous to the claimed invention because it is in the same field of task scheduling strategies. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Merrifield in view of Jiang to incorporate the teachings of Konik and include wherein to schedule the one or more instructions the one or more circuits are to: determine respective node labels assigned to one or more nodes of the plurality of nodes, each respective node label indicating a number of processors to be used for instructions scheduled to the node to which the label is assigned; based, at least in part, on the respective node labels. Doing so would allow for virtual machine data to be used in the scheduling process. “Control then continues to block 415 where the first virtual machine 150 calculates an estimated time to perform the task, using the resources that are allocated to the first virtual machine 150” [Konik ¶ 42].
With regard to claim 10, Merrifield in view of Jiang in view of Konik teaches the system of claim 8, as referenced above. Merrifield further teaches wherein the latency of the one or more interconnects is based, at least in part, on proximity of the two or more processors. “As shown in FIG. 2, physical SLIT 200 specifies a latency (also known as "distance") value for every pair of physical NUMA nodes (i, j) that indicates the relative latency of performing a memory access from node i to node j” [Merrifield ¶ 20]. “Like nodes 0 and 1 of blade 114(1), physical NUMA nodes 2 and 3 are coupled via an inter-socket interconnect 116(2) that allows processor socket 110(3) of node 2 to remotely access DRAM 112(4) of node 3 (referred to as "on-blade remote DRAM" from the perspective of processor socket 110(3)/node 2), and allows processor socket 110(4) of node 3 to remotely access DRAM 112(3) of node 2 (referred to as "on-blade remote DRAM" from the perspective of processor socket 110( 4)/node 3)” [Merrifield ¶ 17]. “Large memory and compute systems are typically designed with multiple processor sockets, each directly attached to a pool of local memory and indirectly attached to the local memories of other processor sockets (i.e., remote memories) via an interconnect or bus. This architecture is known as a Non-Uniform Memory Access (NUMA) architecture because each processor socket can access data in its local memory faster (i.e., with lower latency) than data in remote memory. A grouping of a processor socket and its local memory is referred to as a NUMA node. Due to the higher costs of remote memory accesses, it is important for system software to be aware of the memory topology of a NUMA system and the memory access latencies between NUMA nodes. Among other things, this allows the system software to make more informed task placement/memory allocation decisions and thus improve system performance. The Advanced Configuration and Power Interface (ACPI) specification defines a System Locality Information Table (SLIT) that system firmware can use to provide node-to-node latency information to system software” [Merrifield ¶ 2-3].
With regard to claim 11, Merrifield in view of Jiang in view of Konik teaches the system of claim 8, as referenced above. Merrifield further teaches wherein the latency of the one or more interconnects is based, at least in part, on a socket domain. “Large memory and compute systems are typically designed with multiple processor sockets, each directly attached to a pool of local memory and indirectly attached to the local memories of other processor sockets (i.e., remote memories) via an interconnect or bus. This architecture is known as a Non-Uniform Memory Access (NUMA) architecture because each processor socket can access data in its local memory faster (i.e., with lower latency) than data in remote memory. A grouping (domain) of a processor socket and its local memory is referred to as a NUMA node. Due to the higher costs of remote memory accesses, it is important for system software to be aware of the memory topology of a NUMA system and the memory access latencies between NUMA nodes. Among other things, this allows the system software to make more informed task placement/memory allocation decisions and thus improve system performance” [Merrifield ¶ 2-3].
With regard to claim 13, Merrifield in view of Jiang in view of Konik teaches the system of claim 8, as referenced above. Merrifield further teaches:
wherein the one or more processors are to schedule a second one or more instructions to be performed by a second one or more processors “Within this first loop, hypervisor 102 can determine a mapping between virtual NUMA node i and a single physical NUMA node j based on various factors present at the time of workflow execution (e.g., current compute and memory loads on physical NUMA nodes) (block 606) … Finally, at block 620, hypervisor 102 can allow one or more virtual NUMA nodes of VM 104 to be migrated (subsequent) on a temporary basis to other physical NUMA nodes (i.e., nodes different from the one on which the virtual NUMA node is initially placed) throughout the VM's runtime” [Merrifield ¶ 44]. “Further, rather than strictly pinning each virtual NUMA node to its mapped physical NUMA node, hypervisor 102 can temporarily migrate each virtual NUMA node to different physical NUMA nodes on an as-needed basis” [Merrifield ¶ 28].
based, at least in part, on an equivalent latency of the latency “The Advanced Configuration and Power Interface (ACPI) specification defines a System Locality Information Table (SLIT) that system firmware can use to provide node-to-node latency information to system software. In cases where a NUMA system serves as a virtualization host (i.e., is configured to run a hypervisor and virtual machines (VMs)), it is useful for the hypervisor to expose the system's physical SLIT, or at least some portion thereof, in the form of a "virtual SLIT" to the guest operating system (OS) of each VM. Like the system software of a bare-metal system, the guest OS can use this SLIT information to make intelligent task placement/memory allocation decisions in accordance with the system's underlying memory characteristics” [Merrifield ¶ 3-4]. “Finally, according to the third approach (referred to as "dynamic placement" and detailed in section (6) below), hypervisor 102 can build and expose a virtual SLIT to a VM's guest OS based on one-to-one mappings in a manner that is largely similar to one-to-one static placement approach. However, rather than determining these mappings based on a static user-provided configuration, hypervisor 102 can determine the mappings dynamically at the time of VM power-on based on various runtime factors (e.g., the current compute load on each physical NUMA node, the current memory load on each physical NUMA node, etc.)” [Merrifield ¶ 27].
of one or more interconnects. “Large memory and compute systems are typically designed with multiple processor sockets, each directly attached to a pool of local memory and indirectly attached to the local memories of other processor sockets (i.e., remote memories) via an interconnect or bus. This architecture is known as a Non-Uniform Memory Access (NUMA) architecture because each processor socket can access data in its local memory faster (i.e., with lower latency) than data in remote memory. A grouping of a processor socket and its local memory is referred to as a NUMA node. Due to the higher costs of remote memory accesses, it is important for system software to be aware of the memory topology of a NUMA system and the memory access latencies between NUMA nodes” [Merrifield ¶ 2-3]. “Like nodes 0 and 1 of blade 114(1), physical NUMA nodes 2 and 3 are coupled via an inter-socket interconnect 116(2) that allows processor socket 110(3) of node 2 to remotely access DRAM 112(4) of node 3 (referred to as "on-blade remote DRAM" from the perspective of processor socket 110(3)/node 2), and allows processor socket 110(4) of node 3 to remotely access DRAM 112(3) of node 2 (referred to as "on-blade remote DRAM" from the perspective of processor socket 110( 4)/node 3)” [Merrifield ¶ 17].
With regard to claim 15, Merrifield teaches:
A method comprising: scheduling one or more instructions to be performed by two or more processors of a node of a plurality of nodes each comprising a respective plurality of processors, “As shown in FIG. 1A, NUMA system 100 includes a hypervisor 102 and one or more VMs (nodes) 104 in software, as well as a physical NUMA topology 106 comprising M physical NUMA nodes 108 (identified via indices 0 to M-1) in hardware” [Merrifield ¶ 15]. “Each physical NUMA node 108 is a logical grouping of a compute resource 110 and a physical memory 112 of NUMA system 100 that exhibits the property of "non-uniform memory access," which means that the compute resource is able access the physical memory of its NUMA node (referred to as local memory) faster-or in other words, with lower latency than the physical memories of other NUMA nodes (referred to as remote memories)” [Merrifield ¶ 15]. “This virtual NUMA topology includes one or more virtual NUMA nodes, each comprising a virtual CPU and associated memory, which the hypervisor "places"----or in other words, schedules for execution-on physical NUMA nodes of the system” [Merrifield ¶21].
a number of processors to be used for instructions scheduled to the node to which the label is assigned; “In a NUMA system like system 100 of FIGS. 1A and 1B, the hypervisor can choose to expose a virtual NUMA topology to the guest OS of a VM based on various factors (e.g., the number of virtual central processing units (CPUs) provisioned for the VM, the amount of memory provisioned for the VM, etc.). This virtual NUMA topology includes one or more virtual NUMA nodes, each comprising a virtual CPU and associated memory, which the hypervisor "places"----or in other words, schedules for execution-on physical NUMA nodes of the system. For example, FIG. 3 depicts a scenario 300 in which VM 104(1) of FIG. 1A is presented a virtual NUMA topology 302 comprising three virtual NUMA nodes 0, 1, and 2 (each with two virtual CPUs), which hypervisor 102 has placed on physical NUMA nodes 0, 1, and 2 respectively” [Merrifield ¶ 21].
based, at least in part, on the respective node labels and latency of one or more interconnects between the two or more processors. “Large memory and compute systems are typically designed with multiple processor sockets, each directly attached to a pool of local memory and indirectly attached to the local memories of other processor sockets (i.e., remote memories) via an interconnect or bus. This architecture is known as a Non-Uniform Memory Access (NUMA) architecture because each processor socket can access data in its local memory faster (i.e., with lower latency) than data in remote memory. A grouping of a processor socket and its local memory is referred to as a NUMA node. Due to the higher costs of remote memory accesses, it is important for system software to be aware of the memory topology of a NUMA system and the memory access latencies between NUMA nodes. Among other things, this allows the system software to make more informed task placement/memory allocation decisions and thus improve system performance. The Advanced Configuration and Power Interface (ACPI) specification defines a System Locality Information Table (SLIT) that system firmware can use to provide node-to-node latency information to system software” [Merrifield ¶ 2-3].
Merrifield fails to explicitly teach A processor comprising: one or more circuits to schedule one or more instructions to be performed by two or more processors of a node of a plurality of nodes each comprising a respective plurality of processors, and select the two or more processors.
However, Jiang teaches:
A processor comprising: one or more circuits to schedule one or more instructions to be performed by two or more processors of a node of a plurality of nodes each comprising a respective plurality of processors, “When executing this guest device driver, a processor of this particular endpoint device determines a task is ready for data transfer between two endpoint devices of the guest VM that utilizes a first hardware topology (block 902)” [Jiang ¶ 53]. “Referring to FIG. 8, a generalized diagram is shown of tables 800 used for scheduling tasks on multiple endpoint devices using virtual resources” [Jiang ¶ 49]. “Systems and methods for efficiently scheduling tasks to multiple endpoint devices are contemplated. In various implementations, multiple endpoint devices are placed in a computing system. The endpoint devices include one or more of a general-purpose microprocessor, a parallel data processor or processing unit, local memory, and one or more link or other interconnect interfaces for transferring data with other endpoint devices” [Jiang ¶ 17].
and select the two or more processors “In an implementation, the processor selects a pair of endpoint devices listed in the table that provide a smallest latency or smallest distance for data transfer based on the physical hardware topology. Following, the processor schedules the task on the selected pair of endpoint devices” [Jiang ¶ 18].
Jiang is considered to be analogous to the claimed invention because it is in the same field of task scheduling strategies. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Merrifield to incorporate the teachings of Jiang and include a processor comprising: one or more circuits to schedule one or more instructions to be performed by two or more processors of a node of a plurality of nodes each comprising a respective plurality of processors, and select the two or more processors. Doing so would allow for effectively scheduling tasks between multiple processors. “For example, the guest VM being executed by the processor of the endpoint device generates an operating system (OS) call to determine the latencies. These latencies rely on the latency information based on the guest VM topology, rather than the physical hardware topology. Therefore, when executing the device driver, the processor schedules tasks with mispredicted latencies between nodes of the computing system such as between two processors located in the computing system” [Jiang ¶ 2].
Merrifield in view of Jiang fails to explicitly teach wherein to schedule the one or more instructions the one or more circuits are to: determine respective node labels assigned to one or more nodes of the plurality of nodes, each respective node label indicating a number of processors to be used for instructions scheduled to the node to which the label is assigned; based, at least in part, on the respective node labels.
However, Konik teaches:
wherein to schedule the one or more instructions the one or more circuits are to: determine respective node labels assigned to one or more nodes of the plurality of nodes, each respective node label indicating a number of processors to be used for instructions scheduled to the node to which the label is assigned; “The virtual machines 150-1, 150-2, 150-3, 150-4, and 150-5 and the server computers 100-1 and 100-2 may send their respective virtual machine data 152-1 and 152-2 (or entries within the virtual machine data 152-1 and 152-2) to each other and receive the virtual machine data 152-1 and 152-2 (or entries) from each other” [Konik ¶ 36]. “The virtual machine data 152 comprises any number of entries, such as the example entries 302,304,306, and 308, each of which comprises an example virtual machine identifier (ID) field 312, an expiration time field 314, an assigned processors field 316, an allocated memory field 318, and an automatic extension field 320” [Konik ¶ 37]. “The assigned processors field 316, in each entry, specifies the number of the processors 101 or the amount of processor cycles or time slices of the processors 101 that are allocated to the virtual machine 150 identified by the virtual machine identifier field 312, in the same entry” [Konik ¶ 38].
based, at least in part, on the respective node labels “FIGS. 4 and 5 depict flowcharts of example processing for scheduling a task to a virtual machine, according to an embodiment of the invention” [Konik ¶ 39]. “Control then continues to block 415 where the first virtual machine 150 calculates an estimated time to perform the task, using the resources that are allocated to the first virtual machine 150 … In an embodiment, the first virtual machine 150 adjusts the estimated time from the past actual or average time in proportion to the ratio of the amount of resources allocated at the past times and the current time. For example, if the past assigned processors of the first virtual machine 150 were half has much as the current assigned processors 316 of the first virtual machine 150, then the first virtual machine 150 calculates the estimated time to be has half as long as the past actual time” [Konik ¶ 42]. “If the determination at block 505 is true, then a selected virtual machine exists with an estimated time that is before its expiration time 314, and the estimated time of the selected virtual machine is the smallest estimated time of all virtual machines, so control continues to block 510 where the first virtual machine 150 sends the request 156 to perform the task to the selected virtual machine, and the first virtual machine 150 halts the performance of the task. The selected virtual machine receives and performs the task…” [Konik ¶ 47].
Konik is considered to be analogous to the claimed invention because it is in the same field of task scheduling strategies. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Merrifield in view of Jiang to incorporate the teachings of Konik and include wherein to schedule the one or more instructions the one or more circuits are to: determine respective node labels assigned to one or more nodes of the plurality of nodes, each respective node label indicating a number of processors to be used for instructions scheduled to the node to which the label is assigned; based, at least in part, on the respective node labels. Doing so would allow for virtual machine data to be used in the scheduling process. “Control then continues to block 415 where the first virtual machine 150 calculates an estimated time to perform the task, using the resources that are allocated to the first virtual machine 150” [Konik ¶ 42].
With regard to claim 17, Merrifield in view of Jiang in view of Konik teaches the method of claim 15, as referenced above. Merrifield further teaches wherein the latency of the two or more interconnects is based, at least in part, on proximity of the two or more processors. “As shown in FIG. 2, physical SLIT 200 specifies a latency (also known as "distance") value for every pair of physical NUMA nodes (i, j) that indicates the relative latency of performing a memory access from node i to node j” [Merrifield ¶ 20]. “Like nodes 0 and 1 of blade 114(1), physical NUMA nodes 2 and 3 are coupled via an inter-socket interconnect 116(2) that allows processor socket 110(3) of node 2 to remotely access DRAM 112(4) of node 3 (referred to as "on-blade remote DRAM" from the perspective of processor socket 110(3)/node 2), and allows processor socket 110(4) of node 3 to remotely access DRAM 112(3) of node 2 (referred to as "on-blade remote DRAM" from the perspective of processor socket 110( 4)/node 3)” [Merrifield ¶ 17]. “Large memory and compute systems are typically designed with multiple processor sockets, each directly attached to a pool of local memory and indirectly attached to the local memories of other processor sockets (i.e., remote memories) via an interconnect or bus. This architecture is known as a Non-Uniform Memory Access (NUMA) architecture because each processor socket can access data in its local memory faster (i.e., with lower latency) than data in remote memory. A grouping of a processor socket and its local memory is referred to as a NUMA node. Due to the higher costs of remote memory accesses, it is important for system software to be aware of the memory topology of a NUMA system and the memory access latencies between NUMA nodes. Among other things, this allows the system software to make more informed task placement/memory allocation decisions and thus improve system performance. The Advanced Configuration and Power Interface (ACPI) specification defines a System Locality Information Table (SLIT) that system firmware can use to provide node-to-node latency information to system software” [Merrifield ¶ 2-3].
With regard to claim 18, Merrifield in view of Jiang in view of Konik teaches the method of claim 15, as referenced above. Merrifield further teaches wherein the scheduling the one or more instructions is based, at least in part, on a constraint placement of instructions performed by a certain number of processors. “Multiple containers can share the same kernel, but each container can be constrained to only use a defined amount of resources such as CPU, memory, and I/O” [Merrifield ¶ 47]. “In a NUMA system like system 100 of FIGS. 1A and 1B, the hypervisor can choose to expose a virtual NUMA topology to the guest OS of a VM based on various factors (e.g., the number of virtual central processing units (CPUs) provisioned for the VM, the amount of memory provisioned for the VM, etc.)” [Merrifield ¶ 21].
With regard to claim 19, Merrifield in view of Jiang in view of Konik teaches the method of claim 15, as referenced above. Merrifield further teaches wherein the latency of the one or more interconnects is based, at least in part, on a socket domain. “Large memory and compute systems are typically designed with multiple processor sockets, each directly attached to a pool of local memory and indirectly attached to the local memories of other processor sockets (i.e., remote memories) via an interconnect or bus. This architecture is known as a Non-Uniform Memory Access (NUMA) architecture because each processor socket can access data in its local memory faster (i.e., with lower latency) than data in remote memory. A grouping (domain) of a processor socket and its local memory is referred to as a NUMA node. Due to the higher costs of remote memory accesses, it is important for system software to be aware of the memory topology of a NUMA system and the memory access latencies between NUMA nodes. Among other things, this allows the system software to make more informed task placement/memory allocation decisions and thus improve system performance” [Merrifield ¶ 2-3].
Claims 2, 6, 9, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Merrifield (US 2023/0012606 A1) in view of Jiang (US 2023/0401082 A1) in view of Konik (US 2014/0173614 A1) in view of Lu (US 2022/0075637 A1).
Regarding Claim 2, Merrifield in view of Jiang in view of Konik teaches the processor of claim 1, as referenced above. Merrifield in view of Jiang in view of Konik fails to teach wherein another node label assigned to at least one or more nodes is indicative of a maximum number of processors to perform instructions at the at least one node.
However, Lu teaches wherein another node label assigned to at least one or more nodes is indicative of a maximum number of processors to perform instructions at the at least one node. “With CPU and memory hot-add components 114 and 116, hypervisor 106 can turn on CPU and memory hot-add functionality for VM 108 and thereby enable a user to dynamically add vCPUs and/or memory to the VM during its runtime” [Lu ¶ 14]. “At a high level, these techniques involve computing a "virtual NUMA node size" for the VM (i.e., a maximum number of vCPUs and maximum amount of RAM to be included in each of the VM's virtual NUMA nodes), creating a virtual NUMA topology for the VM based on the computed virtual NUMA node size and the VM's provisioned vCPUs and memory, and exposing the virtual NUMA topology to the VM” [Lu ¶ 10].
Lu is considered to be analogous to the claimed invention because it is in the same field of task scheduling strategies. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Merrifield in view of Jiang in view of Konik to incorporate the teachings of Lu and include wherein another node label assigned to at least one or more nodes is indicative of a maximum number of processors to perform instructions at the at least one node. Doing so would allow for the addition of virtual processors and memory supported by the system hypervisor. “However, as part of block 506, rather than simply creating and populating a set of mappings in the VM's virtual firmware that associate each existing vCPU and memory region of VM 108 with a corresponding existing virtual NUMA node in the virtual NUMA topology, hypervisor 106 can also create/populate a set of mappings that associate "placeholder" vCPUs (i.e., vCPUs that are not currently present in the virtual NUMA topology) with corresponding existing or placeholder virtual NUMA nodes, based on the maximum number of vCPUs supported by hypervisor 106” [Lu ¶ 31].
Regarding Claim 6, Merrifield in view of Jiang in view of Konik teaches the processor of claim 1, as referenced above. Merrifield in view of Jiang in view of Konik fails to teach wherein the one or more circuits are to schedule the one or more instructions based, at least in part, on a dynamic labeling of the plurality of nodes.
However, Lu teaches wherein the one or more circuits are to schedule the one or more instructions based, at least in part, on a dynamic labeling of the plurality of nodes. “With CPU and memory hot-add components 114 and 116, hypervisor 106 can turn on CPU and memory hot-add functionality for VM 108 and thereby enable a user to dynamically add vCPUs and/or memory to the VM during its runtime” [Lu ¶ 14]. “At a high level, these techniques involve computing a "virtual NUMA node size" for the VM (i.e., a maximum (dynamic labeling) number of vCPUs and maximum amount of RAM to be included in each of the VM's virtual NUMA nodes), creating a virtual NUMA topology for the VM based on the computed virtual NUMA node size and the VM's provisioned vCPUs and memory, and exposing the virtual NUMA topology to the VM” [Lu ¶ 10].
It would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Merrifield in view of Jiang in view of Konik to incorporate the teachings of Lu and include wherein the one or more circuits are to schedule the one or more instructions based, at least in part, on a dynamic labeling of the plurality of nodes. Doing so would allow for the addition of virtual processors and memory supported by the system hypervisor. “However, as part of block 506, rather than simply creating and populating a set of mappings in the VM's virtual firmware that associate each existing vCPU and memory region of VM 108 with a corresponding existing virtual NUMA node in the virtual NUMA topology, hypervisor 106 can also create/populate a set of mappings that associate "placeholder" vCPUs (i.e., vCPUs that are not currently present in the virtual NUMA topology) with corresponding existing or placeholder virtual NUMA nodes, based on the maximum number of vCPUs supported by hypervisor 106” [Lu ¶ 31].
Regarding Claim 9, Merrifield in view of Jiang in view of Konik teaches the system of claim 8, as referenced above. Merrifield fails to teach wherein another node label assigned to at least one of the one or more nodes is indicative of a dynamic number of processors to perform instructions.
Merrifield fails to teach wherein another node label assigned to at least one of the one or more nodes is indicative of a dynamic number of processors to perform instructions.
However, Lu teaches wherein another node label assigned to at least one of the one or more nodes is indicative of a dynamic number of processors to perform instructions. “With CPU and memory hot-add components 114 and 116, hypervisor 106 can turn on CPU and memory hot-add functionality for VM 108 and thereby enable a user to dynamically add vCPUs and/or memory to the VM during its runtime” [Lu ¶ 14]. “At a high level, these techniques involve computing a "virtual NUMA node size" for the VM (i.e., a maximum number of vCPUs and maximum amount of RAM to be included in each of the VM's virtual NUMA nodes), creating a virtual NUMA topology for the VM based on the computed virtual NUMA node size and the VM's provisioned vCPUs and memory, and exposing the virtual NUMA topology to the VM” [Lu ¶ 10].
It would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Merrifield in view of Jiang in view of Konik to incorporate the teachings of Lu and include wherein another node label assigned to at least one of the one or more nodes is indicative of a dynamic number of processors to perform instructions. Doing so would allow for the addition of virtual processors and memory supported by the system hypervisor. “However, as part of block 506, rather than simply creating and populating a set of mappings in the VM's virtual firmware that associate each existing vCPU and memory region of VM 108 with a corresponding existing virtual NUMA node in the virtual NUMA topology, hypervisor 106 can also create/populate a set of mappings that associate "placeholder" vCPUs (i.e., vCPUs that are not currently present in the virtual NUMA topology) with corresponding existing or placeholder virtual NUMA nodes, based on the maximum number of vCPUs supported by hypervisor 106” [Lu ¶ 31].
Regarding Claim 16, Merrifield in view of Jiang in view of Konik teaches the method of claim 15, as referenced above. Merrifield in view of Jiang in view of Konik fails to teach wherein another node label assigned to at least one or more nodes is indicative of a maximum number of processors to perform instructions at the at least one node.
However, Lu teaches wherein another node label assigned to at least one or more nodes is indicative of a maximum number of processors to perform instructions at the at least one node. “With CPU and memory hot-add components 114 and 116, hypervisor 106 can turn on CPU and memory hot-add functionality for VM 108 and thereby enable a user to dynamically add vCPUs and/or memory to the VM during its runtime” [Lu ¶ 14]. “At a high level, these techniques involve computing a "virtual NUMA node size" for the VM (i.e., a maximum number of vCPUs and maximum amount of RAM to be included in each of the VM's virtual NUMA nodes), creating a virtual NUMA topology for the VM based on the computed virtual NUMA node size and the VM's provisioned vCPUs and memory, and exposing the virtual NUMA topology to the VM” [Lu ¶ 10].
Lu is considered to be analogous to the claimed invention because it is in the same field of task scheduling strategies. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Merrifield in view of Jiang in view of Konik to incorporate the teachings of Lu and include wherein another node label assigned to at least one or more nodes is indicative of a maximum number of processors to perform instructions at the at least one node. Doing so would allow for the addition of virtual processors and memory supported by the system hypervisor. “However, as part of block 506, rather than simply creating and populating a set of mappings in the VM's virtual firmware that associate each existing vCPU and memory region of VM 108 with a corresponding existing virtual NUMA node in the virtual NUMA topology, hypervisor 106 can also create/populate a set of mappings that associate "placeholder" vCPUs (i.e., vCPUs that are not currently present in the virtual NUMA topology) with corresponding existing or placeholder virtual NUMA nodes, based on the maximum number of vCPUs supported by hypervisor 106” [Lu ¶ 31].
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Merrifield (US 2023/0012606 A1) in view of Jiang (US 2023/0401082 A1) in view of Konik (US 2014/0173614 A1) in view of Lu (US 2022/0075637 A1) in view of Jacobs (US 2014/0115593 A1).
Regarding Claim 12, Merrifield in view of Jiang in view of Konik teaches the system of claim 8, as referenced above. Merrifield in view of Jiang in view of Konik fails to teach wherein a dynamic label of processors changes.
However, Lu teaches wherein a dynamic label of processors changes “Upon receiving this request, hypervisor 106 can check whether any of the existing virtual NUMA nodes in the virtual NUMA topology of VM 108 include a placeholder (i.e., disabled) vCPU, per the mappings populated in the VM's virtual firmware data structure at block 506 of FIG. SA (block 510). If the answer is yes, hypervisor 106 can enable that placeholder vCPU by changing is corresponding indicator (dynamic label) from "disabled" to "enabled," thereby causing VM 108 to see it as a newly available vCPU and fulfilling the vCPU hot-add request (block 512)” [Lu ¶ 59].
It would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Merrifield in view of Jiang in view of Konik to incorporate the teachings of Lu and include wherein a dynamic label of processors changes. Doing so would allow for the addition of virtual processors and memory supported by the system hypervisor. “However, as part of block 506, rather than simply creating and populating a set of mappings in the VM's virtual firmware that associate each existing vCPU and memory region of VM 108 with a corresponding existing virtual NUMA node in the virtual NUMA topology, hypervisor 106 can also create/populate a set of mappings that associate "placeholder" vCPUs (i.e., vCPUs that are not currently present in the virtual NUMA topology) with corresponding existing or placeholder virtual NUMA nodes, based on the maximum number of vCPUs supported by hypervisor 106” [Lu ¶ 31].
Additionally, Lu teaches the hot removal of virtual CPUs during runtime. “Further, in certain embodiments logic component 120 of hypervisor 106 can enable the hot-removal of vCPUs, memory regions, and/or fully or partially populated virtual NUMA nodes from VM 108's virtual NUMA topology (in addition to hot-add)” [Lu ¶ 29]. However, Merrifield in view of Jiang in view of Konik in view of Lu fails to explicitly teach based, at least in part, on completion of all instructions being performed by a plurality of processors on a node.
Jacobs teaches based, at least in part, on completion of all instructions being performed by a plurality of processors on a node. “In response to execution of the request completing, the dispatcher 138 removes the stored record of the first virtual processor consuming a home node first physical processor” [Jacobs ¶ 51].
Jacobs is considered to be analogous to the claimed invention because it is in the same field of task scheduling strategies. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Merrifield in view of Jiang in view of Konik in view of Lu to incorporate the teachings of Jacobs and include based, at least in part, on completion of all instructions being performed by a plurality of processors on a node. Doing so would allow for improvements to the performance of virtual processors. “In addition to actively removing virtual processors receiving excess capacity off of their home affinity domain (node) in favor of allowing a virtual processor of a partition to receive entitled cycles in its home affinity domain, the dispatcher takes additional steps to return virtual processors back to their home affinity domain as quickly as possible in the event no choice exists but to run them outside of their home affinity domain (node)” [Jacobs ¶ 17].
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Merrifield (US 2023/0012606 A1) in view of Jiang (US 2023/0401082 A1) in view of Konik (US 2014/0173614 A1) in view of Lu (US 2022/0075637 A1) in view of Loudon (US 2017/0315835 A1).
Regarding Claim 14, Merrifield in view of Jiang in view of Konik in view of Lu teaches the system of claim 9, as referenced above. Merrifield in view of Lu in view of Bruno in view of Lu fails to explicitly teach wherein a percentage of one or more nodes assigned the first and second node label is configurable.
However, Loudon teaches wherein a percentage of one or more nodes assigned the first and second node label is configurable. “In embodiments, time critical virtual machines are fixed to a particular NUMA node. In embodiments, non-time critical virtual machines run applications that do not have such strict requirements” [Loudon ¶ 79]. “In embodiments, the configuring of the first virtual machine comprises pinning the first virtual machine to run only on the subset 106 of cores of the plurality. Due to this pinning, the first virtual machine is dedicated to run on cores 110A and 110B only. In embodiments, the configuring of the second virtual machine comprises not pinning the second virtual machine to run on any particular core of the plurality 110” [Loudon ¶ 54-55 Examiner notes configuring a virtual machine configures its nodes which determine the percentage of the one or more nodes assigned to the first and second node labels].
Loudon is considered to be analogous to the claimed invention because it is in the same field of task scheduling strategies. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Merrifield in view of Jiang in view of Konik in view of Lu to incorporate the teachings of Loudon and include wherein a percentage of one or more nodes assigned the first and second node label is configurable. Doing so would allow for different configurations for time critical and non-time critical applications to improve processing. “Embodiments comprise splitting virtual machines into two types. "Time critical" virtual machines run applications that require uncontended access to CPU resources (for example, those performing media packet forwarding). In embodiments, time critical virtual machines are fixed to a particular NUMA node. In embodiments, non-time critical virtual machines run applications that do not have such strict requirements” [Loudon ¶ 79].
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Merrifield (US 2023/0012606 A1) in view of Jiang (US 2023/0401082 A1) in view of Konik (US 2014/0173614 A1) in view of Lu (US 2022/0075637 A1) in view of Rana (US 2017/0230733 A1).
Regarding Claim 20, Merrifield in view of Jiang in view of Konik in view of Lu teaches the method of claim 15, as referenced above. Merrifield in view of Jiang in view of Konik in view of Lu fails to teach further comprising: generating a fitness score of a node that includes the two or more processors, indicating a different value than a number of processors performing the one or more instructions; and scheduling a second one or more instructions to be performed by a different number of the two or more processors than the number of processors performing the one or more instructions.
However, Lu teaches:
further comprising: generating (a determination) a fitness score of a node that includes the two or more processors, “For example, in a particular implementation pertaining to CPU hot-add, hypervisor 106 can determine whether any existing virtual NUMA node is associated with a "placeholder" vCPU in the virtual firmware data structure which indicates that the virtual NUMA node is not yet full (described in section (4) below). If the answer at block 310 is yes, hypervisor 106 can add the new vCPU or new memory region to that existing virtual NUMA node, thereby fulfilling the hot-add request (block 312)” [Lu ¶ 22-23].
the fitness score indicating a different value than a number of processors performing the one or more instructions; “Turning now to FIG. 3B, at block 308 hypervisor 106 can receive (from, e.g., a user or administrator of VM 108) a request to hot-add a new vCPU or a new memory region to VM 108. Upon receiving this request, hypervisor 106 can check whether any existing virtual NUMA node in the VM's virtual NUMA topology has not yet reached its maximum vCPU or memory limit, per the virtual NUMA node size computed at block 302 of FIG. 3A (block 310)” [Lu ¶ 22 Examiner notes adding a new vCPU increases the number of processors performing the instructions].
and scheduling a second one or more instructions to be performed by a different number of the two or more processors than the number of processors performing the one or more instructions. “CPU hot-add (sometimes referred to as CPU hot-plug) and memory hot-add are features in modern hypervisors that enable a user to add virtual processing cores (i.e., vCPUs) and memory (i.e., RAM) respectively to running virtual machines (VMs)” [Lu ¶ 1]. “If the answer at block 310 is yes, hypervisor 106 can add the new vCPU or new memory region to that existing virtual NUMA node, thereby fulfilling the hot-add request (block 312)” [Lu ¶ 23].
It would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Merrifield to incorporate the teachings of Lu and include further comprising: generating a fitness score of a node that includes the one or more processors, the fitness score indicating a different value than a number of processors performing the two or more instructions; and scheduling a second one or more instructions to be performed by a different number of the two or more processors than the number of processors performing the one or more instructions. Doing so would allow for the addition of virtual processors and memory supported by the system hypervisor. “However, as part of block 506, rather than simply creating and populating a set of mappings in the VM's virtual firmware that associate each existing vCPU and memory region of VM 108 with a corresponding existing virtual NUMA node in the virtual NUMA topology, hypervisor 106 can also create/populate a set of mappings that associate "placeholder" vCPUs (i.e., vCPUs that are not currently present in the virtual NUMA topology) with corresponding existing or placeholder virtual NUMA nodes, based on the maximum number of vCPUs supported by hypervisor 106” [Lu ¶ 31].
Merrifield in view of Jiang in view of Konik in view of Lu in view of Lu fails to teach further comprising: generating a fitness score of a node that includes the two or more processors, the fitness score.
However, Rana teaches further comprising: generating a fitness score of a node that includes the two or more processors, the fitness score. “In various embodiments, scoring logic 128 and/or orchestrator 106 may also rank nodes for workload placement or other purposes (e.g., capacity planning or rebalancing activities including killing or migrating workloads or services or tuning elements on the virtual layer) based on their availability scores and/or edge tension scores. In various embodiments, nodes may be selected for ranking based, at least in part, on available capacity and/or tensions with one or more neighboring nodes, and based, at least in part, on associated features … Selection of one or more nodes may be performed at initial placement of a workload and/or during operation, e.g., in response to a rebalancing” [Rana ¶ 78]. “For example, features associated with processors 140 or co-processors 148 may include one or more of a number of cores, processor speed, cache architecture, memory architecture (e.g., non-uniform memory access (NUMA)), instruction set architecture (ISA), etc” [Rana ¶ 32].
Rana is considered to be analogous to the claimed invention because it is in the same field of task scheduling strategies. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Merrifield in view of Lu to incorporate the teachings of Rana and include further comprising: generating a fitness score of a node that includes the two or more processors, the fitness score. Doing so would allow for further comparing of node capabilities for more efficient hardware usage through workload placement. “In various embodiments, scoring logic 128 and/or orchestrator 106 may also rank nodes for workload placement or other purposes (e.g., capacity planning or rebalancing activities including killing or migrating workloads or services or tuning elements on the virtual layer) based on their availability scores and/or edge tension scores” [Rana ¶ 78].
Response to Arguments
Applicant's arguments filed 04/21/2026 have been fully considered but they are not persuasive. Applicant argues in substance:
I. Merrifield's description of a "grouping" of a "processor socket and its local memory" referred to as a "NUMA node" and "access latencies between NUMA nodes" fails to teach or suggest determine respective node labels assigned to one or more nodes of the plurality of nodes, each respective node label indicating a number of processors to be used for instructions scheduled to the node to which the label is assigned, as recited by amended claim 1. In fact, Merrifield makes no mention of any node labels that are assigned to nodes, much less any indication of a number of processors to be used for instructions scheduled to a particular node.
Furthermore, Merrifield fails to teach or suggest select the two or more processors based, at least in part, on the respective node labels and latency of one or more interconnects between the two or more processors. Instead, Merrifield merely describes a "grouping" of a "processor socket and its local memory" referred to as a "NUMA node" and "access latencies between NUMA nodes," without any mention of the above features of amended claim 1.
The cited reference fails to teach or suggest "wherein to schedule the one or more instructions the one or more circuits are to: determine respective node labels assigned to one or more nodes of the plurality of nodes, each respective node label indicating a number of processors to be used for instructions scheduled to the node to which the label is assigned; and select the two or more processors based, at least in part, on the respective node labels and latency of one or more interconnects between the two or more processors," as recited in amended claim 8.
The cited reference fails to teach or suggest "wherein to schedule the one or more instructions the one or more circuits are to: determine respective node labels assigned to one or more nodes of the plurality of nodes, each respective node label indicating a number of processors to be used for instructions scheduled to the node to which the label is assigned; and select the two or more processors based, at least in part, on the respective node labels and latency of one or more interconnects between the two or more processors," as recited in amended claim 15.
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
II. Even if claim 1 recites a "judicial exception," which Applicant does not concede, Applicant submits that amended claim 1 is not directed to a judicial exception because the claim as a whole integrates the judicial exception into a practical application. As stated in the October 2019 Update, "if the additional limitations reflect an improvement in the functioning of a computer, or an improvement to another technology or technical field, the claim integrates the judicial exception into a practical application and thus imposes a meaningful limit on the judicial exception" and "[t]he claim is eligible at Step 2A." The October 2019 Update also states that "if the specification sets forth an improvement in technology, the claim must be evaluated to ensure that the claim itself reflects the disclosed improvement" and "[t]he claim itself does not need to explicitly recite the improvement described in the specification."18/224,796
Applicant submits that amended claim 1 satisfies the above considerations indicative of elements that have integrated the exception into a practical application. For example, claim 1 recites "select the two or more processors based, at least in part, on the respective node labels and latency of one or more interconnects between the two or more processors."
The Specification states that "[e]xisting techniques to allocate processing resources to a workload in a group of computing devices yield inefficient results" and that "if a scheduler schedules several workloads to be performed using different computing clusters, said clusters can vary in performance and variation in performance can affect scheduling of these jobs and predictability of scheduling" and that "scheduling, including allocating of resource to perform workloads, can be improved." Specification, paragraph [0003]. The Specification further states that "[t]echniques presented herein are an improvement on prior solutions at least because maintaining information of latency of interconnections coupled to processors in computing nodes may be useful for a job scheduler to avoid considerable cost of communicating across memory domain boundaries." Specification, paragraph [0058].
By using a system to select two or more processors to perform instructions based, at least in part, on the respective node labels and latency of one or more interconnects between the two or more processors, the system may improve performance of the instructions by selecting a node with lower latency of interconnects (an improvement in the technical field of compute clusters and data processing).
The 2019 PEG also notes that "because revised Step 2A does not evaluate whether an additional element is well-understood, routine, conventional activity, examiners are reminded that a claim that includes conventional elements may still integrate an exception into a practical application, thereby satisfying the subject matter eligibility requirement of Section 101." Therefore, even if claim 1 recites a "judicial exception," which Applicant does not concede, Applicant submits that claim 1 integrates a "practical application" under Prong 2 according to the 2019 PEG and the October 2019 Update, and therefore is eligible.
Examiner respectfully disagrees. MPEP 2106.04(d)(1) states “Second, if the specification sets forth an improvement in technology, the claim must be evaluated to ensure that the claim itself reflects the disclosed improvement. That is, the claim includes the components or steps of the invention that provide the improvement described in the specification”. From the current claim language, it is unclear that the argued improvements are implemented. The claims merely select nodes which is considered a mental process, because selecting and scheduling can be performed within the human mind. Improvements to a mental process cannot constitute an improvement in a technical field. MPEP 2106.05(a)(II): “However, it is important to keep in mind that an improvement in the abstract idea itself (e.g. a recited fundamental economic concept) is not an improvement in technology. For example, in Trading Technologies Int’l v. IBG, 921 F.3d 1084, 1093-94, 2019 USPQ2d 138290 (Fed. Cir. 2019), the court determined that the claimed user interface simply provided a trader with more information to facilitate market trades, which improved the business process of market trading but did not improve computers or technology”. The argued impartments are directed to the mental process of scheduling, and claims fail to actually implement the improvements to performance of a computer. The arguments have been considered but were not found to be persuasive.
III. As stated in the 2019 PEG, it is possible that a claim that does not "integrate" a recited judicial exception "is nonetheless patent eligible." If a claim has been determined to be directed to a judicial exception under revised Step 2A, examiners should then evaluate the additional elements individually and in combination under Step 2B to determine whether they provide an inventive concept (i.e., whether the additional elements amount to significantly more than the exception itself). If the examiner determines that the element (or combination of elements) amounts to "significantly more" than the exception itself (Step 2B: YES), the claim is eligible, thereby concluding the eligibility analysis. The 2019 PEG further states that a claim that does not meaningfully integrate a judicial exception into a practical application of the exception sufficient to pass muster at Step 2A, may nonetheless include additional subject matter that is unconventional and thus an "inventive concept" at Step 2B.
Even if claim 1 includes a "judicial exception" and does not integrate it into a "practical application," neither of which Applicant concedes, Applicant submits that claim 1 amounts to "significantly more" than a judicial exception. In particular, claim 1 is directed to an inventive concept based on a combination of elements that include "one or more circuits to schedule one or more instructions to be performed by two or more processors of a node of a plurality of nodes each comprising a respective plurality of processors, wherein to schedule the one or more instructions the one or more circuits are to: determine respective node labels assigned to one or more nodes of the plurality of nodes, each respective node label indicating a number of processors to be used for instructions scheduled to the node to which the label is assigned; and select the two or more processors based, at least in part, on the respective node labels and latency of one or more interconnects between the two or more processors."
Applicant submits that the above features of claim 1 reflect improvements in the technical field of compute clusters and data processing, amount to significantly more than a judicial exception, include unconventional subject matter, and provide an inventive concept.
Examiner respectfully disagrees. It is unclear what specific unconventional subject matter Applicant refers to. Further, the determining and selecting of the independent claims are mental processes which are abstract ideas. The additional claim elements of “one or more circuits to schedule one or more instructions to be performed by two or more processors of a node of a plurality of nodes each comprising a respective plurality of processors” are merely generic computing components which fail to integrate the abstract ideas into a practical application, and do not amount to significantly more than the abstract ideas. The arguments have been considered but were not found to be persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
When responding to this Office Action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 CFR 1.111(c).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARI F RIGGINS whose telephone number is (571)272-2772. The examiner can normally be reached Monday-Friday 7:00AM-4:30PM.
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/A.F.R./Examiner, Art Unit 2197
/BRADLEY A TEETS/Supervisory Patent Examiner, Art Unit 2197
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