Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 5 is objected to because of the following informalities: “a gate insulating layer” in line 1. For the sake of compact prosecution, claim 5 is interpreted in the instant Office action as follows: “a gate insulating layer” is found to be a typographical error and is believed to be equivalent to “the gate insulating layer” based on antecedence for this term in claim 1, line 13; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation “the surface of the second field insulating layer” in line . There is insufficient antecedent basis for this limitation in the claim. For the sake of compact prosecution, claim 10 is interpreted in the instant Office action as follows: “the surface of the second field insulating layer” is equivalent to “a surface of the second field insulating layer”. This interpretation is to be confirmed by applicant in the next office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CN 108807282 A, hereinafter “the ‘282 reference”.
Regarding claim 1, the ‘282 reference discloses an Integrated Circuit (IC) semiconductor device (Fig. 2) comprising:
field insulating layers (211) buried in field trenches (212) disposed apart from each other inside a substrate (1);
active regions (10) defined by the field insulating layers;
and active fins (See annotated figure, similarly annotated in Fig. 4. Note: “fins” is interpreted here consistent with Applicant’s disclosure, Fig. 11B: F2) disposed on the active regions (on in the D3 direction, See annotated figure for direction designation) and protruding from surfaces of the field insulating layers (Fig. 2 shows the fins protruding in the D3 direction),
wherein the field insulating layers comprise a first subfield insulating layer (211a) and a second subfield insulating layer (211b), wherein a surface of the first subfield insulating layer (See annotated figure for surface designation) is disposed at a level (D3 level) lower than a level (D3 level) of a surface of the second subfield insulating layer (See annotated figure for surface designation), wherein a single layer (131) covers top portions and side walls of the active fins (covers in the D1/D3 plane as shown in Fig. 2), and wherein the single layer is a gate insulating layer (pg. 11 of translation: “gate dielectric layer”).
Illustrated below are marked and annotated figures of Figs. 2 and 4 of the ‘282 reference.
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Regarding claim 2, the ‘282 reference discloses the IC semiconductor device of claim 1 (Fig. 2), wherein the first subfield insulating layer comprises a first material (pg. 10: “silicon oxide”) and the second subfield insulating layer comprises a second material (pg. 10: “silicon nitride”), and wherein the first material of the first subfield insulating layer has a higher etch selectivity (pg. 9: “fast etching rate”) with respect to a hard mask pattern (the peaks of the active fins) than an etch selectivity of the second material of the second subfield insulating layer (pg. 9: “slower etching rate”. Note: each of 211a and 211b are etched while the peaks of the fins remain, as shown in the method step of Fig. 11 using the etching conditions of pg. 9. Thus, meeting “with respect to a hard mask pattern”).
Regarding claim 3, the ‘282 reference discloses the IC semiconductor device of claim 1 (Fig. 2), wherein: the surface of the first subfield insulating layer has a concave shape (See the enlarged portion of Fig. 2 showing the concave shape), and the surface of the second subfield insulating layer has a flat shape (211b is flat in the D1 direction).
Regarding claim 4, the ‘282 reference discloses the IC semiconductor device of claim 1 (Fig. 2), wherein the active regions have a same body as the active fins (a single integrally formed body is shown).
Regarding claim 5, the ‘282 reference discloses the IC semiconductor device of claim 1 (Fig. 2), wherein a gate insulating layer (forming 131 “sequentially” is shown in the method step of Fig. 13a) and a gate electrode (forming 133 “sequentially” is shown in the method step of Fig. 13a) are sequentially formed on the active fins and the field insulating layers (on in the D3 direction).
Regarding claim 6, the ‘282 reference discloses the IC semiconductor device of claim 5 (Fig. 4), wherein: surfaces of the active fins (See annotated figure for surface designation) and the field insulating layers (See annotated figure for surface designation) are disposed at a level (D3 level) lower than a surface of the substrate (See annotated figure for surface designation; lower in the D3 direction), and the active regions, the active fins, the gate insulating layer, and the gate electrode constitute a Buried Channel Array Transistor (BCAT) (the channel of the transistor of Fig. 4 is buried within 10, and wraps around gate 130 when flowing from source 110 to drain 120; pg. 11 : “source…drain”. Note: this wrapping shape is consistent with Applicant’s disclosure: [0070]: “saddle”).
Regarding independent claim 7, the ‘282 reference discloses an integrated circuit (IC) semiconductor device (Fig. 2) comprising:
field insulating layers (211) buried in field trenches (212) disposed apart from each other inside a substrate (1);
active regions (10) defined by the field insulating layers;
and active fins (See annotated figure, similarly annotated in Fig. 4. Note: “fins” is interpreted here consistent with Applicant’s disclosure, Fig. 11B: F2) disposed on the active regions (on in the D3 direction, See annotated figure for direction designation) and protruding from surfaces of the field insulating layers (Fig. 2 shows the fins protruding in the D3 direction),
wherein: the field insulating layers comprise a first field insulating layer (See annotated figure, a portion of 211) having a first width (W1), a second field insulating layer (See annotated figure) having a second width (W2) that is less than the first width (“less than” is shown in annotated Fig. 1, where W2 is only between adjacent 10, while W1 includes this same distance twice as well as the distance overlapping another 10),
the first field insulating layer comprises a first subfield insulating layer (211a) and a second subfield insulating layer (211b), a surface of the first subfield insulating layer (See annotated figure for surface designation) is disposed at a level (D3 level) lower than a level (D3 level) of a surface of the second subfield insulating layer (See annotated figure for surface designation), a single layer (131) covers top portions and side walls of the active fins (covers in the D1/D3 plane as shown in Fig. 2), and the single layer is a gate insulating layer (pg. 11 of translation: “gate dielectric layer”).
Illustrated below is a marked and annotated figure of Fig. 1 of the ‘282 reference.
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Regarding claim 8, the ‘282 reference discloses the IC semiconductor device of claim 7 (Fig. 1), wherein the first field insulating layer is formed in a region between (between in the D1 direction) outermost portions of the active fins disposed on the active regions (the terminal surfaces of the cited portions of 10 in the D1 direction).
Regarding claim 9, the ‘282 reference discloses the IC semiconductor device of claim 7 (Fig. 2), wherein: the surface of the first subfield insulating layer has a concave shape (See the enlarged portion of Fig. 2 showing the concave shape), and the surface of the second subfield insulating layer has a flat shape (211b is flat in the D1 direction).
Regarding claim 10 as noted in the 112(b) rejection, the ‘282 reference discloses the IC semiconductor device of claim 7 (Fig. 2), wherein a surface of the second field insulating layer (selecting the surface of 211a as a surface of the second field insulating layer”. See annotated figure for surface designation) has a concave shape (See the enlarged portion of Fig. 2 showing the concave shape).
Regarding claim 11, the ‘282 reference discloses the IC semiconductor device of claim 7 (Fig. 2), wherein the second field insulating layer comprises a third subfield insulating layer (211a or 211b).
Regarding claim 12, the ‘282 reference discloses the IC semiconductor device of claim 11 (Fig. 2), wherein a surface of the third subfield insulating layer (selecting 211b as “the third subfield insulating layer”. See annotated figure for surface designation) is disposed at a level (D3 level) higher than another surface of the first subfield insulating layer (higher than a surface of 211a).
Regarding claim 13, the ‘282 reference discloses the IC semiconductor device of claim 11 (Fig. 2), wherein a surface of the second field insulating layer (a surface of 211a) is disposed at a level (D3 level) lower than a surface of the first field insulating layer (a surface of 211b).
Regarding claim 14, the ‘282 reference discloses the IC semiconductor device of claim 11 (Fig. 2), wherein a surface of the third subfield insulating layer (selecting 211a as “the third subfield insulating layer”. See annotated figure for surface designation) has a concave shape (See the enlarged portion of Fig. 2 showing the concave shape).
Claims 15 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 20210126098 A1).
Regarding independent claim 15, Lee discloses an integrated circuit (IC) semiconductor device (Fig. 4) comprising:
field insulating layers (Fig. 4: layer 114/112, and Fig. 5: layer 113) buried in field trenches (114T/112T and 113T respectively) disposed apart from each other inside a substrate (100);
active regions (105) defined by the field insulating layers; and
active fins (105a, 105b) disposed on the active regions and protruding from surfaces of the field insulating layers (protruding in the DR4 direction),
wherein: the field insulating layers comprise a first field insulating layer (114. Note: the layer relied upon is annotated as 114 in Fig. 4 and 112 in Fig. 3 based on different directions of the cross section being shown. See annotated Fig. 2 showing these separate annotations represent the same structure.) having a first width (Fig. 3: w2) and a second field insulating layer (113) having a second width (w3) that is less than the first width (“less than” is shown in annotated Fig. 2, where w3 is only between adjacent ACT/105, while w2 includes this same distance twice as well as the distance overlapping another ACT/105),
the first field insulating layer comprises a first subfield insulating layer (Fig. 4: 120) and a second subfield insulating layer (122), a surface of the first subfield insulating layer and a surface of the second subfield insulating layer have concave shapes (concave in the DR4 direction),
a single layer (131) covers top portions and side walls of the active fins (“covers” in the DR4 and DR2 directions shown in Fig. 3), and the single layer is a gate insulating layer ([0056]: “first gate dielectric film”).
Illustrated below are marked and annotated figures of Figs. 2, 3, and 4 of Lee.
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Regarding claim 18, Lee discloses the IC semiconductor device of claim 15 (Fig. 3), wherein a surface of the first field insulating layer (See annotated figure for surface designation) has a same height (DR4 height) as a surface of the second field insulating layer (See annotated figure for surface designation).
Regarding claim 19, Lee discloses the IC semiconductor device of claim 15 (Fig. 3), wherein the second field insulating layer comprises a single third subfield insulating layer (only 120 is shown for 113, thus “single”).
Regarding claim 20, Lee discloses the IC semiconductor device of claim 15 (Fig. 4), wherein the active regions are a same body as the active fins (a single integrally formed body is shown), and the active fins are formed by recess-etching upper portions of the field insulating layers (the method step shown in Figs. 10a and 10b; [0087]: “recessed”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-17 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of the ‘282 reference.
Regarding claim 16, Lee discloses the IC semiconductor device of claim 15 (Fig. 3), however fails to teach “wherein protective patterns are further formed on both sidewalls of the second field insulating layer that is in contact with the active regions”.
The ‘282 reference discloses protective patterns (Fig. 2: 132) are further formed on (indirectly on) both sidewalls of the second field insulating layer (211. See annotated figure for layer designation) that is in contact with the active regions (active regions 10). The ‘282 reference teaches motivation for including the protective patterns in that it would enable adjusting electrical characteristics of the device (pg. 12 : “work function layer”). Modifying the device of Lee by including the protective patterns of the ‘282 reference in the same way would arrive at the claimed configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success because the ‘282 reference does not require modifying the underlying structures or overlying structures to incorporate these protective patterns. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed protective patterns because it would enable adjusting electrical characteristics of the device. MPEP 2143 (I)(G).
Regarding claim 17, Lee discloses the IC semiconductor device of claim 15 (Fig. 3), wherein a surface of the second field insulating layer has a [shape].
Lee fails to teach “a surface of the second field insulating layer has a concave shape”.
The ‘282 reference teaches a surface of the second field insulating layer (Fig. 2: the surface of 211a. See annotated figure for surface designation) has a concave shape (See the enlarged portion of Fig. 2 showing the concave shape). Modifying the shape of the surface of Lee to have a concave shape in the same way would arrive at the claimed shape configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each scenario an oxide film is etched (Lee: [0041]: “silicon oxide”; the ‘282 reference: pg. 10: “silicon oxide”). The ‘282 reference teaches motivation for modifying the surface shape because surface shape is a design choice according to device requirements (pg. 10: “when forming a micro trench 230, the shape, depth and size of the opening can be adjusted according to the actual requirement”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed concave shape because it is a difference in shape chosen according to device requirements. MPEP 2144.04 (IV)(B).
Response to Arguments
Applicant's arguments filed 1/22/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claim 1 that “Kao fails to disclose the above features of claim 1: “a single layer covers top portions and side walls of the active fins” and “the single layer is a gate insulating layer””. Remarks at pg. 13. Applicant provides similar assertions regarding amended independent claims 7 and 15. Remarks at pg. 13.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 1, 7, and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. New references (the ‘282 reference; Lee) are relied upon in the instant Office action, as necessitated by claim amendment.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
/Kretelia Graham/ Supervisory Patent Examiner, Art Unit 2817 February 17, 2026