Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/17/2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/3/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 (and dependent claims 2-6 dependent therefrom), 7 (and dependent claims 8-10 and 14 dependent therefrom), 14, 15 (and dependent claims 16-17 and 20 dependent therefrom), and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, “a level of a surface of the first subfield insulating layer” in line 16 is unclear whether it is referring to the same “level” and “surface of the first subfield insulating layer” recited in line 13 or some other surface. For the sake of compact prosecution, claim 1 is interpreted in the instant Office action as follows: “a level of a surface of the first subfield insulating layer” in line 16 is referring to the same level and surface, and is equivalent to “the level of the surface of the first subfield insulating layer”. This interpretation is to be confirmed by applicant in next office action.
Regarding claim 7, “a level of a surface of the first subfield insulating layer” in lines 17-18 is unclear whether it is referring to the same “level” and “surface of the first subfield insulating layer” recited in line 14 or some other surface. For the sake of compact prosecution, claim 7 is interpreted in the instant Office action as follows: “a level of a surface of the first subfield insulating layer” in lines 17-18 is referring to the same level and surface, and is equivalent to “the level of the surface of the first subfield insulating layer”. This interpretation is to be confirmed by applicant in next office action.
Regarding claim 14, “a surface of the third subfield insulating layer” in line 2 is unclear whether it is referring to the same “surface of the third subfield insulating layer” recited in claim 7 or some other surface. For the sake of compact prosecution, claim 14 is interpreted in the instant Office action as follows: “a surface of the third subfield insulating layer” in line 2 is referring to the same surface, and is equivalent to “the surface of the third subfield insulating layer”. This interpretation is to be confirmed by applicant in next office action.
Regarding claim 15, “a level of a surface of the first subfield insulating layer” in line 18 is unclear whether it is referring to the same “level” and “surface of the first subfield insulating layer” recited in line 14 or some other surface. For the sake of compact prosecution, claim 15 is interpreted in the instant Office action as follows: “a level of a surface of the first subfield insulating layer” in line 18 is referring to the same level and surface, and is equivalent to “the level of the surface of the first subfield insulating layer”. This interpretation is to be confirmed by applicant in next office action.
Regarding claim 15, “a surface of the first subfield insulating layer and a surface of the second subfield insulating layer” in lines 19-20 is unclear whether it is referring to the same “surface of the first subfield insulating layer” and “surface of the second subfield insulating layer” recited in lines 14-15 or some other surfaces. For the sake of compact prosecution, claim 15 is interpreted in the instant Office action as follows: “a surface of the first subfield insulating layer and a surface of the second subfield insulating layer” in lines 19-20 is referring to the same surfaces, and is equivalent to “the surface of the first subfield insulating layer and the surface of the second subfield insulating layer”. This interpretation is to be confirmed by applicant in next office action.
Regarding claim 17, “a surface of the single third subfield insulating layer” in line 2 is unclear whether it is referring to the same “surface of the single third subfield insulating layer” recited in claim 15 or some other surface. For the sake of compact prosecution, claim 17 is interpreted in the instant Office action as follows: “a surface of the single third subfield insulating layer” in line 2 is referring to the same surface, and is equivalent to “the surface of the single third subfield insulating layer”. This interpretation is to be confirmed by applicant in next office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10, 14-17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CN 108807282 A, hereinafter “the ‘282 reference”.
Regarding claim 1 as noted in the 112(b) rejection, the ‘282 reference discloses an Integrated Circuit (IC) semiconductor device (Fig. 2) comprising:
field insulating layers (211) buried in field trenches (212) disposed apart from each other inside a substrate (1);
active regions (10) defined by the field insulating layers; and
active fins (See annotated Fig. 2, and similarly annotated Fig. 4. Note: “fins” is interpreted here consistent with Applicant’s disclosure, Fig. 11B: F2) disposed on the active regions (“on” in the D3 direction, See annotated figure for direction designation) and protruding from surfaces of the field insulating layers (Fig. 2 shows the fins “protruding” in the D3 direction),
wherein the field insulating layers comprise a first field insulating layer (See annotated figure, a portion of 211) having a first width (W1) and a second field insulating layer (See annotated figure, another portion of 211) having a second width (W2) that is less than the first width (“less than” is shown in annotated Fig. 1, where W2 is only between adjacent 10, while W1 includes this same distance twice as well as the distance overlapping another 10),
wherein the first field insulating layer comprises a first subfield insulating layer (211a) having a third width (W3) and a second subfield insulating layer (211b) having a fourth width (W4) that is larger than the third width (“larger” because of the tapered shape),
wherein a surface of the first subfield insulating layer (Surface A of 211a) is disposed at a level (D3 level) lower than a level (D3 level) of a surface of the second subfield insulating layer (Surface A of 211b),
wherein a surface of the second field insulating layer (Surface B of 211a) is disposed at a level (D3 level) lower than the level of the surface of the first subfield insulating layer (the same surface/level cited above, Surface A of 211a),
wherein a single layer (131) covers top portions and side walls of the active fins (“covers” in the D1/D3 plane as shown in Fig. 2), and
wherein the single layer is a gate insulating layer (pg. 11 of translation: “gate dielectric layer”).
Illustrated below are marked and annotated figures of Figs. 1, 2, and 4 of the ‘282 reference.
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Regarding claim 2, the ‘282 reference discloses the IC semiconductor device of claim 1 (Fig. 2), wherein the first subfield insulating layer comprises a first material (pg. 10: “silicon oxide”) and the second subfield insulating layer comprises a second material (pg. 10: “silicon nitride”), and wherein the first material of the first subfield insulating layer has a higher etch selectivity (pg. 9: “fast etching rate”) with respect to a hard mask pattern (the peaks of the active fins) than an etch selectivity of the second material of the second subfield insulating layer (pg. 9: “slower etching rate”. Note: each of 211a and 211b are etched while the peaks of the fins remain, as shown in the method step of Fig. 11 using the etching conditions of pg. 9. Thus, meeting “with respect to a hard mask pattern”).
Regarding claim 3, the ‘282 reference discloses the IC semiconductor device of claim 1 (Fig. 2), wherein: the surface of the first subfield insulating layer has a concave shape (See the enlarged portion of Fig. 2 showing the concave shape), and the surface of the second subfield insulating layer has a flat shape (211b is flat in the D1 direction).
Regarding claim 4, the ‘282 reference discloses the IC semiconductor device of claim 1 (Fig. 2), wherein the active regions have a same body as the active fins (a single integrally formed body is shown).
Regarding claim 5, the ‘282 reference discloses the IC semiconductor device of claim 1 (Fig. 2), wherein the gate insulating layer (forming 131 “sequentially” is shown in the method step of Fig. 13a) and a gate electrode (forming 133 “sequentially” is shown in the method step of Fig. 13a) are sequentially formed on the active fins and the field insulating layers (on in the D3 direction).
Regarding claim 6, the ‘282 reference discloses the IC semiconductor device of claim 5 (Fig. 4), wherein: surfaces of the active fins (See annotated figure for surface designation) and the field insulating layers (See annotated figure for surface designation) are disposed at a level (D3 level) lower than a surface of the substrate (See annotated figure for surface designation; lower in the D3 direction), and the active regions, the active fins, the gate insulating layer, and the gate electrode constitute a Buried Channel Array Transistor (BCAT) (the channel of the transistor of Fig. 4 is buried within 10, and wraps around gate 130 when flowing from source 110 to drain 120; pg. 11 : “source…drain”. Note: this wrapping shape is consistent with Applicant’s disclosure: [0070]: “saddle”).
Regarding independent claim 7 as noted in the 112(b) rejection, the ‘282 reference discloses an integrated circuit (IC) semiconductor device (Fig. 2) comprising:
field insulating layers (211) buried in field trenches (212) disposed apart from each other inside a substrate (1);
active regions (10) defined by the field insulating layers; and
active fins (See annotated Fig. 2, and similarly annotated Fig. 4. Note: “fins” is interpreted here consistent with Applicant’s disclosure, Fig. 11B: F2) disposed on the active regions (“on” in the D3 direction, See annotated figure for direction designation) and protruding from surfaces of the field insulating layers (Fig. 2 shows the fins “protruding” in the D3 direction),
wherein:
the field insulating layers comprise a first field insulating layer (See annotated figure, a portion of 211) having a first width (W1) and a second field insulating layer (See annotated figure, another portion of 211) having a second width (W2) that is less than the first width (“less than” is shown in annotated Fig. 1, where W2 is only between adjacent 10, while W1 includes this same distance twice as well as the distance overlapping another 10),
the first field insulating layer comprises a first subfield insulating layer (211a) having a third width (W3) and a second subfield insulating layer (211b) having a fourth width (W4) that is larger than the third width (“larger” because of the tapered shape),
a surface of the first subfield insulating layer (Surface A of 211a) is disposed at a level (D3 level) lower than a level (D3 level) of a surface of the second subfield insulating layer (Surface A of 211b),
the second field insulating layer comprises a third subfield insulating layer (211a or 211b, a corresponding portion),
a surface of the third subfield insulating layer (Surface B of 211a/211b) is disposed at a level (D3 level) lower than the level of the surface of the first subfield insulating layer (the same surface/level cited above, Surface A of 211a),
a single layer (131) covers top portions and side walls of the active fins (“covers” in the D1/D3 plane as shown in Fig. 2), and
the single layer is a gate insulating layer (pg. 11 of translation: “gate dielectric layer”).
Regarding claim 8, the ‘282 reference discloses the IC semiconductor device of claim 7 (Fig. 1), wherein the first field insulating layer is formed in a region between (between in the D1 direction) outermost portions of the active fins disposed on the active regions (the terminal surfaces of the cited portions of 10 in the D1 direction).
Regarding claim 9, the ‘282 reference discloses the IC semiconductor device of claim 7 (Fig. 2), wherein: the surface of the first subfield insulating layer has a concave shape (See the enlarged portion of Fig. 2 showing the concave shape), and the surface of the second subfield insulating layer has a flat shape (211b is flat in the D1 direction).
Regarding claim 10, the ‘282 reference discloses the IC semiconductor device of claim 7 (Fig. 2), wherein a surface of the second field insulating layer (selecting surface A of 211a as “a surface of the second field insulating layer”. See annotated figure for surface designation) has a concave shape (See the enlarged portion of Fig. 2 showing the concave shape).
Regarding claim 14 as noted in the 112(b) rejection, the ‘282 reference discloses the IC semiconductor device of claim 7 (Fig. 2), wherein the surface of the third subfield insulating layer (selecting 211a as “the third subfield insulating layer”. See annotated figure for surface designation) has a concave shape (Surface B of 211a has a concave shape when including portions of the sidewalls).
Regarding independent claim 15 as noted in the 112(b) rejections, the ‘282 reference discloses an integrated circuit (IC) semiconductor device (Fig. 2) comprising:
field insulating layers (211) buried in field trenches (212) disposed apart from each other inside a substrate (1);
active regions (10) defined by the field insulating layers; and
active fins (See annotated Fig. 2, and similarly annotated Fig. 4. Note: “fins” is interpreted here consistent with Applicant’s disclosure, Fig. 11B: F2) disposed on the active regions (“on” in the D3 direction, See annotated figure for direction designation) and protruding from surfaces of the field insulating layers (Fig. 2 shows the fins “protruding” in the D3 direction),
wherein:
the field insulating layers comprise a first field insulating layer (See annotated figure, a portion of 211) having a first width (W1) and a second field insulating layer (See annotated figure, another portion of 211) having a second width (W2) that is less than the first width (“less than” is shown in annotated Fig. 1, where W2 is only between adjacent 10, while W1 includes this same distance twice as well as the distance overlapping another 10),
the first field insulating layer comprises a first subfield insulating layer (211a) having a third width (W3) and a second subfield insulating layer (211b) having a fourth width (W4) that is larger than the third width (“larger” because of the tapered shape),
a surface of the first subfield insulating layer (Surface A of 211a) is disposed at a level (D3 level) lower than a level (D3 level) of a surface of the second subfield insulating layer (Surface A of 211b),
the second field insulating layer comprises a single third subfield insulating layer (211a, a corresponding portion, there is only a single 211a),
a surface of the single third subfield insulating layer (Surface B of 211a) is disposed at a level (D3 level) lower than the level of the surface of the first subfield insulating layer (the same surface/level cited above, Surface A of 211a),
the surface of the first subfield insulating layer (See the enlarged portion of Fig. 2 showing the concave shape) and the surface of the second subfield insulating layer have concave shapes (Surface A of 211b has a concave shape when including portions of the sidewalls. See annotated Fig. 4 showing the sidewalls and concave shape),
a single layer (131) covers top portions and side walls of the active fins (“covers” in the D1/D3 plane as shown in Fig. 2), and
the single layer is a gate insulating layer (pg. 11 of translation: “gate dielectric layer”).
Regarding claim 16, the ‘282 reference discloses the IC semiconductor device of claim 15 (Fig. 2), wherein protective patterns (132) are further formed on (indirectly on) both sidewalls of the second field insulating layer that is in contact with the active regions.
Regarding claim 17 as noted in the 112(b) rejection, the ‘282 reference discloses the IC semiconductor device of claim 15 (Fig. 2), wherein the surface of the single third subfield insulating layer has a concave shape (Surface B of 211a has a concave shape when including portions of the sidewalls).
Regarding claim 20, the ‘282 reference discloses the IC semiconductor device of claim 15 (Fig. 2), wherein the active regions are a same body as the active fins (a single integrally formed body is shown), and the active fins are formed by recess-etching upper portions of the field insulating layers (the method step shown in Fig. 11).
Response to Arguments
Applicant's arguments filed 4/17/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claims 1, 7, and 15 that “the '282 reference fails to disclose or teach that the element 211 in FIG. 2 of the '282 reference (allegedly corresponding to the field insulating layer) comprises […] as recited in claim 1”. Remarks at pg. 10.
Examiner’s reply:
The examiner disagrees and points to MPEP 2111: Broadest Reasonable Interpretation. The examiner finds Applicant’s remarks attempting to describe the differences between the disclosed shapes of the field insulating layers from the shapes found in the prior art. However, the widths and surfaces as claimed reasonably encompass designations beyond those explicitly described in Applicant’s disclosure. Applicant’s amendments have changed the scope of the claims, thus necessitating the new grounds of rejection in the instant Office action. The examiner has relied upon the ‘282 reference in the instant Office action for additional teachings as necessitated by the claim amendments. Accordingly, the examiner has included additional citations and annotations to clarify the interpretation of the reference.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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