Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee (US 20230013061 A1).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1, Lee discloses an integrated circuit (IC) semiconductor device (Fig. 7) comprising:
field insulating layers (110/120/115) buried in field trenches (TR2/TR1) disposed apart from each other inside a substrate (100/ACT/Fins, See annotated figure);
active regions (ACT) defined by the field insulating layers; and
active fins (Fins) disposed on the active regions and protruding (“protruding” in the DR4 direction) from surfaces of the field insulating layers (surfaces 110a/115a/120a),
wherein the field insulating layers comprise a first field insulating layer (110/120) having a first width (See annotated figure) and a second field insulating layer (115) having a second width (See annotated figure) that is less than the first width (“less than” is shown in annotated Fig. 1, where W2 is only between adjacent 10, while W1 includes this same distance twice as well as the distance overlapping another 10),
wherein the first field insulating layer comprises a first subfield insulating layer (110) having a third width (See annotated figure) and a second subfield insulating layer (120) having a fourth width (See annotated figure) that is larger than the third width (“larger than” is based on the amount of overlap of these layers),
wherein a top surface (110a) of the first subfield insulating layer is disposed at a level (DR4 “level”) lower than a level (DR4 “level”) of a top surface (120a) of the second subfield insulating layer,
wherein a surface (120 in R1) of the second field insulating layer is disposed at a level (DR4 “level”) lower than a level (DR4 “level”) of the top surface of the first subfield insulating layer,
wherein a single layer (GI) covers top portions and side walls of the active fins, and on the field insulating layers,
wherein the single layer is a gate insulating layer ([0042]: “gate dielectric layer”),
wherein a gate electrode (WL) is further formed on the gate insulating layer, and
wherein a second area (See annotated figure) of portions of the active fins facing the gate electrode (“facing” in the DR2 direction) over the second field insulating layer is larger (“larger” based on the DR4 overlap. Note: this interpretation is consistent with Applicant’s disclosure: Fig. 11B: 138/F2 overlap areas, and Applicant’s remarks entered 8/31/2026: pg. 11) than a first area (See annotated figure) of other portions of the active fins facing the gate electrode (“facing” in the DR2 direction) over the first field insulating layer.
Illustrated below are marked and annotated figures of Figs. 1 and 7 of Lee.
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Regarding claim 2, Lee discloses the IC semiconductor device of claim 1 (Fig. 7), wherein the first subfield insulating layer comprises a first material ([0035]: “silicon oxide”) and the second subfield insulating layer comprises a second material ([0035]: “silicon nitride”), and wherein the first material of the first subfield insulating layer has a higher etch selectivity with respect to a hard mask pattern (method step of Fig. 13 shows mask HM, which is used to produce the resultant shape of layers 110/120. Since layer 110 is etched further than layer120, these materials have the claimed “etch selectivity” configuration; [0075]: “etch selectivity”) than an etch selectivity of the second material of the second subfield insulating layer.
Regarding claim 4, Lee discloses the IC semiconductor device of claim 1 (Fig. 7), wherein the active regions have a same body as the active fins (these structures as cited are integrally formed as “a same body” based on not separation/distinct delineation among these features).
Regarding claim 5, Lee discloses the IC semiconductor device of claim 1 (Fig. 7), wherein the gate insulating layer and the gate electrode are sequentially formed on (directly “on”) the active fins and the field insulating layers.
Regarding claim 6, Lee discloses the IC semiconductor device of claim 5 (Fig. 7), wherein: top surfaces of the active fins (surfaces at TR3) and the field insulating layers (surfaces at TR4) are disposed at a level (DR4 level) lower than a top surface of the substrate (Fig. 3 shows TR3 is “lower” in the DR4 direction than other portions of substrate 100), and the active regions, the active fins, the gate insulating layer, and the gate electrode constitute a Buried Channel Array Transistor (BCAT) ([0075]: “transistor” buried within 100).
Regarding independent claim 7, Lee discloses an integrated circuit (IC) semiconductor device (Fig. 7) comprising:
field insulating layers (110/120/115) buried in field trenches (TR2/TR1) disposed apart from each other inside a substrate (100/ACT/Fins, See annotated figure);
active regions (ACT) defined by the field insulating layers; and
active fins (Fins) disposed on the active regions and protruding (“protruding” in the DR4 direction) from surfaces of the field insulating layers (surfaces 110a/115a/120a),
wherein the field insulating layers comprise a first field insulating layer (110/120) having a first width (See annotated figure) and a second field insulating layer (115) having a second width (See annotated figure) that is less than the first width (“less than” is shown in annotated Fig. 1, where W2 is only between adjacent 10, while W1 includes this same distance twice as well as the distance overlapping another 10),
wherein the first field insulating layer comprises a first subfield insulating layer (110) having a third width (See annotated figure) and a second subfield insulating layer (120) having a fourth width (See annotated figure) that is larger than the third width (“larger than” is based on the amount of overlap of these layers),
wherein a top surface (110a) of the first subfield insulating layer is disposed at a level (DR4 “level”) lower than a level (DR4 “level”) of a top surface (120a) of the second subfield insulating layer,
wherein the second field insulating layer comprises a third subfield insulating layer (115),
wherein a top surface (115a) of the third subfield insulating layer is disposed at a level (DR4 “level”) lower than the level of the top surface of the first subfield insulating layer,
wherein a single layer (GI) covers top portions and side walls of the active fins, and on the field insulating layers,
wherein the single layer is a gate insulating layer ([0042]: “gate dielectric layer”),
wherein a gate electrode (WL) is further formed on the gate insulating layer, and
wherein a second area (See annotated figure) of portions of the active fins facing the gate electrode (“facing” in the DR2 direction) over the second field insulating layer is larger than a first area (See annotated figure) of other portions of the active fins facing the gate electrode (“facing” in the DR2 direction) over the first field insulating layer.
Regarding claim 8, Lee discloses the IC semiconductor device of claim 7 (Fig. 7), wherein the first field insulating layer is formed in a region between (“between” in the DR2 direction) outermost portions of the active fins disposed on the active regions (the terminal surfaces of the cited portions of ACT in the DR2 direction).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference (or combination of references), but are disclosed or rendered obvious by secondary references or remarks.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 1 above, and further in view of CN 108807282 A, hereinafter “the ‘282 reference”.
Regarding claim 3, Lee discloses the IC semiconductor device of claim 1 (Fig. 7), wherein: the top surface of the first subfield insulating layer has a concave shape, and the top surface of the second subfield insulating layer has a flat shape (120a is flat in the DR2 direction).
Lee fails to teach “the top surface of the first subfield insulating layer has a concave shape”.
The ‘282 reference discloses wherein: the top surface of the first subfield insulating layer has a concave shape (See the enlarged portion of Fig. 2 showing the concave shape), and the top surface of the second subfield insulating layer has a flat shape (211b is flat in the D1 direction).
Modifying the shape of “the first subfield insulating layer” by incorporating “a concave shape” (of the ‘282 reference) would arrive at the claimed shape configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success including the claimed shape configuration because it is a known resultant shape (i.e., an inherent shape configuration) produced by similar techniques on similar structures (Lee: Fig. 12 etching technique and [0066]: “etching process”; the ‘282 reference: Fig. 1 etching technique and pg. 3 of translation: “etching process”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed shape configuration because it is a known difference in shape produced by similar techniques on similar structures. MPEP 2144.04 (IV)(B); MPEP 2112 (III).
Illustrated below are marked and annotated figures of Figs. 1, 2, and 4 of the ‘282 reference.
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Claims 9-10 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 7 above, and further in view of “the ‘282 reference”.
Regarding claim 9, Lee discloses the IC semiconductor device of claim 7 (Fig. 7), wherein: the top surface of the first subfield insulating layer has a concave shape, and the top surface of the second subfield insulating layer has a flat shape (120a is flat in the DR2 direction).
Lee fails to teach “the top surface of the first subfield insulating layer has a concave shape”.
The ‘282 reference discloses wherein: the top surface of the first subfield insulating layer has a concave shape (See the enlarged portion of Fig. 2 showing the concave shape), and the top surface of the second subfield insulating layer has a flat shape (211b is flat in the D1 direction).
Modifying the shape of “the first subfield insulating layer” by incorporating “a concave shape” (of the ‘282 reference) would arrive at the claimed shape configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success including the claimed shape configuration because it is a known resultant shape (i.e., an inherent shape configuration) produced by similar techniques on similar structures (Lee: Fig. 12 etching technique and [0066]: “etching process”; the ‘282 reference: Fig. 1 etching technique and pg. 3 of translation: “etching process”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed shape configuration because it is a known difference in shape produced by similar techniques on similar structures. MPEP 2144.04 (IV)(B); MPEP 2112 (III).
Regarding claim 10, Lee discloses the IC semiconductor device of claim 7, but fails to teach “wherein a top surface of the second field insulating layer has a concave shape”.
The ‘282 reference discloses wherein a top surface of the second field insulating layer has a concave shape (See the enlarged portion of Fig. 2 showing the concave shape).
Modifying the shape of “the second field insulating layer” by incorporating “a concave shape” (of the ‘282 reference) would arrive at the claimed shape configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success including the claimed shape configuration because it is a known resultant shape (i.e., an inherent shape configuration) produced by similar techniques on similar structures (Lee: Fig. 12 etching technique and [0066]: “etching process”; the ‘282 reference: Fig. 1 etching technique and pg. 3 of translation: “etching process”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed shape configuration because it is a known difference in shape produced by similar techniques on similar structures. MPEP 2144.04 (IV)(B); MPEP 2112 (III).
Regarding claim 14, Lee discloses the IC semiconductor device of claim 7, but fails to teach “wherein the top surface of the third subfield insulating layer has a concave shape”.
The ‘282 reference discloses wherein the top surface of the third subfield insulating layer has a concave shape (See the enlarged portion of Fig. 2 showing the concave shape).
Modifying the shape of “the third subfield insulating layer” by incorporating “a concave shape” (of the ‘282 reference) would arrive at the claimed shape configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success including the claimed shape configuration because it is a known resultant shape (i.e., an inherent shape configuration) produced by similar techniques on similar structures (Lee: Fig. 12 etching technique and [0066]: “etching process”; the ‘282 reference: Fig. 1 etching technique and pg. 3 of translation: “etching process”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed shape configuration because it is a known difference in shape produced by similar techniques on similar structures. MPEP 2144.04 (IV)(B); MPEP 2112 (III).
Claims 15, 17, and 20 are rejected under 35 U.S.C. 103 as being obvious over Lee, in view of “the ‘282 reference”.
The applied reference (Lee) has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Regarding independent claim 15, Lee discloses an integrated circuit (IC) semiconductor device (Fig. 7) comprising:
field insulating layers (110/120/115) buried in field trenches (TR2/TR1) disposed apart from each other inside a substrate (100/ACT/Fins, See annotated figure);
active regions (ACT) defined by the field insulating layers; and
active fins (Fins) disposed on the active regions and protruding (“protruding” in the DR4 direction) from surfaces of the field insulating layers,
wherein the field insulating layers comprise a first field insulating layer (110/120) having a first width (See annotated figure) and a second field insulating layer having a second width (See annotated figure) that is less than the first width (“less than” is shown in annotated Fig. 1, where W2 is only between adjacent 10, while W1 includes this same distance twice as well as the distance overlapping another 10),
wherein the first field insulating layer comprises a first subfield insulating layer (110) having a third width (See annotated figure) and a second subfield insulating layer (120) having a fourth width (See annotated figure) that is larger than the third width (“larger than” is based on the amount of overlap of these layers),
wherein a top surface (110a) of the first subfield insulating layer is disposed at a level (DR4 “level”) lower than a level (DR4 “level”) of a top surface (120a) of the second subfield insulating layer,
wherein the second field insulating layer comprises a single third subfield insulating layer (115),
wherein a top surface (115a) of the single third subfield insulating layer is disposed at a level (DR4 “level”) lower than the level of the top surface of the first subfield insulating layer,
wherein the top surface of the first subfield insulating layer and the top surface of the second subfield insulating layer have concave shapes,
wherein a single layer (GI) covers top portions and side walls of the active fins, and on the field insulating layers,
wherein the single layer is a gate insulating layer ([0042]: “gate dielectric layer”),
wherein protective patterns (Fig. 4: 210) are further formed on (indirectly “on”) both sidewalls of the second field insulating layer that is in contact with the active regions,
wherein the protective patterns are in direct contact with the active regions (Fig. 4 shows “direct contact” of 210 with ACT),
wherein a gate electrode (Fig. 7: WL) is further formed on the gate insulating layer, and
wherein a second area (See annotated figure) of portions of the active fins facing the gate electrode (“facing” in the DR2 direction) over the second field insulating layer is larger (“larger” based on the DR4 overlap. Note: this interpretation is consistent with Applicant’s disclosure: Fig. 11B: 138/F2 overlap areas, and Applicant’s remarks entered 8/31/2026: pg. 11) than a first area (See annotated figure) of other portions of the active fins facing the gate electrode (“facing” in the DR2 direction) over the first field insulating layer.
Lee fails to teach “wherein the top surface of the first subfield insulating layer and the top surface of the second subfield insulating layer have concave shapes”.
The ‘282 reference discloses wherein the top surface of the first subfield insulating layer (See the enlarged portion of Fig. 2 showing the concave shape) and the top surface of the second subfield insulating layer have concave shapes (See Fig. 4 showing the concave shape wrapped around gate electrode 130).
Modifying the shape of “the first subfield insulating layer” and “the second subfield insulating layer” by incorporating “concave shapes” (of the ‘282 reference) would arrive at the claimed shape configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success including the claimed shape configuration because it is a known resultant shape (i.e., an inherent shape configuration) produced by similar techniques on similar structures (Lee: Fig. 12 etching technique and [0066]: “etching process”; the ‘282 reference: Fig. 1 etching technique and pg. 3 of translation: “etching process”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed shape configuration because it is a known difference in shape produced by similar techniques on similar structures. MPEP 2144.04 (IV)(B); MPEP 2112 (III).
Regarding claim 17, Lee in view of the ‘282 reference discloses the IC semiconductor device of claim 15 (‘the 282 reference: Fig. 2), wherein the top surface of the single third subfield insulating layer has a concave shape (See the enlarged portion of Fig. 2 showing the concave shape).
Regarding claim 20, Lee in view of the ‘282 reference discloses the IC semiconductor device of claim 15 (Lee: Fig. 7), wherein the active regions are a same body as the active fins (these structures as cited are integrally formed as “a same body” based on not separation/distinct delineation among these features), and the active fins are formed by recess-etching upper portions of the field insulating layers (This product-by-process feature is shown in the method step of Fig. 12. MPEP 2113).
Response to Arguments
Applicant's arguments filed 8/31/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claim 15 that “the work function layer…is not formed on both sidewalls of the second field insulating layer that is in contact with the active regions” and “the ‘282 reference fails to disclose or teach the above elements of claim 15”. Remarks at pg. 11.
Examiner’s reply:
Applicant’s arguments with respect to claim 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The examiner finds the new limitation overcoming the ‘282 reference as previously applied. However, the new ground of rejection raised in the instant Office action relies upon a newly found reference (Lee) as necessitated by the claim amendment. Additionally, the examiner finds the claim as written reasonably including structural configurations beyond the contended configuration of Applicant’s disclosure. MPEP 2111.
Applicant argues:
Applicant argues with respect to amended claims 1, 7, and 15 that “a second area…larger than a first area…the ‘282 reference fails to disclose or teach the above elements”. Remarks at pg. 11.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 1, 7, and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The examiner finds the new limitation overcoming the ‘282 reference as previously applied. However, the new ground of rejection raised in the instant Office action relies upon a newly found reference (Lee) as necessitated by the claim amendment.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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