DETAILED ACTION
Status of Claims
As of the amendment filed 1/21/26, no claims have been added, canceled, or amended. Therefore, claims 1-19 remain pending, with claims 1, 10, and 16 being independent.
Response to Arguments
Applicant's arguments filed 1/21/26 have been fully considered but they are not persuasive. Applicant makes the following arguments:
“Applicants point out that reference 114 is an interconnect structure (Chen paragraph 20) which includes a dielectric layer 114a. As such, reference 114 fails to meet the limitation for a front metal layer.” (p. 7, 3rd para.).
“To meet the claimed insulator layer, the Examiner points to Chen Figure 1A and reference 110. Applicants point out that reference 110 is a semiconductor substrate (Chen paragraph 18), and thus is clearly not an insulator layer.” (p. 7, 4th para.).
“To meet the claimed first region, the Examiner points to Chen Figure 1A and reference 102. To meet the claimed second region, the Examiner points to Chen Figure 1A and reference 101. Applicants point out that the region 101 does not include any metal portions of the interconnect structure 114, and thus the requirement of claim 1 for the front metal layer to include BOTH the first region and the second region is not met. (p. 7, 6th para.).
“Chen Figure 1B shows the formation of opening 142 in passivation 120 over pad 130a, but this opening is filled by the insulating layer 150 in Chen Figure 1C. There is no teaching in Chen for forming a contact layer for electrical wafer sorting probes in the opening 142.” (p. 8 1st para.)
“There is no teaching in Chen for partly removing the passivation layer 120 from over the line 130b in the second region.” *p. 8, 2nd para.)
As to argument a), “front metal layer” is claimed but no where is it claimed that this layer is made entirely of metal. In fact, Applicant’s invention is directed to a packaging/metallization means in an IC (“metal layer 10 comprising, for instance, a Cu damascene top metallization layer of an integrated circuit semiconductor product structure”, see p. 8, last paragraph of the specification). That is, Applicant’s metal layer is a metallization layer. Or at least it can reasonably be interpreted as a metallization layer. The Chen reference teaches that layer 114 is a metallization layer containing a metal 114b/c buried within a dielectric 114a ([0020]). It is very well-known in the art that metallization layers include a metal line/via buried within a dielectric layer. Furthermore, it is reasonable to interpret the instant front metal layer as a metallization layer. If Applicant would like the front metal layer 10 to be interpreted as a layer made of metal, then that should be claimed.
As to argument b), Examiner agrees that 110 is a substrate, however substrates have insulating layers. Otherwise, they would be short-circuiting everything if they were a slab of metal. Also, as stated above, Chen layer 114 is a metallization layer. That means the substrate below is some kind of active substrate and there would absolutely need to be at least one insulating layer therein.
As to argument c) Applicant does not claim that the second region must include metal portions, only that it is over the front metal layer. As discussed in argument a), the front metal layer can be broadly reasonably interpreted as a metallization layer. Thus, both regions 102 and 101 are over the front metal layer.
As to argument d), Chen teaches the passivation opening 142 is formed by fully removing the passivation layer (120 and 122) over the metal layer 114 in the first region 102 (fig. 1B). Subsequent to that, some other steps are performed (i.e. a dielectric 150 is filled in the passivation opening 142 (fig. 1C) and then a second opening 170 is formed over the first region 102 and though the dielectric 150 and in the passivation opening 142 (fig. 1G)). Then, a contact layer 172 is formed in the second opening 170, which is within the passivation opening 142 (fig. 1H). Thus, the limitation is met. The contact layer IS formed withing the passivation opening, just later on after some intervening steps have been performed.
As to argument e), Examiner never stated or implied that line 130b is in the second region. Figure 1D very clearly removes passivation layer 120 and 122 over the second region 101.
The Examiner believes to have responded to all arguments. The prior art rejection is maintained and is reproduced in its entirety below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 10-13, 16, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (US 2021/0375721).
As to claims 1, 10, 11, 16, and 17, Chen teaches a method (figs. 1A-1K) and device formed by said method, comprising: providing a semiconductor chip (100) comprising a front metal layer (114, [0020], fig. 1A) over an insulator layer (110, [0018]), wherein the front metal layer includes a first region (102) and a second region (101, [0019]), and wherein a surface passivation (120 and 122) extends over the front metal layer (114, [0025]); fully removing the surface passivation (120 and 122) from over the front metal layer (114) at the first region (102) to form a first passivation opening (142) exposing an upper surface of the front metal layer at the first region (fig. 1B, [0026], 120 and 122 is removed above 102 where 134 is located), without fully removing the surface passivation from over the front metal layer at the second region (101, fig. 1b); forming a contact layer (172) for electrical wafer sorting probes over the front metal layer (114) in the passivation opening at the first region (102, fig. 1H, [0032]); and partly removing the surface passivation (120 and 122) from over the front metal layer (114) at the second region (101) to form a second passivation opening (140) which does not expose the front metal layer at the second region Fig. 1B, layer 120 still remains), wherein the second region (101) having the surface passivation partly removed defines, with the second passivation opening, a location for a growth region for growing electrically conductive material over the at least one second region of the front metal layer (via 154, [0029] – [0030], seed layer can be deposited and growth of copper interconnect occurs).
As to claim 2, Chen further teaches the first region and the second region are provided at mutually insulated portions of the front metal layer. (114a, [0020]).
As to claim 3, Chen further teaches the first region and the second region are provided at mutually short-circuited portions of the front metal layer ([0032], fig. 1H).
As to claims 4 and 12, Chen further teaches the surface passivation (120 and 122) comprises a protective layer (122) for covering the upper surface of said front metal layer and: fully removing the surface passivation comprises removing the protective layer (122) from over the front metal layer at the first region (102); and partly removing comprises leaving the protective layer (120) on the upper surface of the front Damascene metal layer at the second region (101, fig. 1B, [0022], [0025], and [0026]).
As to claim 5, Chen further teaches fully removing a portion of the protective layer (102 and 122) from over the second region (101) to form a third passivation opening (152, fig. 1D, [0028]); and growing electrically conductive material in said third passivation opening on said front metal layer at the second region (via 154, [0029] – [0030], seed layer can be deposited and growth of copper interconnect occurs).
As to claims 6 and 13, Chen further teaches the front metal layer (114) comprises copper ([0020]) and wherein growing electrically conductive material comprises growing copper in said third passivation opening on said front metal layer ([0029]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-9, 14, 15, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Applicant’s Admitted Prior Art (herein “AAPA”, pages 5 and 6 of the instant specification)
As to claims 7, 14, and 18, Chen does not teach forming a laser direct structuring insulating layer covering the surface passivation and covering the protective layer at the second region; activating the laser direct structuring insulating layer with a via opening extending though the laser direct structuring insulating layer and through the protective layer at the second region to reach the upper surface of the front metal layer at the second region; and growing electrically conductive material in said via opening to form an interconnect.
However, AAPA teaches LDS/DCI processing with these very same steps, and that they are standard in the industry (see pages 5 and 6). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to form the metallization layers as taught by AAPA so as to use an industrially tested and accepted method for forming a BEOL structure.
As to claims 8, 9, 15, and 19, Chen does not explicitly teach these limitations, however using laser ablation to form a via opening and using a damascene method to form a metal layer are known in the art and would have been obvious so as to use an industrially tested and accepted method for forming a BEOL structure.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any response to this Office Action should be faxed to (571) 273-8300 or mailed to:
Commissioner for Patents
P.O. Box 1450
Alexandria, VA 22313-1450
Hand-Delivered responses should be brought to:
Customer Service Window
Randolph Building
401 Dulany Street
Alexandria, VA 22313
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KAREN KUSUMAKAR/
Primary Examiner, Art Unit 2897
2/3/26