DETAILED ACTION
This action is responsive to communication filed 01/13/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II in the reply filed on 01/13/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 07/21/2023 and 05/12/2024 are acknowledged. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 18-25 and 28-31 are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US 20170062496 A1) in view of Jeon (US 20230197754 A1).
Regarding claim 18, Lai et al. (see, e.g., FIGS. 3 and 7 and annotated FIG. 14A below) teaches a method for forming an image sensor (100), comprising: forming a plurality of photodiode doping regions (Fig. 7: 104) in and on a front side (102A) of a substrate (Fig. 7: 102); forming deep isolation trenches (Fig. 7: 122) from a back side (Fig. 7: 102B) of the substrate, wherein the deep isolation trenches separate the plurality of photodiode doping regions; depositing a hole accumulation layer (Fig. 7: 132) on sidewalls of the deep isolation trenches; depositing a first isolation layer (Fig. 10: 140) on the hole accumulation layer, wherein the first isolation layer has a first thickness (see annotated FIG. 14A below: “T1”); depositing a first filling material (Fig. 12: 142) on the first isolation layer in the deep isolation trenches; and depositing a second isolation layer (Fig. 14A: 146) on the first isolation layer and exposed surfaces of the first filling material, wherein the second isolation layer has a second thickness (see annotated FIG. 14A below: “T2”) greater than the first thickness.
However, Lai et al. fails to teach that the first filling material encloses an air gap therein.
Jeon (see, e.g., FIG. 5) teaches that the first filling material (166) encloses an air gap (AG) therein for the purpose of reducing parasitic capacitance in the isolation layers (paragraph [0057]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the method of forming of air gaps as described by Jeon to the method of forming an image sensor as described by Lai et al. for the purpose of reducing parasitic capacitance in the isolation layers (paragraph [0057]).
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Regarding claim 19, Lai et al. (see, e.g., FIGS. 12 and 13A) teaches the method of claim 18, further comprising: after depositing the first filling material, removing a portion of the first filling material until the first isolation layer is exposed (paragraph [0032]).
Regarding claim 20, Lai et al. (see, e.g., FIG. 15) teaches the method of claim 18, further comprising: depositing a second filling material (148 and 150) on the second isolation layer, wherein the first and second filling materials comprise the same material (paragraph [0032]: “142B may comprise tungsten” and paragraph [0035]: “148 may comprise tungsten”).
Regarding claim 21, Lai et al. (see, e.g., FIGS. 3 and 7 and annotated FIG. 14A above) teaches a method for forming an image sensor (Fig. 14A: 100), comprising: forming a plurality of photodiode doping regions (Fig. 3: 104) in and on a front side (Fig. 3: 102A) of a semiconductor substrate (Fig. 3: 102); thinning the semiconductor substrate from a back side (Fig. 3: 102B) opposite the front side (paragraph [0014]); forming deep isolation trenches (Fig. 3: 122) from the back side of the semiconductor substrate, the deep isolation trenches laterally separating the plurality of photodiode doping regions; depositing a hole accumulation layer (Fig. 7: 132) on sidewalls and a bottom of the deep isolation trenches; depositing a first isolation layer (Fig. 14A: 140) on the hole accumulation layer, the first isolation layer having a first thickness (see annotated FIG. 14A above: “T1”); depositing a first filling material (Fig. 14A: 142) on the first isolation layer to fill the deep isolation trenches; and depositing a second isolation layer (Fig. 14A: 146) on the first isolation layer and exposed surfaces of the first filling material, the second isolation layer having a second thickness (see annotated FIG. 14A above: “T2”) greater than the first thickness.
However, Lai et al. fails to teach that the first filling material encloses an air gap within the deep isolation trenches.
Jeon (see, e.g., FIG. 5) teaches that the first filling material (166) encloses an air gap (AG) therein for the purpose of reducing parasitic capacitance in the isolation layers (paragraph [0057]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the method of forming of air gaps as described by Jeon to the method of forming an image sensor as described by Lai et al. for the purpose of reducing parasitic capacitance in the isolation layers (paragraph [0057]).
Regarding claim 22, Lai et al. (see, e.g., FIGS. 12 and 13A) teaches the method of claim 21, further comprising: after depositing the first filling material, removing a portion of the first filling material until the first isolation layer is exposed (paragraph [0032]).
Regarding claim 23, Lai et al. (see, e.g., FIG. 15) teaches the method of claim 21, further comprising: depositing a second filling material (148 and 150) on the second isolation layer, wherein the first and second filling materials comprise the same material (paragraph [0032]: “142B may comprise tungsten” and paragraph [0035]: “148 may comprise tungsten”).
Regarding claim 24, Lai et al. (see, e.g., FIG. 7) teaches the method of claim 21, wherein the hole accumulation layer comprises a high-K dielectric material selected from the group consisting of Al203, HfO2, ZrO2, Y203, and combinations thereof (paragraph [0023]).
Regarding claim 25, Lai et al. (see, e.g., FIG. 14A) teaches the method of claim 21, wherein the first isolation layer comprises a dielectric material (paragraph [0031]: “silicon oxide”).
However, Lai et al. fails to teach that the first isolation layer comprises a high-K dielectric material.
Jeon (see, e.g., FIG. 5) teaches that the first isolation layer (162) comprises a high-K dielectric material (paragraph [0055]: “162 may include silicon oxide or a high-k dielectric material”) and shows that both silicon oxide and high-k dielectric materials are known to serve the same purpose as an isolation liner.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the silicon oxide isolation layer as described by Lai et al. with a high-k isolation layer as described by Jeon as a simple substitution of known elements to achieve the same results.
Regarding claim 28, Lai et al. teaches the method of claim 21.
However, Lai et al fails to teach that the air gap is fully enclosed within the first filling material without extending to a back surface of the semiconductor substrate.
Jeon (see, e.g., FIG. 5) teaches that the air gap (AG) is fully enclosed within the first filling material (166) without extending to a back surface (110F2) of the semiconductor substrate.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the fully enclosed air gaps as described by Jeon to the method of forming an image sensor as describe by Lai et al. for the purpose of preventing further layers from making contact with the air gap (paragraph [0108]).
Regarding claim 29, Lai et al. teaches the method of claim 21.
However, Lai et al. fails to teach that the first isolation layer and the first filling material comprises a same material.
Lai et al. teaches that the first isolation layer comprises silicon oxide (paragraph [0031]).
Jeon (see, e.g., FIG. 5) teaches that the first filling material (166) comprises silicon oxide for the purpose of being a better material for forming the enclosed air gap (paragraphs [0103] and [0104]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the first filling material as described by Lai et al. with the first filling material as described by Jeon, thereby causing the first isolation layer and first filling material to comprise the same material, for the purpose of being a better material for forming the enclosed air gap (paragraphs [0103] and [0104]).
Regarding claim 30, Lai et al. (see, e.g., FIG. 14A) teaches the method of claim 21, wherein the first isolation layer and the second isolation layer comprise a same material (paragraph [0031]: “140 comprises an oxide such as silicon oxide” and paragraph [0033]: “146 comprises silicon oxide”).
Regarding claim 31, Lai et al. teaches the method of claim 21, wherein the first isolation layer and the second isolation layer comprise dielectric materials (paragraph [0031]: “140 comprises an oxide such as silicon oxide” and paragraph [0033]: “146 comprises silicon oxide”).
However, Lai et al. fails to teach that the first isolation layer and the second isolation layer comprise different dielectric materials.
Jeon (see, e.g., FIG. 5) teaches that the first isolation layer (162) comprises either silicon oxide or a high-k dielectric material (paragraph [0055]) and shows that both silicon oxide and high-k dielectric materials are known to serve the same purpose as an isolation liner.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the silicon oxide isolation layer as described by Lai et al. with a high-k isolation layer as described by Jeon, thereby causing the first isolation layer and second isolation layer to comprise different dielectric materials, as a simple substitution of known elements to achieve the same results.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US 20170062496 A1) in view of Jeon (US 20230197754 A1) as applied to claim 21 above, and further in view of Qiao (US 12051615 B2).
Regarding claim 26, Lai et al. teaches the method of claim 21.
However, Lai et al fails to teach that the first isolation layer has a thickness that gradually decreases from an opening of the deep isolation trenches toward a bottom of the deep isolation trenches.
Qiao (see, e.g. FIG. 6) teaches that the first isolation layer (20) has a thickness that gradually decreases from an opening of the deep isolation trenches toward a bottom of the deep isolation trenches (column 7, lines 64-67) for the purpose of ensuring the isolation layer can be oxidized without oxidizing the substrate (column 8, lines 8-17).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include that the first isolation layer has a thickness that gradually decreases from an opening of the deep isolation trenches toward a bottom of the deep isolation trenches as described by Qiao to the method of forming an image sensor as described by Lai et al. for the purpose of ensuring the isolation layer can be oxidized without oxidizing the substrate (column 8, lines 8-17).
Claims 21 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20230197754 A1) in view of Lai et al. (US 20170062496 A1).
Regarding claim 21, Jeon (see, e.g., FIGS. 4, 10, and 11, and annotated FIG. 5 below) teaches a method for forming an image sensor (Fig. 4: 100), comprising: forming a plurality of photodiode doping regions (Fig. 10: 120) in and on a front side (Fig. 10: 110F1) of a semiconductor substrate (Fig. 10: 110); thinning the semiconductor substrate (paragraph [0092]) from a back side (Fig. 11: 110F2) opposite the front side; forming deep isolation trenches (Fig. 5: 160) from the back side of the semiconductor substrate, the deep isolation trenches laterally separating the plurality of photodiode doping regions; depositing a first isolation layer (Fig. 5: 162), the first isolation layer having a first thickness (see annotated FIG. 5 below: “first thickness”); depositing a first filling material (Fig. 5: 166) on the first isolation layer to fill the deep isolation trenches, wherein the first filling material encloses an air gap (Fig. 5: AG) within the deep isolation trenches; and depositing a second isolation layer (Fig. 5: 181) on the first isolation layer and exposed surfaces of the first filling material, the second isolation layer having a second thickness (see annotated FIG. 5 below: “second thickness”) greater than the first thickness.
However, Jeon fails to teach depositing a hole accumulation layer on sidewalls and a bottom of the deep isolation trenches on which the first isolation layer is deposited.
Lai et al. (see, e.g., FIGS. 7 and 10) teaches depositing a hole accumulation layer (Fig. 7: 132) on sidewalls and a bottom of the deep isolation trenches (Fig. 7: 122) on which the first isolation layer (Fig. 10: 140) is deposited for the purpose of preventing pixel degradation (paragraph [0023]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the deposition of a hole accumulation layer as described by Lai et al. to the method of forming an image sensing device as described by Jeon for the purpose of preventing pixel degradation (paragraph [0023]).
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Regarding claim 27, Jeon (see, e.g., annotated FIG. 5 above) teaches the method of claim 21.
However, Jeon fails to explicitly teach the air gap has a height that is between about 55% and about 90% of a depth of the deep isolation trenches. Jeon, on the other hand, does teach that the height of the air gap appears to be about 50% in proportion to the height of the trench as seen in annotated Fig. 5 above.
However, differences in height will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such height difference is critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph) of the height of the air gap in proportion to the trench height, it would have been obvious to one of ordinary skill in the art to modify the height of the gap in the device of Jeon through routine experimentation.
Criticality
The specification contains no disclosure of either the critical nature of the claimed height of the gap or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claims 32-37 are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US 20170062496 A1) in view of Jeon (US 20230197754 A1), and further in view of Qiao (US 12051615 B2).
Regarding claim 32, Lai et al. (see, e.g., FIGS. 3 and 7 and annotated FIG. 14A above) teaches a method for forming an image sensor (Fig. 14A: 100), comprising: forming photodiode regions (Fig. 3: 104) in a semiconductor substrate (Fig. 3: 102); forming deep trench isolation structures (Fig. 3: 122) from a backside (Fig. 3: 102B) of the semiconductor substrate to separate adjacent photodiode regions; conformally forming a hole accumulation layer (Fig. 7: 132) along sidewalls of the deep trench isolation structures; forming a first isolation layer (Fig. 14A: 140) on the hole accumulation layer; depositing a filling material (Fig. 14A: 142) within the deep trench isolation structures; and forming an isolation cap (Fig. 14A: 146) over the dielectric filling material by depositing a second isolation (Fig. 14A: 146) layer thicker than the first isolation layer (see annotated FIG. 14A above: “T2” greater than “T1”).
However, Lai et al. fails to teach that the first isolation layer has a thickness that decreases along a depth direction of the deep trench isolation structures, and depositing a dielectric filling material within the deep trench isolation structures such that an enclosed air gap is formed within the dielectric filling material.
Jeon (see, e.g., FIG. 5) teaches depositing a dielectric (paragraph [0103]: “silicon oxide”) filling material (166) within the deep trench isolation structures such that an enclosed air gap (AG) is formed within the dielectric filling material.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the method of depositing a dielectric filling material having enclosed air gaps as described by Jeon to the method of forming an image sensor as described by Lai et al. for the purpose of reducing parasitic capacitance in the isolation layers (paragraph [0057]) and being a better material for forming the enclosed air gap (paragraphs [0103] and [0104]).
However, Lai et al. in view of Jeon fails to teach that the first isolation layer has a thickness that decreases along a depth direction of the deep trench isolation structures.
Qiao (see, e.g. FIG. 6) teaches forming a first isolation layer (20) on the hole accumulation layer with a thickness that decreases along a depth direction of the deep trench isolation structures (column 7, lines 64-67) for the purpose of ensuring the isolation layer can be oxidized without oxidizing the substrate (column 8, lines 8-17).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include that the first isolation layer has a thickness that gradually decreases from an opening of the deep isolation trenches toward a bottom of the deep isolation trenches as described by Qiao to the method of forming an image sensor as described by Lai et al. in view of Jeon for the purpose of ensuring the isolation layer can be oxidized without oxidizing the substrate (column 8, lines 8-17).
Regarding claim 33, Lai et al. (see, e.g., FIGS. 12 and 13A) teaches the method of claim 32, further comprising: planarizing the dielectric filling material prior to forming the isolation cap (paragraph [0032]).
Regarding claim 34, Lai et al. (see, e.g., annotated FIG. 14A above) teaches the method of claim 32, wherein forming the deep trench isolation structures comprises forming trenches having a narrower top critical dimension (see annotated FIG. 14A above: “Top Width”) and a wider mid-depth dimension (see annotated FIG. 14A above: “Mid Width”).
Regarding claim 35, Lai et al. (see, e.g., FIG. 1) teaches the method of claim 32, wherein the deep trench isolation structures are formed after bonding the semiconductor substrate (102) to a logic die (200 and paragraph [0009]).
Regarding claim 36, Lai et al. (see, e.g., FIG. 16) teaches the method of claim 32, further comprising: forming color filters (152) over the dielectric filling material.
Regarding claim 37, Lai et al. (see, e.g., annotated FIG. 14A above) teaches the method of claim 36, wherein the second isolation layer extends across an entire width of a top surface (see annotated FIG. 14A above: “Top Width”) of the dielectric filling material.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AIDAN D BANKLER whose telephone number is (571)272-0883. The examiner can normally be reached Monday through Thursday 7:00-5:00.
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/AIDAN D BANKLER/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 March 24, 2026