Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Specification
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9, 17-18, 20-22, 25-26, 29, 32 and 47 are rejected under 35 U.S.C. 103 as being unpatentable over Ko et al. (US 2021/0143008 A1) in view of Kim et al. (US 2019/0229071 A1) and Park et al. (US 2018/0033779 A1).
Regarding independent claim 1: Ko teaches (e.g., Figs. 1-2) a semiconductor package comprising:
a substrate ([0003] and [0036]-[0037]: 100) comprising a substrate pad ([0038]: 130),
the substrate having a first trench ([0038]-[0040]: left side trench: 110) on a top surface of the substrate (100); and
a chip stack ([0036]-[0037]: 200) on the substrate, the chip stack comprising a plurality of semiconductor chips ([0039] and [0041]-[0043]: 210;220;230),
wherein a chip pad ([0039] and [0041]-[0043]: 211) of a first semiconductor chip ([0039] and [0041]-[0043]: 210), which is a lowermost one of the plurality of semiconductor chips ([0039] and [0041]-[0043]: 210;220;230), is bonded to the substrate pad (130) of the substrate (100), and
wherein the first trench overlaps with a corner of the first semiconductor chip ([0038]-[0039] and [0050]: the first trench 110 overlaps with a corner of the first semiconductor chip 210), when viewed in plan view (Fig. 2 shows plan view; [0048] and [0050]).
Ko does not expressly teach
a substrate comprising a plurality of vias;
wherein the chip pad and the substrate pad are formed of a same metallic material.
the first trench is provided in the substrate only at the corner of the first semiconductor chip, when viewed in plan view.
Kim teaches (e.g., Fig. 2) a method comprising a chip pad ([0019], [0028] and [0030]: 115) and a substrate pad ([0024]: 142);
Kim further teaches a substrate ([0023]: 112) comprising a plurality of vias ([0025]: 114);
wherein the chip pad ([0028] and [0030]: 142) and the substrate pad ([0024]: 115) are formed of a same metallic material ([0019], [0024], [0028] and [0030]: selecting copper as same material).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the semiconductor package of Ko, the substrate comprising a plurality of vias; wherein the chip pad and the substrate pad are formed of a same metallic material, as taught by Kim, for the benefits of increasing the integrated circuit density and thus increasing the device functionalities by combining a plurality of stacked packages, in addition, using the same material for the pads contributes to reducing the contact resistance of the interconnection structures.
Park teaches (e.g., Figs. 9-10; [0043]) a semiconductor package comprising a first trench ([0046]-[0047]: trench includes 25a and 2a), a first chip ([0050]: 20) and a substrate ([0047]: 1);
Park further teaches that the first trench ([0046]-[0047]: trench includes 25a and 2a) is provided in the substrate only at the corner (Fig. 10; ([0046]-[0047]: trench including 25a and 2a is provided in the substrate only at the corner) of the first semiconductor chip (20), when viewed in plan view (as shown in Fig. 9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the semiconductor package of Ko as modified by Kim, the first trench being provided in the substrate only at the corner of the first semiconductor chip, when viewed in plan view, as taught by Park, for the benefits of increasing the contrast with background of the substrate, thus, improving alignment accuracy during bonding process or following steps requiring more visible alignment marks.
Regarding claim 2: Ko, Kim and park teach the claim imitation of the semiconductor package of claim 1, on which this claim depends,
wherein the corner of the first semiconductor chip (Ko: 210) is vertically spaced apart from the substrate (Ko: Fig.2 and Fig. 1: the sides or the corner of the semiconductor chip 210 is spaced apart from the sides of the substrate 110).
Regarding claim 3: Ko, Kim and park teach the claim imitation of the semiconductor package of claim 1, on which this claim depends,
wherein, when viewed in plan view, a first portion of the first trench overlaps with the first semiconductor chip (Ko: Fig. 2; [0038]-[0039] and [0050]: the first portion of the first trench 110 overlaps with the first semiconductor chip 210), and
a second portion of the first trench other than the first portion is located outside a side surface of the first semiconductor chip (Ko: Figs. 1-2; [0038]-[0039] and [0050]: the second portion of the first trench 110 other than the first portion is located outside a side surface of the first semiconductor chip 210).
Regarding claim 4: Ko, Kim and park teach the claim imitation of the semiconductor package of claim 1, on which this claim depends,
wherein the first trench has rectangular cross shape, when viewed in plan view (Ko: Fig. 2; #110is-110os: left side trench 110).
Regarding claim 5: Ko, Kim and park teach the claim imitation of the semiconductor package of claim 1, on which this claim depends,
wherein: the first semiconductor chip has a first side surface and a second side surface adjacent to the first side surface, the corner of the first semiconductor chip is a corner at which the first side surface and the second side surface meet (Ko: Fig. 2; [0038]-[0039] and [0050]: the corner of the first semiconductor chip 210 is a corner at which the first side surface and the second side surface meet the sides 110is-110os and shorter sides of rectangular left side and right side of trench 110), and
the first trench is located below the corner and extends along the first side surface and the second side surface (Ko: Fig. 2; [0038]-[0039] and [0050]: #110is-110os and other sides of 110 are located below the corner and extends along the first side surface and the second side surface).
Regarding claim 6: Ko and Kim teach the claim imitation of the semiconductor package of claim 5, on which this claim depends,
wherein the first trench surrounds the first semiconductor chip, when viewed in plan view (Ko: Fig. 2; [0038]-[0039] and [0050]: #110is-110os: the first trench, left side 110 surrounds the first semiconductor chip, when viewed in plan view; see [0065], [0077]-[0080]).
Although, in the embodiment of Fig. 1-2, Ko does not appear to disclose that the first trench surrounds the first semiconductor chip, when viewed in plan view,
in another embodiment,
Ko teaches (e.g., Figs. 24-26) a semiconductor device comprising a first trench (Figs. 24-26: [0065], [0077]-[0080]);
Ko further teaches that the first trench surrounds the first semiconductor chip, when viewed in plan view (Figs. 24-26: [0065], [0077]-[0080]).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to provide a first trench such that the first trench surrounds the first semiconductor chip, when viewed in plan view, as taught by Ko, for the benefits of supporting the chip stacks from all sides and thus avoid device damage due to uneven pressure.
Regarding claim 7: Ko, Kim and park teach the claim imitation of the semiconductor package of claim 1, on which this claim depends,
wherein the substrate further comprises a second trench (Ko: Figs. 1-2: [0038]-[0040]: right side trench 110 defined by 110is and 110os) is in the top surface of the substrate,
the second trench (Ko: Figs. 1-2: [0038]-[0040]: right side trench 110 defined by 110is and 110os) being spaced apart from the first trench (Ko: Figs. 1-2: [0038]-[0040]: left side trench 110 defined by 110is and 110os),
wherein a first side surface of the first semiconductor chip (Ko: 210) is in contact with the corner (Ko: [0038]-[0040]),
wherein the second trench extends along the first side surface of the first semiconductor chip (Ko: Fig. 2; [0038]-[0040]: the second trench extends along the first side surface of the first semiconductor chip 210), and
wherein the second trench overlaps the first side surface of the first semiconductor chip, when viewed in plan view (Ko: plan view shown in Fig. 2; [0038]-[0040]: the second trench overlaps the first side surface of the first semiconductor chip).
Regarding claim 9: Ko, Kim and park teach the claim imitation of the semiconductor package of claim 1, on which this claim depends,
wherein the substrate further comprises a third trench (Ko: Fig. 2; [0048]-[0050]: upper trench 110) in the top surface of the substrate, the third trench being spaced apart from the first trench Ko: Fig. 2; [0048]-[0050]: left side trench 110),
wherein the third trench (Ko: upper trench 110) is adjacent to the corner.
Although, in the embodiment of Fig. 1-2, Ko does not appear to disclose that an entirety of the third trench overlaps with the first semiconductor chip, when viewed in plan view,
in another embodiment,
Ko teaches (e.g., Figs. 14-15) a semiconductor device comprising a third trench (Figs. 14-15: [0066]-[0067]: 113);
Ko further teaches that an entirety of the third trench overlaps with the first semiconductor chip, when viewed in plan view ([0066]-[0067]: the third trench 113 overlaps with the first semiconductor chip area 150 and thus with the 210, [0041]).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to provide a first trench such that the entirety of the third trench overlaps with the first semiconductor chip, when viewed in plan view, as taught by Ko, for the benefits of shielding the trench from external unwanted foreign particles and reducing the stress of the upper chip stack edges.
Regarding claim 17: Ko, Kim and park teach the claim imitation of the semiconductor package of claim 1, on which this claim depends,
further comprising a mold layer (Ko: [0039] and [0047]: 400) on the substrate that encloses the chip stack (Ko: [0039]: 200),
Ko does not expressly teach in Figs. 1-2 that the mold layer extends into the first trench.
However, Ko teaches (e.g., Fig. 5) that the mold layer (Ko: 200) extends into the first trench (Ko: 110).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Ko, a molding such that the mold layer extends into the first trench, as taught by the alternative embodiment of Ko, for the benefits of protecting the edges of the trench from foreign particles or moisture, and thus improve device reliability.
Regarding claim 18: Ko, Kim and park teach the claim imitation of the semiconductor package of claim 1, on which this claim depends,
wherein a bottom surface of the first semiconductor chip (Ko: 210) and a bottom surface of the chip pad (Ko: 211) are substantially flat and are substantially coplanar with each other (Ko: Fig.1; [0039] and [0043]),
wherein the top surface of the substrate (Ko: 100) and a top surface of the substrate pad (Ko: 130) are substantially flat and are substantially coplanar with each other (Ko: Fig. 1; [0038]-[0039]), and
wherein the bottom surface of the first semiconductor chip (Ko: 210) is in contact with the top surface of the substrate (Ko: 100).
Regarding independent claim 20: Ko teaches (e.g., Figs. 1-2) a semiconductor package comprising:
a buffer chip ([0003] and [0036]-[0037]: 100);
a first semiconductor chip ([0039] and [0041]-[0043]: 210) on the buffer chip,
a first pad ([0038]-[0039] and [0044]: 130) of the buffer chip being bonded to a second pad ([0039] and [0041]-[0043]: 211) of the first semiconductor chip (210),
a second semiconductor chip ([0039] and [0041]-[0043]: 220) on the first semiconductor chip (210),
a third pad ([0039] and [0041]-[0043]: 211) of the first semiconductor chip (210) being bonded to a fourth pad ([0039] and [0041]-[0043]: 211) of the second semiconductor chip (220), the third pad and the fourth pad being formed of a same metallic material ([0039] and [0041]-[0043]: both pads labeled 211; same designation indicates similar material or structure; per MPEP, it is not permissible to designate different structures or materials with the same element designation);
a mold layer ([0036]: 400) on the buffer chip that encloses the first semiconductor chip (210) and the second semiconductor chip (220); and
a buffering structure ([0036] and [0040]: 310) interposed between the buffer chip (100) and the first semiconductor chip (210),
wherein the buffering structure (310) overlaps with a corner of the first semiconductor chip (210), when viewed in plan view (Fig. 2 shows the plan view).
Ko does not expressly teach
the first pad and the second pad being formed of a same metallic material,
the first trench is provided in the substrate only at the corner of the first semiconductor chip, when viewed in plan view.
Kim teaches (e.g., Fig. 2) a method comprising a substrate ([0023]: 112), a first pad ([0019], [0028] and [0030]: 115) and a second pad ([0019], [0028] and [0030]: 142);
Kim further teaches that the first pad and the second pad are formed of a same metallic material ([0019], [0024], [0028] and [0030]: selecting copper as same material).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the semiconductor package of Ko, the first pad and the second pad being formed of a same metallic material, as taught by Kim, for the benefits of reducing the contact resistance of the interconnection structure.
Park teaches (e.g., Figs. 9-10; [0043]) a semiconductor package comprising a first trench ([0046]-[0047]: trench includes 25a and 2a), a first chip ([0050]: 20) and a substrate ([0047]: 1);
Park further teaches that the first trench ([0046]-[0047]: trench includes 25a and 2a) is provided in the substrate only at the corner (Fig. 10; ([0046]-[0047]: trench including 25a and 2a is provided in the substrate only at the corner) of the first semiconductor chip (20), when viewed in plan view (as shown in Fig. 9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the semiconductor package of Ko as modified by Kim, the first trench being provided in the substrate only at the corner of the first semiconductor chip, when viewed in plan view, as taught by Park, for the benefits of increasing the contrast with background of the substrate, thus, improving alignment accuracy during bonding process or following steps requiring more visible alignment marks.
Regarding claim 21: Ko, Kim and Park teach the claim imitation of the semiconductor package of claim 20, on which this claim depends,
wherein the buffering structure (Ko: 310) is buried in an upper portion of the buffer chip (Ko: 100) and is in contact with a bottom surface of the first semiconductor chip (Ko: 210).
Regarding claim 22: Ko, Kim and Park teach the claim imitation of the semiconductor package of claim 21, on which this claim depends,
wherein a top surface of the buffering structure (Ko: 310) is substantially flat and is substantially coplanar with a top surface of the buffer chip (Ko: 100).
Regarding claim 25: Ko, Kim and Park teach the claim imitation of the semiconductor package of claim 20, on which this claim depends,
wherein the buffer chip (Ko: 100) comprises a first trench (Ko: [0039]: left side trench 110) in a top surface of the buffer chip,
wherein the first trench (Ko: left side trench 110) overlaps with the corner of the first semiconductor chip (Ko: 210), when viewed in plan view (Ko: Fig. 2; [0048] and [0050]) and wherein the buffering structure (Ko: 310) is in the first trench (Ko: left side trench 110).
Ko as modified by Kim does not expressly teach that the first trench is provided in the buffer chip only at the corner of the first semiconductor chip, when viewed in plan view.
However, Park teaches (e.g., Figs. 9-10; [0043]) a semiconductor package comprising a first trench ([0046]-[0047]: trench includes 25a and 2a), a first chip ([0050]: 20) and a buffer semiconductor chip ([0047]: 1; note that in Applicant ‘s specification, “the base substrate may be referred to as a buffer semiconductor chip 100”; see [0032]:);
Park further teaches that the first trench ([0046]-[0047]: trench includes 25a and 2a) is provided in the buffer semiconductor chip only at the corner (Fig. 10; ([0046]-[0047]: trench including 25a and 2a is provided in the buffer semiconductor chip only at the corner) of the first semiconductor chip (20), when viewed in plan view (as shown in Fig. 9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the semiconductor package of Ko as modified by Kim, the first trench being provided in the buffer chip only at the corner of the first semiconductor chip, when viewed in plan view, as taught by Park, for the benefits of increasing the contrast with background of the substrate, thus, improving alignment accuracy during bonding process or following steps requiring more visible alignment marks.
Regarding claim 26: Ko, Kim and Park teach the claim imitation of the semiconductor package of claim 20, on which this claim depends,
wherein the corner of the first semiconductor chip (Ko: 210) is vertically spaced apart from the buffer chip (Ko: 100).
Regarding claim 29: Ko, Kim and Park teach the claim imitation of the semiconductor package of claim 28, on which this claim depends,
wherein the buffering structure (Ko: 310) is located at the same level as the first pad (Ko: buffering structure 310 and first pad 130 are at the same layer bottom layer level), and
wherein the buffering structure (Ko: 310) has substantially the same thickness as the first pad (Ko: first pad 130).
Regarding independent claim 32: Ko teaches (e.g., Figs. 1-2) a semiconductor package comprising:
a semiconductor substrate ([0003] and [0036]-[0037]: 100);
a plurality of semiconductor chips ([0036]-[0038]: 200) stacked on the semiconductor substrate (100); and
a mold layer ([0036], [0039] and [0045]: 400) on the semiconductor substrate that encloses the plurality of semiconductor chips (200),
wherein the semiconductor substrate (100) comprises:
a first trench ([0038]-[0040]: left side trench: 110) in a top surface of the semiconductor substrate (100); and
a first buffering structure ([0036] and [0039]-[0040]: 310) in the first trench,
wherein the first trench ([0038]-[0040]: left side trench: 110) overlaps with a corner of a lowermost one of the plurality of semiconductor chips (200), when viewed in plan view Fig. 2 shows plan view; [0048] and [0050]), and
wherein a rigidity of the first buffering structure is less than a rigidity of the semiconductor substrate ([0036]-[0040] and [0044]-[0045]: silicon substrate more rigid than a flowable adhesive layer).
Ko does not expressly teach
a substrate comprising a plurality of vias;
wherein the first trench is provided in the semiconductor substrate only at the corner of the lowermost one of the plurality of semiconductor chips, when viewed in plan view.
Kim teaches (e.g., Fig. 2) a method comprising a substrate ([0023]: 112);
Kim further teaches a substrate ([0023]: 112) comprising a plurality of vias ([0025]: 114);
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the semiconductor package of Ko, the substrate comprising a plurality of vias, as taught by Kim, for the benefits of increasing the integrated circuit density and thus increasing the device functionalities by combining a plurality of stacked packages.
Park teaches (e.g., Figs. 9-10; [0043]) a semiconductor package comprising a first trench ([0046]-[0047]: trench includes 25a and 2a), a first chip ([0050]: 20) and a substrate ([0047]: 1);
Park further teaches that the first trench ([0046]-[0047]: trench includes 25a and 2a) is provided in the substrate only at the corner (Fig. 10; ([0046]-[00`]: trench including 25a and 2a is provided in the substrate only at the corner) of the lowermost one of the plurality of semiconductor chips (20), when viewed in plan view (as shown in Fig. 9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the semiconductor package of Ko as modified by Kim, the first trench being provided in the semiconductor substrate only at the corner of the lowermost one of the plurality of semiconductor chips, when viewed in plan view, as taught by Park, for the benefits of increasing the contrast with background of the substrate, thus, improving alignment accuracy during bonding process or following steps requiring more visible alignment marks.
Regarding claim 47: Ko, Kim and park teach the claim imitation of the semiconductor package of claim 1, on which this claim depends,
Ko as modified by Kim and Park teaches
wherein the first trench (Park: [0046]-[0047]: trench includes 25a and 2a) is provided at each corner of the first semiconductor chip (park: 20), and overlaps each corner of the first semiconductor chip (20), when viewed in plan view (Park: as shown in Figs. 9-10).
Claims 12-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ko et al. (US 2021/0143008 A1) in view of Kim et al. (US 2019/0229071 A1) and Park et al. (US 2018/0033779 A1) as applied above and further in view of De Rochemont (US 2018/0358295 A1).
Regarding claim 12: Ko, Kim and Park teach the claim imitation of the semiconductor package of claim 1, on which this claim depends,
Ko as modified by Kim and Park teaches that the substrate further comprises a first buffering structure (Ko: [0039]: 110) in the first trench,
wherein the first buffering structure (Ko: [0040]: 310), and
wherein a top surface of the first buffering structure ([0045]: 205a) is substantially flat ([0045]: 205a is substantially flat) and is substantially coplanar with the top surface of the substrate (Park: Fig. 10; #1).
Ko as modified by Kim and Park does not expressly teach that the first buffering structure comprises a metallic material.
Note that Ko teaches that the first buffering structure is an adhesive or has adhesive properties ([Ko: 0040]: 310).
De Rochemont teaches (e.g., Figs. 3A-4I and 7A-7F) a semiconductor package comprising a substrate ([0052] and [0139] and [0142]: 601);
De Rochemont further teaches a first buffering structure comprising a metallic material ([0143]: the bonding layer 640 is a dielectric material like titanium oxide).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Ko as modified by Kim and Park, the first buffering structure comprising a metallic material, as taught by De Rochemont, for the benefits of further increase the contrast of the substrate edges for an improved accuracy during bonding process above the substrate.
Regarding claim 13: Ko, Kim, Park and De Rochemont teach the claim imitation of the semiconductor package of claim 12, on which this claim depends,
Ko as modified by Kim, Park and De Rochemont teaches that the first buffering structure (Ko: 310; corresponding to Park: 205a) is at the same level as the substrate pad (Park: 1), and
wherein the first buffering structure (Ko: 310) has substantially the same thickness as the substrate pad (Ko: 130).
Regarding claim 15: Ko, Kim, Park and De Rochemont teach the claim imitation of the semiconductor package of claim 12, on which this claim depends,
wherein the substrate further comprises a second buffering structure (Ko: [0045]: second buffering 310 on the side opposite the first trench, Fig. 2, upper portion) in the first trench,
wherein the second buffering structure comprises an insulating material (Ko: [0044]-[0045]: NCF; corresponding to De Rochemont: [0047]: 205a insulating material), and
wherein a rigidity of the second buffering structure is less than a rigidity of the substrate (Ko: insulating layer 310 has rigidity less than the rigidity of the substrate because the insulating layer is a flowable material, whereas the substrate is used as a support substrate).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5,7,9,12-13,15,17-18,20-22,25-26,29,32 and 47 have been considered but are moot because the new ground of rejection does not rely on any reference or combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument or of newly added limitation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812