Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 and 23-30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (Pub. No. US 2015/0228751 A1, herein Kim).
Regarding claim 1, Kim discloses a structure, comprising: a first vertically-oriented semiconductor pillar 15 having one or more sidewalls, and a top surface, the first vertically-oriented semiconductor pillar having a first width (Kim: Fig. 1 and paragraph [0024]); a first dielectric material 30-50 abutted to the one or more sidewalls of the first vertically-oriented semiconductor pillar (Kim: Fig. 1 and paragraphs [0024]-[0025]); a second vertically-oriented semiconductor pillar 15 having one or more sidewalls, and a top surface; a first conductive structure 80-90 having a first surface, and having a second width that is greater than the first width, the first conductive structure disposed such that a second portion of its first surface is in contact with the top surface of the first vertically-oriented semiconductor pillar; a second conductive structure 80-90 is disposed on the top surface of the second vertically-oriented semiconductor pillar 15 (Kim: Fig. 1 and paragraphs [0026], [0028]-[0029]); and a first dielectric plug 70 disposed between the first conductive structure and the second conductive structure (Kim: Fig. 1 and paragraph [0041]), wherein a first portion of the first surface of the first conductive structure extends laterally beyond the top surface of the first vertically-oriented semiconductor pillar, and the first portion of the first surface is disposed on the first dielectric material; and a top surface of the first dielectric plug is coplanar with a top surface of the first conductive structure (Kim: Fig. 1 and paragraph [0027]).
Regarding claim 2, Kim discloses the structure of claim 1, wherein the first vertically-oriented semiconductor pillar is integral with a semiconductor substrate (Kim: Fig. 1 and paragraph [0024]).
Regarding claim 3, Kim discloses the structure of claim 2, wherein the second vertically-oriented semiconductor pillar 15 is abutted on at least one of its one or more sidewalls by at least the first dielectric material 30-50, wherein a first portion of the second conductive structure 80-90 is disposed on the top surface of the second vertically-oriented semiconductor pillar 15, and is in contact therewith (Kim: Fig. 1 and paragraphs [0026]-[0029]), wherein the first conductive structure comprises a first metal silicide structure, and the second conductive structure comprises a second metal silicide structure (Kim: Fig. 1 and paragraphs [0026], [0049]).
Regarding claim 4, Kim discloses the structure of claim 3, wherein the first dielectric plug 70 is disposed between the first metal silicide structure and the second metal silicide structure (Kim: Fig. 1 and paragraph [0041]).
Regarding claim 5, Kim inherently discloses the structure of claim 4, wherein the first dielectric plug comprises silicon nitride (Kim: Fig. 1 and paragraphs [0039], [0041]).
Regarding claim 6, Kim inherently discloses the structure of claim 3, wherein the first metal silicide structure has an area (The term “an area” is a broad term and is considered to be any part of the metal silicide structure 80.) that is greater than an area of the top surface of the first vertically-oriented semiconductor pillar, and the second metal silicide structure has an area that is greater than the top surface of the second vertically-oriented semiconductor pillar (Kim: Fig. 1 and paragraphs [0026]-[0027]).
Regarding claim 7, Kim inherently discloses the structure of claim 6, wherein the first metal silicide structure has a resistivity that is less than a resistivity of the first vertically-oriented semiconductor pillar, and the second metal silicide structure has a resistivity that is less than a resistivity of the second vertically-oriented semiconductor pillar (Kim: Fig. 1 and paragraphs [0026]-[0027], [0045]; Salicidation (self-aligned silicide) process lowers the contact resistance, allowing signals to travel faster without overheating the circuit).
Regarding claim 8, Kim inherently discloses the structure of claim 3, wherein the first dielectric plug is disposed on the first dielectric material (Kim: Fig. 1 and paragraph [0041]).
Regarding claim 23, Kim discloses a structure, comprising: a first vertically-oriented semiconductor pillar 15 having one or more sidewalls, and a top surface, the first vertically-oriented semiconductor pillar having a first width (Kim: Fig. 1 and paragraph [0024]); a first dielectric material 30 abutted to the one or more sidewalls of the first vertically-oriented semiconductor pillar (Kim: Fig. 1 and paragraphs [0024]-[0025]); and a first conductive structure 80/90 (Kim: Fig. 1 and paragraphs [0026], [0028]-[0029]) having a first surface (the surface contacting the top and sidewalls of the pillar 15), and having a second width that is greater than the first width, the first conductive structure disposed such that a second portion of its first surface is in contact with the top surface of the first vertically-oriented semiconductor pillar, wherein a first portion of the first surface of the first conductive structure extends laterally beyond the top surface of the first vertically-oriented semiconductor pillar, and the first portion of the first surface is disposed on the first dielectric material 30, and wherein the first conductive structure is in contact with the top surface and the one or more sidewalls of the first vertically-oriented semiconductor pillar 15 (Kim: Fig. 1 and paragraph [0027]).
Regarding claim 24, Kim discloses the structure of claim 23, wherein the first vertically-oriented semiconductor pillar is integral with a semiconductor substrate (Kim: Fig. 1 and paragraph [0024]).
Regarding claim 25, Kim discloses the structure of claim 23, further comprising: a second vertically-oriented semiconductor pillar 15 having one or more sidewalls, and a top surface, wherein the second vertically-oriented semiconductor pillar is abutted on at least one of its one or more sidewalls by at least the first dielectric material 30, wherein a first portion of a second conductive structure 80 is disposed on the top surface of the second vertically-oriented semiconductor pillar, and is in contact therewith (Kim: Fig. 1 and paragraphs [0026]-[0029]), wherein the first conductive structure comprises a first metal silicide structure, and the second conductive structure comprises a second metal silicide structure (Kim: Fig. 1 and paragraphs [0026], [0049]).
Regarding claim 26, Kim discloses the structure of claim 25, further comprising: a first dielectric plug 70 disposed between the first metal silicide structure and the second metal silicide structure (Kim: Fig. 1 and paragraph [0041]).
Regarding claim 27, Kim inherently discloses the structure of claim 26, wherein the first dielectric plug comprises silicon nitride (Kim: Fig. 1 and paragraphs [0039], [0041]).
Regarding claim 28, Kim inherently discloses the structure of claim 25, wherein the first metal silicide structure has an area (The term “an area” is a broad term and is considered to be any part of the metal silicide structure 80.) that is greater than an area of the top surface of the first vertically-oriented semiconductor pillar, and the second metal silicide structure has an area that is greater than the top surface of the second vertically-oriented semiconductor pillar (Kim: Fig. 1 and paragraphs [0026]-[0027]).
Regarding claim 29, Kim inherently discloses the structure of claim 28, wherein the first metal silicide structure has a resistivity that is less than a resistivity of the first vertically-oriented semiconductor pillar, and the second metal silicide structure has a resistivity that is less than a resistivity of the second vertically- oriented semiconductor pillar (Kim: Fig. 1 and paragraphs [0026]-[0027], [0045]; Salicidation (self-aligned silicide) process lowers the contact resistance, allowing signals to travel faster without overheating the circuit).
Regarding claim 30, Kim inherently discloses the structure of claim 25, wherein a first dielectric plug is disposed on the first dielectric material (Kim: Fig. 1 and paragraph [0041]).
Allowable Subject Matter
Claims 9-10 and 21-22 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 9, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein a top surface of the second dielectric structure is coplanar with a top surface of the first metal silicide structure. Claims 10 and 21-22 are included likewise as they depend from claim 9.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claims 1-8 and 23-30 have been fully considered, but are found to be moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
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April 14, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813