Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 12/15/25. Claims 1-20 are pending in this application. Non-elected claims 12-20, without traverse, have been withdrawn from examination.
Claim Rejections Under 35 U.S.C. §102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-11 are rejected under 35 U.S.C. §102(a)(2) as being unpatentable over Chen (US 20230144120 A1).
Regarding claim 1, Chen discloses a semiconductor device comprising: an array of memory cells (see fig 4, 5, para [0003] and para [0028] 100 disclosing memory device), wherein each of the memory cells comprises a vertical transistor (see figs 4 and 5 disclosing vertical transistors), wherein the vertical transistor comprises a semiconductor body extends in a first direction(see fig 9, disclosing 130/260 and 103 being transistor components arranged vertically in 110); bit lines coupled to the memory cells (see fig 9, disclosing 260 being integral to memory cell), wherein each of the bit lines is electrically connected to a first end of the semiconductor body (formed within 110); and first air gaps (170/213a), wherein at least one of the first air gaps is between adjacent bit lines (see 170/213a are formed in between 260).
Applicant has amended claim 1 to recite that the storage unit is coupled to the vertical transistor and that the storage unit is coupled to the storage unit is coupled to the vertical transistor at a second end of the second body. This office action has adjusted the interpretation of Chen to mean that either 1) the substrate includes the entire body (210/170/260/130) or 2) that the storage is formed on the top and the bit line is formed on bottom (of the substrate). Chen further discloses this newly amended features. In particular, Chen discloses the identical arrangement as claimed in claim 1. See reproduction of figures:
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Further, applicant appears to assert that both the capacitor and the bitlines are on an integral continuous substrate. However, this office action notes that this feature is not recited in the amended claims.
Regarding claim 2, Chen discloses the semiconductor device of claim 1, wherein at least two of adjacent first air gaps are between adjacent bit lines(see 170/213a are formed in between 260 are at least two airgaps).
Regarding claim 3, Chen discloses the semiconductor device of claim 1, further comprising: word lines coupled to the memory cells, wherein each of the word lines is electrically connected to the gate structure (see para [0030] disclosing word line is at the gate, see figs 1, 2, 140 being the bit lines). Applicant has amended claim 3 to further recite that the gate structure of the vertical transistor coupled to one or more sides of the semiconductor body.
Regarding claim 4, Chen discloses the semiconductor device of claim 3, wherein: each of the first air gaps extends in a second direction, each of the bit tines extends in the second direction, and each of the word tines extends in a third direction; and the first direction is perpendicular to the second direction, and the second direction is perpendicular to the third direction (see fig 6, disclosing airgaps extending in the x-y direction, see 170/185b).
Regarding claim 5, Chen discloses the semiconductor device of claim 1, further comprising: a first dielectric layer, wherein at least a portion of the first dielectric layer is between adjacent bit lines see 170 disclosing dielectric layers next to 140, see fig 1 and 2.
Regarding claim 6, Chen discloses the semiconductor device of claim 1, further comprising: a first dielectric layer, wherein at least a portion of the first dielectric layer is between two adjacent first air gaps (see air gaps 170/185b having dielectric layers).
Regarding claim 7, Chen discloses the semiconductor device of claim 1, further comprising: a first dielectric layer, wherein at least one of the first air gaps is encapsulated by the first dielectric layer (see 185b being encapsulated by 185).
Regarding claim 8, Chen discloses the semiconductor device of claim 1, further comprising: second dielectric layers extending in the first direction, wherein each of the second dielectric layers is between two adjacent semiconductor bodies (see 260 and 170 having at least two dielectric layers adjacent to 110).
Regarding claim 9, Chen discloses the semiconductor device of claim 1, further comprising: a first dielectric layer; and second dielectric layers, wherein at least a portion of the first dielectric layer is between adjacent second dielectric layers(see 260 and 170 having at least two dielectric layers adjacent to each other).
Regarding claim 10, Chen discloses the semiconductor device of claim 9, wherein at least one of the first air gaps is encapsulated by the first dielectric layer and one of the second dielectric layers. (see 260 and 170 having at least two dielectric layers adjacent to 185 encapsulating 185b).
Regarding claim 11, Chen discloses the semiconductor device of claim 1, further comprising: a first dielectric layer, wherein only one first air gap is between adjacent bit lines, and the first air gap is encapsulated by the first dielectric layer (see 260 and 170 having at least two dielectric layers adjacent to 110, 260 and 170 having at least two dielectric layers adjacent to 185 encapsulating 185b)).
Regarding claim 21, Chen he semiconductor device of claim 1, further comprising: a storage unit contact between the semiconductor body and the storage unit (see capacitor contact 181).
Regarding claim 22, Chen discloses the semiconductor device of claim 1, further comprising: bit line contacts, wherein each of the bit line contacts is between the corresponding semiconductor body and the bit line (see 160a between 110 and 210).
Regarding claim 23, Chen discloses the semiconductor device of claim 1, wherein the storage unit comprises a capacitor or a Phase-Change Memory (PCM) element (see para [0035] disclosing capacitor).
Regarding claim 24, Chen discloses the semiconductor device of claim 1, wherein the at least one of the first air gaps extends in the first direction and overlaps with the semiconductor body in a plane orthogonal to the first direction (see 171 extends into the page).
Regarding claim 25, Chen discloses the semiconductor device of claim 3, wherein the gate structure of the vertical transistor is coupled to four sides of the semiconductor body (see para [0030] disclosing at least four gates).
Response to Arguments
Applicants have amended claims to recite additional features. However, applicants amendments has necessitated a shift in interpretation regarding the cited art. Applicant’s assertions are not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893
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