Method DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
The Amendment filed on 2/13/2026, responding to the Office action mailed on 11/14/2025, has been entered into the record. The present Office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-20 are pending in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20210134785 A1) in view of Chen (US 20210233834 A1) and Yu et al. (TW 202203377 A) and Park et al. (US 20150303209 A1).
Re Claim 1 Yang teaches a semiconductor device (FIG. 15C) comprising:
a substrate (100) [0089] including an active pattern (AP2) [0092];
a channel pattern (CH2) [00954] and a source/drain pattern (SD2) that are each on the active pattern (AP2), the source/drain pattern connected to the channel pattern (FIG. 15C);
a gate electrode (GE) [0097] on the channel pattern CH2, the gate electrode extending lengthwise in a first direction (D1, FIG. 14);
an active contact (AC) [0109] on the source/drain pattern (SD2), the active contact extending lengthwise in the first direction (D1, FIG. 14);
an upper contact (SC) [0111] connected to and being disposed below the active contact (AC) and extending into the substrate (100);
Yang does not teach a lower power interconnection line extending lengthwise in a second direction perpendicular to the first direction, and
the lower power interconnection line includes a connection portion connected to the upper contact.
Chen teaches a lower power interconnection line (124) [0022] extending lengthwise in a second direction (D2, left to right, FIG. 2) perpendicular to the first direction (D1), and
the lower power interconnection line (124) includes a connection portion (part of 124 in direct contact with liner 232, [0022] “…232 uses a conductive material…”) (mechanically) connected to the upper contact (350) [0027] and buried in the substrate (110 [0029], FIG. 2)
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chen into the structure of Yang since Chen is also about a transistor semiconductor device.
The ordinary artisan would have been motivated to modify Yang in combination with Yu in the above manner for the motivation of optimally integrating lower power interconnection line to allow the device to maintain optimal voltage levels. [0001] states, “As the integrated circuits continue to scale down, so do the power rails. This inevitably leads to increased voltage drop across the power rails, as well as increased power consumption of the integrated circuits.”
Yang in view of Chen does not teach a power delivery network layer on a bottom surface of the substrate.
Yu teaches a power delivery network layer (100A, page 11 par 3) on a bottom surface of the substrate (72, FIG. 19B).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Yu into the structure of Yang in view of Chen since Yu is also about a transistor semiconductor device.
The ordinary artisan would have been motivated to modify Yang in combination with Yu in the above manner for the motivation of optimally integrating a power delivery network to build a transistor that function at a peak level and is still as small as possible as industry demands smaller devices. Page 3 par 1 states, “As the demand for ever-shrinking electronic components has grown, there has been a need for smaller and more creative semiconductor die packaging techniques.”
Yang in view of Chen and Yu does not teach a lower portion of the upper contact protrudes into the connection portion.
Park teaches a lower portion of the upper contact (A1) [0054] protrudes into the connection portion (L1, [0054], FIG. 2B).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Park into the structure of Yang in view of Chen and Yu since Park is also about a transistor semiconductor device.
The ordinary artisan would have been motivated to modify Park in combination with Yang in view of Chen and Yu in the above manner for the motivation of arranging the upper contact and connection portion of the chip to help the device reach peak memory capacity. [0003] states, “As well as the 3D-IC memory technique, a patterning technique for fine patterns and a multi-level cell (MLC) technique may be used to increase the memory capacity of the semiconductor memory device.”
Re Claim 2 Yang in view of Chen and Yu and Park teaches the semiconductor device as claimed in claim 1, wherein the connection portion (Park, L1) is in contact with a bottom surface and opposite sidewalls of the upper contact (A1, FIG. 2B).
Re Claim 9 Yang in view of Chen and Yu and Park teaches the semiconductor device as claimed in claim 1, wherein the power delivery network layer (Yu, 100A) is configured to apply a source voltage or a drain voltage (it is inherent that the power delivery network is configured to apply a source/drain voltage) to the lower power interconnection line (82, FIG. 19B).
Claims 3-4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20210134785 A1) in view of Chen (US 20210233834 A1) and Yu et al. (TW 202203377 A) and Park et al. (US 20150303209 A1) as applied to claim 1 above, and further in view of Jin et al. (CN 114725058 A).
Re Claim 3 Yang in view of Chen and Yu and Park teaches the semiconductor device as claimed in claim 1, but does not teach:
a lower portion of the connection portion has a first width,
a central portion of the connection portion has a second width,
an upper portion of the connection portion has a third width,
the first width is greater than the second width, and
the third width is greater than the second width.
Jin teaches a lower portion of the connection portion (130, page 5 par 3) has a first width,
a central portion of the connection portion (130) has a second width,
an upper portion of the connection portion (31, page 5 par 3) has a third width,
the first width is greater than the second width, and
the third width is greater than the second width (see FIG. 8 fragment below).
Figure 8 fragment shown below with connection portion and 3 widths labeled
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It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Jin into the structure of Yang in view of Chen and Yu and Park since Jin is also about a transistor semiconductor device.
The ordinary artisan would have been motivated to modify Jin in combination with Yang in view of Chen and Yu and Park in the above manner for the motivation of optimizing the conductor paths in the chip to optimize the current levels in the semiconductor device. Page 2 par 2 states, “The embedded power rail is good for releasing the interconnection of wiring resource, but also can provide a lower resistor current distribution, in addition, it is good for improving the writing margin and reading speed.”
Re Claim 4 Yang in view of Chen and Yu and Park and Jin teaches the semiconductor device as claimed in claim 1, wherein the connection portion (Jin, 130) has a sandglass shape (130 is shaped like bottom half of a sandglass, FIG. 8).
Re Claim 8 Yang in view of Chen and Yu and Park and Jin teaches the semiconductor device as claimed in claim 1, wherein:
a width of the upper contact (Jin, 31) becomes progressively less toward the bottom surface of the substrate (page 5 par 3, 100), and
a width of the lower power interconnection line (130) becomes progressively greater toward the bottom surface of the substrate (100, FIG. 5).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20210134785 A1) in view of Chen (US 20210233834 A1) and Yu et al. (TW 202203377 A) and Park et al. (US 20150303209 A1) as applied to claim 1 above, and further in view of Okamoto et al. (WO 2021111604 A1).
Re Claim 5 Yang in view of Chen and Yu and Park teaches the semiconductor device as claimed in claim 1, further comprising:
a metal layer (Yang, M2) [0045] on the active contact (AC) and the upper contact (SC).
Yang in view of Chen and Yu and Park does not teach the metal layer includes an interconnection line electrically connecting the active contact and the upper contact to each other.
Okamoto teaches the metal layer (4120, page 9 par 4 “control signal line”) includes an interconnection line (4120) electrically connecting the active contact (4121) and the upper contact to each other (3120, FIG. 11).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Okamoto into the structure of Yang in view of Chen and Yu and Park since Okamoto is about FET semiconductor devices
The ordinary artisan would have been motivated to modify Okamoto in combination with Yang in view of Chen and Yu and Park in the above manner for the motivation of using interconnect lines to help reduce power consumption since the current will flow though the interconnection lines. Page 2 par 2 states, “By using a switch, the power supply is turned off when it is not necessary to operate the logic circuit, the leakage current generated in the transistors constituting the logic circuit is suppressed, and the power consumption can be reduced.”
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20210134785 A1) in view of Chen (US 20210233834 A1) and Yu et al. (TW 202203377 A) and Park et al. (US 20150303209 A1) as applied to claim 1 above, and further in view of and Jin et al. (CN 114725058 A) and Cheng et al. (US 20210375665 A1).
Re Claim 6 Yang in view of Chen and Yu and Park and Jin teaches the semiconductor device as claimed in claim 1, but does not teach:
a first liner on a sidewall of the upper contact; and
a lower spacer between the lower power interconnection line and the substrate, wherein:
the lower spacer includes a second liner and an oxide spacer.
Jin teaches a first liner (180, page 8 par 5) on a sidewall of the upper contact (31, FIG. 7); and
a lower spacer (140 and 150) between the lower power interconnection line (130) and the substrate (100), wherein:
the lower spacer includes a second liner (page 7 par 8, 140) and an oxide spacer (page 7 par 6, 150).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Jin into the structure of Yang in view of Chen and Yu and Park since Jin is also about a transistor semiconductor device.
The ordinary artisan would have been motivated to modify Jin in combination with Yang in view of Chen and Yu and Park in the above manner for the motivation of optimally integrating liners and spacers around the conductive paths to help control the device’s resistance and ensure it functions at a peak level. Page 2 par 2 states, “The embedded power rail is good for releasing the interconnection of wiring resource, but also can provide a lower resistor current distribution, in addition, it is good for improving the writing margin and reading speed.”
Yang in view of Chen and Yu and Park and Jin does not teach the connection portion includes a protrusion extending toward the first liner.
Cheng teaches the connection portion (15 and 112, [0017] and [0022], FIG. 10 show 112 is same material/part as 15) includes a protrusion extending toward the first liner (12, [0017], FIG. 10B).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Cheng into the structure of Yang in view of Chen and Yu and Park and Jin since Cheng is about a transistor semiconductor device.
The ordinary artisan would have been motivated to modify Cheng in combination with Yang in view of Chen and Yu and Park and Jin in the above manner for the motivation of optimally arranging conductive layers to help the chip function at a peak level and not require the device to need extra power to function. [0002] states, “For example, for any two adjacent conductive features, when the distance between the conductive features decreases, the resulting capacitance (parasitic capacitance) increases. The increased capacitance results in an increase of power consumption and an increase in the resistive-capacitive (RC) time constant, i.e., an increase of signal delays.”
Re Claim 7 Yang in view of Chen and Yu and Park and Jin and Cheng teaches the semiconductor device as claimed in claim 6, wherein:
the oxide spacer (Cheng, 30 and 60) includes a first oxide spacer (30 on right of 15, [0032] calls out SiON as possible material) on a first side of the lower power interconnection line; and
a second oxide spacer (60 on left of 15, [0018] calls out SiON as possible material) on a second side of the lower power interconnection line (15), and
a thickness of the first oxide spacer (30) is different from a thickness of the second oxide spacer (60, FIG. 10B).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20210134785 A1) in view of Chen (US 20210233834 A1) and Yu et al. (TW 202203377 A) and Park et al. (US 20150303209 A1) as applied to claim 1 above, and further in view of Yang et al. (US 20200051981 A1, Yang2).
Re Claim 10 Yang in view of Chen and Yu and Park teaches the semiconductor device as claimed in claim 1, wherein:
the channel pattern (Yang, CH2) includes a plurality of semiconductor patterns (CH2) stacked sequentially and spaced apart from each other (FIG. 19B).
Yang in view of Chen and Yu and Park does not teach the gate electrode includes an inner electrode between adjacent ones of the plurality of semiconductor patterns and an outer electrode outside the plurality of semiconductor patterns.
Yang2 teaches the gate electrode includes (150) [0072] an inner electrode (150S) [0079] between adjacent ones of the plurality of semiconductor patterns (N1, N2, N3) and an outer electrode (150M) outside the plurality of semiconductor patterns (N1, N2, N3, FIG. 16).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Yang into the structure of Yang in view of Chen and Yu and Park since Yang is about a FET semiconductor device.
The ordinary artisan would have been motivated to modify Yang in combination with Yang in view of Chen and Yu and Park in the above manner for the motivation of integrating electrodes in the device around the channel pattern layers to help the device avoid short circuiting and maintain optimal current levels. [0112] states, “Since the semiconductor device 1 according to the present disclosure has a blocking film 120, in the first region R1, for preventing the first source/drain region 162 from being damaged in the process of forming the gate electrode 150, particularly, the sub-gate portion 150S, a short circuit between the first source/drain region 162 and the gate electrode 150 may be prevented, and since the semiconductor device 1 includes the insulating spacer 140 in the second region, a short circuit between the second source/drain region 164 and the gate electrode 150 may be prevented, thereby ensuring reliability.”
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20210134785 A1) in view of Yu et al. (TW 202203377 A) and Chen (US 20210233834 A1) and Jin et al. (CN 114725058 A).
Re Claim 11 Yang teaches a semiconductor device (FIG. 15C) comprising:
a substrate (100) [0089] including an active pattern (AP2) [0092];
a channel pattern (CH2) [0095] and a source/drain pattern (SD2) that are each on the active pattern (AP2), the source/drain pattern connected to the channel pattern (FIG. 15C);
a gate electrode (GE) [0097] on the channel pattern (CH2), the gate electrode extending lengthwise in a first direction (D1, FIG. 14);
an active contact (AC) [0109] on the source/drain pattern (SD2), the active contact extending lengthwise in the first direction (D1, FIG. 14);
an upper contact (SC) [0111] connected to and disposed below the active contact (AC) and extending into the substrate (100).
Yang does not teach a first liner on a sidewall of the upper contact;
a power delivery network layer on a bottom surface of the substrate.
Yu teaches a first liner (69A, page 6 par 3) on a sidewall of the upper contact (67A, FIG. 1B and 60 region in FIG. 19B);
a power delivery network (100A, page 11 par 3) layer on a bottom surface of the substrate (72, FIG. 19B).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Yu into the structure of Yang since Yu is also about a transistor semiconductor device.
The ordinary artisan would have been motivated to modify Yu in combination with Yang in the above manner for the motivation of optimally integrating the lower power interconnection line and a power delivery network to build a transistor that function at a peak level and is still as small as possible as industry demands smaller devices. Page 3 par 1 states, “As the demand for ever-shrinking electronic components has grown, there has been a need for smaller and more creative semiconductor die packaging techniques.”
Yang in view of Yu does not teach a lower power interconnection line extending lengthwise in a second direction perpendicular to the first direction and buried in the substrate, the lower power interconnection line being in contact with a lower surface of the upper contact.
Chen teaches a lower power interconnection line (124) [0022] extending lengthwise in a second direction (D2, left to right) perpendicular to the first direction (D1) and buried in the substrate (110, [0020], FIG. 2), the lower power interconnection line (124) being in (mechanical) contact with a lower surface of the upper contact (350) [0027].
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chen into the structure of Yang in view of Yu since Chen is also about a transistor semiconductor device.
The ordinary artisan would have been motivated to modify Chen in combination with Yang in view of Yu in the above manner for the motivation of optimally integrating lower power interconnection line to allow the device to maintain optimal voltage levels. [0001] states, “As the integrated circuits continue to scale down, so do the power rails. This inevitably leads to increased voltage drop across the power rails, as well as increased power consumption of the integrated circuits.”
Yang in view of Yu and Chen does not teach a lower spacer between the lower power interconnection line and the substrate;
the lower spacer includes a second liner and an oxide spacer, and
the second liner is formed of a silicon-based insulating material different from that of the oxide spacer.
Jin teaches a lower spacer (140, page 7 par 8 and 150, page 7 par 6) between the lower power interconnection line (130, page 7 par 1) and the substrate (100, page 7 par 3).
the lower spacer (140 and 150) includes a second liner (140, page 7 par 8) and an oxide spacer (150, page 7 par 6), and
the second liner is formed of a silicon-based insulating material different from that of the oxide spacer (page 7 par 8, 140 can be silicon oxynitride, and page 13 par 7, 150 can be silicon oxide, FIG. 1).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Jin into the structure of Yang in view of Yu and Chen is also about a transistor semiconductor device.
The ordinary artisan would have been motivated to modify Jin in combination with Yang in view of Yu and Chen in the above manner for the motivation of arranging the upper contact and connection portion of the chip to help the device function optimally. Page 2 par 2, “The embedded power rail is good for releasing the interconnection of wiring resource, but also can provide a lower resistor current distribution, in addition, it is good for improving the writing margin and reading speed.”
Re Claim 12 Yang in view of Yu and Chen and Jin teaches the semiconductor device as claimed in claim 11, wherein:
the first liner (Jin, page 8 par 5 180 can be silicon oxide) and the second liner (140 can be silicon oxynitride) are formed of different materials from one another, and
the first liner (180) and the second liner (140) are connected directly to each other (FIG. 5).
Claims 13 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20210134785 A1) in view of Yu et al. (TW 202203377 A) and Chen (US 20210233834 A1) and Jin et al. (CN 114725058 A) as applied to claim 11 above, and further in view of Kwak et al. (US 20200168720 A1).
Re Claim 13 Yang in view of Yu and Chen and Jin teaches the semiconductor device as claimed in claim 11, wherein:
the first liner (Jin, 180, page 15 par 5 says 180 can be silicon oxide) and the second liner (140, page 13 par 9 says 140 can be silicon oxide) are formed of the same material as one another.
Yang in view of Yu and Chen and Jin does not teach the first liner and the second liner are separated from each other.
Kwak teaches the first liner (146) [0039] and the second liner (166) [0045] are separated from each other (FIG. 4A).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Kwak into the structure of Yang in view of Yu and Chen and Jin since Kwak is also about a transistor semiconductor device.
The ordinary artisan would have been motivated to modify Kwak in combination with Yang in view of Yu and Chen and Jin in the above manner for the motivation of optimally placing the liners in the device with respect to each other to allow for a device to be as small as possible and still function at a peak level. [0003] states, “With the trend of producing lighter, thinner, and smaller electronics, there is increasing demand for higher integration of integrated circuit devices.”
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20210134785 A1) in view of Yu et al. (TW 202203377 A) and Chen (US 20210233834 A1) and Jin et al. (CN 114725058 A) as applied to claim 11 above, and further in view of Cheng et al. (US 20210375665 A1).
Re Claim 14 Yang in view of Yu and Chen and Jin teaches the semiconductor device as claimed in claim 11, but does not teach:
the oxide spacer includes a first oxide spacer portion on a first side of the lower power interconnection line; and a second oxide spacer portion on a second side of the lower power interconnection line, and
a thickness of the first oxide spacer portion is different from a thickness of the second oxide spacer portion.
Cheng teaches the oxide spacer (30 and 60) includes a first oxide spacer portion (30 on left of 15, [0032]) on a first side of the lower power interconnection line; and a second oxide spacer portion (60 on right of 15, [0018]) on a second side of the lower power interconnection line (15) [0017], and
a thickness of the first oxide spacer portion is different from a thickness of the second oxide spacer portion (FIG. 10B).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Cheng into the structure of Yang in view of Yu and Chen and Jin since Cheng is about a transistor semiconductor device.
The ordinary artisan would have been motivated to modify Cheng in combination with Yang in view of Yu and Chen and Jin in the above manner for the motivation of adding oxide spacers around the lower power interconnection line to help optimize the current in the conductive layers in the device and help reduce the conductive layers from having unwanted current leakage.
Re Claim 15 Yang in view of Yu and Chen and Jin and Cheng teaches the semiconductor device as claimed in claim 11, wherein:
the lower power interconnection line (Cheng, 15 and 112, [0017] and [0022], FIG. 10 show 112 is same material/part as 15) includes a connection portion (top of 15 and 112) connected to the upper contact (114) [0022], and
the connection portion includes a protrusion (12) extending toward the first liner (12, [0017], FIG. 10B).
Claims 16 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20210134785 A1) in view of Yu et al. (TW 202203377 A) and Lin et al. (US 20120007154 A1).
Re Claim 16 Yang teaches a semiconductor device (FIG. 15C) comprising:
a substrate (100) [0089] including an active pattern (AP2) [0092];
a channel pattern (CH2) [0095] and a source/drain pattern (SD2) that are each on the active pattern (AP2), the source/drain pattern connected to the channel pattern (FIG. 15C);
a gate electrode (GE) [0097] on the channel pattern (CH2), the gate electrode extending lengthwise in a first direction (D1, FIG. 14);
a gate insulating layer (GI) [0101] between the gate electrode (GE) and the channel pattern (CH2);
a gate spacer (GS) [0099] on a sidewall of the gate electrode (GE);
a gate capping pattern (GP) [0100] on a top surface of the gate electrode (GE);
an interlayer insulating layer (120) [0152] covering the source/drain pattern (SD2) and the gate capping pattern (GP);
an active contact (AC) [0109] extending lengthwise in the first direction (D1, FIG. 14), penetrating through the interlayer insulating layer (120), and electrically connected to the source/drain pattern (SD2);
a metal-semiconductor compound layer (SC) [0111] between the active contact (AC) and the source/drain pattern (SD2);
a gate contact (GC) [0112] penetrating through the interlayer insulating layer (120) and the gate capping pattern (GP), the gate contact electrically connected to the gate electrode (GE, FIG. 15E);
a first metal layer (M1) [0114] on the interlayer insulating layer (120),
a second metal layer (M2) [0122] on the first metal layer (M1), the second metal layer including a second interconnection line (VI2a) [0126] electrically connected to the first metal layer (M1, FIG. 15C);
Yang does not teach an upper contact penetrating through the interlayer insulating layer and extending into the substrate;
the first metal layer including a first interconnection line electrically connecting the active contact and the upper contact to each other;
a lower power interconnection line extending lengthwise in a second direction perpendicular to the first direction
Yu teaches an upper contact (82, page 8 par 4) penetrating through the interlayer insulating layer (76 in 73 layer, FIG. 4, page 9 par 3) and extending into the substrate (72, page 9 par 1);
the first metal layer (100A, page 11 par 3) including a first interconnection line (104, page 11 par 4, FIG. 8) electrically connecting the active contact (114, page 12 par 2, FIG. 9) and the upper contact (82) to each other (FIG. 19A);
a lower power interconnection line (136, page 14 par 2) extending lengthwise in a second direction (D2/left to right, FIG. 19A) perpendicular to the first direction (FIG. 19A); and
a power delivery network layer (100C, page 14 par 1) on a bottom surface of the substrate (72, FIG. 19A),
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Yu into the structure of Yang since Yu is also about a transistor semiconductor device.
The ordinary artisan would have been motivated to modify Yang in combination with Yu in the above manner for the motivation of optimally integrating the upper contact, the lower power interconnection line, and the power delivery network to build a transistor that function at a peak level and is still as small as possible as industry demands smaller devices. Page 3 par 1 states, “As the demand for ever-shrinking electronic components has grown, there has been a need for smaller and more creative semiconductor die packaging techniques.”
Yang in view of Yu does not teach a lower power interconnection line is buried in the substrate;
a first oxide spacer on a first side of the lower power interconnection line and a second oxide spacer on a second side opposite the first side of the lower power interconnection line; and
wherein a thickness of the first oxide spacer is different from a thickness of the second oxide spacer.
Lin teaches a lower power interconnection line (60) [0018] is buried in the substrate (20);
a first oxide spacer (24) [0012] on a first side (left) of the lower power interconnection line (60) and a second oxide spacer (56) on a second side (right) opposite the first side of the lower power interconnection line (60); and
wherein a thickness of the first oxide spacer (24) is different from a thickness of the second oxide spacer (56, FIG. 8B).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Lin into the structure of Yang and Yu since Lin is also about a transistor semiconductor device.
The ordinary artisan would have been motivated to modify Xie in combination with Yu in view of Yang in the above manner for the motivation of optimally integrating the power interconnection line into the substrate and placing oxide spacers around it to allow for optimal device performance and allow for increased device density in integrated circuit. [0002] states, “Among the efforts to increase device density in integrated circuits, three-dimensional integrated circuits (3DICs) are commonly used. Through-substrate vias (TSV) are often used in 3DIC for connecting multiple dies to package substrates.”
Re Claim 19 Yang in view of Yu and Lin teaches the semiconductor device as claimed in claim 16, wherein:
the channel pattern (Yang, CH2) includes a plurality of semiconductor patterns (CH2) stacked sequentially and spaced apart from each other (FIG. 19B), and
the gate electrode includes an inner electrode (GE between CH2 layer in FIG. 19B) between adjacent ones of the plurality of semiconductor patterns and an outer electrode (GE above CH2) outside the plurality of semiconductor patterns (FIG. 19B).
Re Claim 20 Yang in view of Yu and Lin teaches the semiconductor device as claimed in claim 16, wherein the power delivery network layer (Yu, 100C) is configured to apply a source voltage or a drain voltage to the lower power interconnection line (136, S/D region is in 153, FIG. 19A ).
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20210134785 A1) in view of Yu et al. (TW 202203377 A) and Lin et al. (US 20120007154 A1) as applied to claim 16 above, and further in view of Jin et al. (CN 114725058 A).
Re Claim 17 Yang in view of Yu and Lin teaches the semiconductor device as claimed in claim 16, but does not teach:
the lower power interconnection line includes a connection portion connected to the upper contact, and
a lower portion of the upper contact protrudes into the connection portion.
Jin teaches the lower power interconnection line (Jin, 31) includes a connection portion (bottom part of 31 in FIG. 1A rotated 180 degrees) connected to the upper contact (130, page 5 par 3), and
a lower portion of the upper contact (130) protrudes into the connection portion (31, FIG. 1A rotated 180 degrees).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Jin into the structure of Yang and Yu and Lin since Jin is also about a transistor semiconductor device.
The ordinary artisan would have been motivated to modify Jin in combination with Yu in view of Yang and Lin in the above manner for the motivation of integrating the power interconnection line optimally with the upper contact. Page 2 par 2 states, “The embedded power rail is good for releasing the interconnection of wiring resource, but also can provide a lower resistor current distribution…”
Re Claim 18 Yang in view of Yu and Lin and Jin teaches the semiconductor device as claimed in claim 16, wherein:
a width of the upper contact (Jin, 31, page 5 par 3) becomes progressively less toward the bottom surface of the substrate (100, page 5 par 3), and
a width of the lower power interconnection line (130, page 5 par 3) becomes progressively greater toward the bottom surface of the substrate (100, FIG. 1A).
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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/KENNETH MARK SIPLING/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 4/6/26