Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election of the second embodiment in the reply filed on 12/30/25 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-2 and 14-19 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lai et al., US 2022/0358274 . Lai et al. shows the invention as claimed including a semiconductor device comprising: A substrate 410 comprising a P-well region PW (for example, fig. 4A) ; A first N-type metal oxide semiconductor (NMOS) transistor (DN on left hand side of central PW tap region 214B) provided on the P-well region (see fig. 4B) ; A second NMOS transistor (DN on right hand side of central PW tap region 214P) provided on the substrate; and A common body bias region 214P,414P (see figs. 4A-4B) provided between the first NMOS transistor and the second NMOS transistor and contacting both the P-well region and the substrate, wherein the common body bias region is configured to provide a bias voltage to the first NMOS transistor and the second NMOS transistor (see paragraphs 0049-0057, 0095, and figs. 3B, 4A-4B, and 8) . Concerning dependent claim 2, note that Lai et al. further comprises a common body bias contact plug which contacts the common body bias region (see, for example, fig. 8) . Concerning dependent claim 14, note that Lai et al. discloses wherein the first NMOS transistor comprises a first active region, a second active region, and a first gate, which are each provided in the P-well region, and wherein the second NMOS transistor comprises a first active region, a second active region, and a second gate, which are each provided above the substrate (see figs. 7-8 and their descriptions) . With respect to dependent claim 15, note that Lai et al. discloses wherein a first distance between one of the first active region and the second active region of the first NMOS transistor and the common body bias region is different from a second distance between one of the first active region an d the second active region of the second NMOS transistor and the common body bias region (note that as shown in fig. 4B, for example, different active regions will be different spacings from the same common body bias region) . Regarding dependent claim 16, note that the common body bias region is doped with P-type impurities having a concentration higher than a concentration of P-type impurities of the P-well region . With respect to independent claim 17, note that Lai et al. shows the invention as claimed including a semiconductor device comprising: A substrate 410 comprising: A p-well region (see paragraph 0098) comprising: A first active region (for example, 212SD ) ; a second active region (for example, 212 SD) ; and a first gate provided between the first active region and the second active region (source and drain regions) ; A substrate region 410 comprising: A third active region (source/drain 212SD, for example) ; A fourth active region (212 SD, for example) ; and A second gate provided between the third active region and the fourth active region (see paragraph 0056) and A common body bias region 214P,414P (see figs. 4A-4B) contacting both the substrate region and the P-well region, wherein the common body bias region is configured to provide a bias voltage to at least one of the first active region and the second active region, and to at least one of the third active region and the fourth active region (see paragraphs 0049-0057, 0095, and figs. 3B, 4A-4B, and 8) . As to independent claim 18, note that Lai et al. discloses a semiconductor device comprising: A substrate 410 having a first conductivity type; A well region (see, for example, paragraph 0098 and figs. 4a-4b) having the first conductivity type and provided on the substrate; A first metal oxide semiconductor (MOS) transistor provided in the well region and including a first active region (for example, 212 SD) having a second conductivity type; A second MOS transistor provided on the substrate and including a second active region having a second conductivity type (also, see 212 SD) ; and A common body bias region 214P,414P (see figs. 4A-4B) provided between the first MOS transistor and the second MOS transistor and contacting both the well region and the substrate; Wherein the first MOS transistor and the second MOS transistor are electrically connected to the common body bias region, and wherein the common body bias region is configured to provide a bias voltage to the first MOS transistor and the second MOS transistor (see paragraphs 0049-0057, 0095, and figs. 3B, 4A-4B, and 8) . Concerning dependent claim 19, note that the first conductivity type is P type and the second conductivity type is N type (see paragraph 0056) . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim (s) 12 -13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al., US 2022/0358274 in view of Tachiyama , U.S. Patent 5,892,263 . Lai et al. is applied as above but does not expressly disclose wherein the common body bias region comprises a guard band. Tachiyama discloses the use of guard bands between cmos devices (see, for example, col. 1-lines 53-65). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Lai et al. so as to form guard bands between the cmos devices because in such a way latchup between the devices can be prevented. Concerning dependent claim 13, note that Lai et al. modified by Tachiyama does not expressly disclose a first portion of the guard region provided around the first NMOS transistor and a second portion provided around the second NMOS transistor. However, Tachiyama does disclose the use of guard bands between devices (for example, col. 1-lines 53-65). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to form guard bands around the transistor devices and contacting the common body region in order to provide adequate protection for these device features. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT RICHARD A BOOTH whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-1668 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday to Friday, 8:30 to 5:00 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Christine Kim can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-272-8458 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RICHARD A BOOTH/ Primary Examiner, Art Unit 2812 March 21, 2026