Attorney Docket Number: SAM-61206
Filing Date: 07/25/2023
Claimed Priority Date: 01/11/2023 (KR 10-2023-0004217)
Inventor: Lee
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the election filed on 02/20/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Elections/Restrictions
Applicant’s election without traverse of Invention I, reading on a semiconductor device, and the species corresponding to the semiconductor package reading on figure 1 and the solder-based interconnects reading on figures 4A-4C with the solder disposition reading on figure 3C, in the reply filed on 02/20/2026, is acknowledged. The applicant indicated that claims 1-8 and 10-16 read on the elected species. Claims 7-8, however, read on a non-elected species of the claimed invention (e.g., a species corresponding to the solder-based interconnects reading on figure 5). Accordingly, claims 7-9 and 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected invention and/or species, there being no allowable generic or linking claim.
Initial Remarks
For all citations from non-U.S. references, please refer to the original non-English versions of the documents that are attached to this Office action.
Claim Objections
The claims are objected to because of the following informalities:
In lines 6-7 of claim 6, “at a positions corresponding to the plurality of dummy solders” should read as either “at positions corresponding to the plurality of dummy solders” or “at a position corresponding to the plurality of dummy solders”
Appropriate correction is required. No new matter should be added.
Claims Rejection
Initially, and with respect to claims 1 and 15, note that a “product by process” claim is directed to the product per se, no matter how actually made. See In re Thorpe, 227 USPQ 964 (CAFC, 1985) and the related case law cited therein which makes it clear that it is the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that, as here, an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. As stated in Thorpe,
even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir. 1935).
Note that the applicants have the burden of proof in such cases, as the above case law makes clear.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 3-4, 6, 13, and 16 are rejected under 35 U.S.C. 112(b) for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 3 recites the limitation “wherein… the at least one dummy solder includes a plurality of dummy solders disposed at each of four corners of the quadrangular shape of the surface of the main body”. The language of claim does not clearly render whether the limitation “a plurality of dummy solders disposed at each of four corners of the quadrangular shape of the surface of the main body” is intended to mean that a plurality of dummy solders is each disposed at each of four corners of the quadrangular shape or that the plurality of dummy solders in its totality has elements disposed at each of four corners of the quadrangular shape. Accordingly, this limitation in the claim is indefinite.
Claim 4 recites the limitation “wherein… the at least one dummy solder includes a plurality of dummy solders disposed at each of four sides of the quadrangular shape of the surface of the main body”. The language of claim does not clearly render whether the limitation “a plurality of dummy solders disposed at each of four sides of the quadrangular shape of the surface of the main body” is intended to mean that a plurality of dummy solders is each disposed at each of four sides of the quadrangular shape or that the plurality of dummy solders in its totality has elements disposed at each of four sides of the quadrangular shape. Accordingly, this limitation in the claim is indefinite.
Claim 6 recites the limitations “wherein each of the connection terminals includes a connection pad and a conductive metal post protruding from the connection pad, and each of the solder bumps is disposed on a respective conductive metal post and “a plurality of dummy connection terminals having the same structure as the connection terminals”. Parental claim 1, however, recites the presence of two distinct connection terminals: connection terminals upon which a solder bump array is disposed and connection terminals of a device. The claims fail to clarify which of the two distinct “connection terminals” the limitations of claim 6 are intended to refer. Accordingly, this limitation in the claim is indefinite.
Claim 13 recites the limitation “wherein the dummy solder is made of Sn-Bi-X, wherein X is Ag or Fe”. Parental claim 1, however, recites the limitation “a semiconductor package comprising… at least one dummy solder…”. In the event that more than one dummy solder is selected for parental claim 1, dependent claim 13 provides no clear indication of which specific dummy solder from the plurality of dummy solders the limitation “wherein the dummy solder” is intended to refer. Accordingly, this limitation in the claim is indefinite.
Claim 16 recites the limitation “wherein the plurality of dummy connection terminals are… arranged point-symmetrically”. The claim and its parental claim have failed to define with regards to what point or what feature the “plurality of dummy connection terms” are meant to be arranged “point-symmetrically” about. Accordingly, this limitation in the claim is indefinite.
Claim 14 depends from claim 13 and thus inherits the deficiencies identified supra.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10, and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Shi (US 2017/0317062) in view of Alley (US 2009/0072385).
Regarding claim 1, Shi (see, e.g., figs. 1A, 2A, and 3-6) shows most aspects of the instant invention, including a semiconductor package 1 comprising:
a main body 200/100 including at least one semiconductor chip 220;
a plurality of solder bumps 140 provided on a surface 110a of the main body;
a solder bump array including the plurality of solder bumps 140, wherein the solder bumps are configured to electrically connect each of the solder bumps to a respective connection terminal 240 of a device 200 by a soldering process (see, e.g., pars.0023/ll.1-2 and 22-24, 0040/ll.1-18, and 0042/ll.11-12); and
at least one dummy solder 150 connected to the surface of the main body and disposed point-symmetrically about a center of the solder bump array (see, e.g., fig. 1A);
wherein:
the plurality of solder bumps 140 of the solder bump array have a first melting point Second Temperature (see, e.g., par.0023/ll.16-18 and 0040/ll.13-15), and the at least one dummy solder 150 has a second melting point First Temperature lower than the first melting point (see, e.g., pars.0023/ll.16-18, 0037/ll.1-7, and 0040/ll.13-15) so that when heated, the at least one dummy solder melt before the plurality of solder bumps and generate a force in a direction in which the plurality of solder bumps contact connection terminals 240 of the device 200 by surface tension during a soldering process (see, e.g., figs. 3-5 and pars.0038/ll.13-23, 0050/ll.13-19, and 0054/ll.1-9)
Although Shi teaches most aspects of the instant invention, including that Shi’s solder bump array/solder bumps is/are disposed on a surface of Shi’s main body, that Shi’s package includes respective connection terminals of a device, and that Shi’s solder bumps may be electrically connected to connection terminals, Shi shows only solder bumps alone and fails to specify that Shi’s semiconductor package includes a plurality of connection terminals provided on a surface of the main body, wherein the solder bump array is disposed on the plurality of connection terminals such that the plurality of solder bumps are configured to electrically connect each of the connection terminals to Shi’s a respective connection terminal of the device by a soldering process. Alley, in the same field of endeavor and in a similar structure to Shi, teaches many embodiments in which a plurality of connection terminals 611a/611b or 911 are provided on a surface (surface of 605 closest to 621) or (surface of 905 closest to 919) of a main body 605/621/623/619 or 905/919, wherein a solder bump array is disposed on the plurality of connection terminals, and wherein the solder bump array includes a plurality of solder bumps 615a/615b or 915 configured to electrically connect each of the connection terminals to a respective connection terminal (e.g., 617 or 917) of a device 619 or 919 (see, e.g., Alley: figs. 3 and 6 and pars.0050, 0065-0068, and 0096). Alley teaches that including a plurality of connection terminals, shown to be provided on a surface of a main body such that a solder bump array including solder bumps is disposed on the plurality of connection terminals, allows for minimization of the pitch of interconnects and reduction of solder usage as compared to solder-only interconnect structures (see, e.g., Alley: pars.0037 and 0104). Furthermore, Alley teaches that configuring a plurality of solder bumps arranged in such a structure so that the solder bumps are configured to electrically connect each of the connection terminals to a respective connection terminal of a device by a soldering process can facilitate electrical connection between package elements and connection terminals whilst simultaneously improving conductive thermal transport and mitigating defects in the solder bumps, parasitic resistance, and degradation of reliability (see, e.g., Alley: par.0037 and 0065).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include in Shi’s semiconductor package a plurality of connection terminals provided on a surface of the main body and a solder bump array disposed on the plurality of connection terminals, as taught by Alley, so as to promote scaling and miniaturization and increase potential interconnect density in Shi’s device while simultaneously reducing solder usage and amount. Furthermore, it would have been additionally obvious at the time of filing the invention to one of ordinary skill in the art to have a plurality of solder bumps in such a structure configured to electrically connect each of the connection terminals to a respective connection terminal of Shi’s device by a soldering process, as taught by Alley, so as to ensure the already-discussed benefits of Alley while facilitating electrical connections between features of Shi’s semiconductor package, improving conductive thermal transport, mitigating defects in Shi’s solder bumps, reducing parasitic resistance, and ensuring reliability in Shi’s semiconductor package (see, e.g., Alley: par.0037 and 0065).
In reference to the claim language pertaining to “generat[ing] a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process”, the claiming of a new use, new function, or unknown property which is inherently present in the prior art does not necessarily make the claim patentable. In re Best, 195 USPQ 430, 433 (CCPA 1977) and In re Swinehart, 439 F. 2d 210, 169 USPQ 226 (CCPA 1971); please also see MPEP § 2112). Since Shi/Alley shows all the features of the claimed invention, the characteristic of “generat[ing] a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process” is an inherent property of Shi/Alley.
In other words, the specific claim limitation of “generat[ing] a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process” is a property of the dummy solder component of Shi/Alley’s device.
Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best, 562 F.2d at 1255, 195 USPQ at 433. See also Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985).
In the instant case, Shi acknowledges the presence and effects of surface tension and teaches the same solder bump and dummy solder melting points/processes as recited in the claim, therefore, the priorly melted dummy solders will “generate force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process” also recited in the claim.
Accordingly and nevertheless, it is noted that Shi/Alley shows all structural aspects of the semiconductor package according to the claimed invention (see paragraphs 19-24 above), and that the method steps of “electrically connecting each of the connection terminals to a respective connection terminal of a device by a soldering process” and having “when heated, the at least one dummy solder melt before the plurality of solder bumps and generate a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process” are intermediate steps that do not affect the structure of the final device.
Regarding claim 10, Shi (see, e.g., figs. 1A, 2A, and 3-6) shows that the main body 200/100 further includes a substrate or an interposer 210 including a first surface 210a and a second surface 210b oppose the first surface and the at least one semiconductor chip 220 is mounted on the first surface and the plurality of solder bumps 140 and the at least one dummy solder 150 are disposed on the second surface.
Regarding claim 12, Shi (see, e.g., pars.0037/ll.8 and 0040/ll.15) shows that the first melting point Second Temperature is 210 °C or more, and the second melting point First Temperature is 190 °C or less.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66. Similarly, a prima facie case of obviousness exists where the claimed ranges and prior art ranges do not overlap but are close enough that one skilled in the art would have expected them to have the same properties. Titanium Metals Corp. of Amer.v.Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985).
"[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See also In re Harris, 409 F.3d 1339, 74 USPQ2d 1951 (Fed. Cir. 2005).
Nevertheless, differences in temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed temperatures, i.e., 210 °C or more and 190 °C or less, it would have been obvious to one of ordinary skill in the art to use these values in the device of Shi/Alley.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed temperatures or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 13, Shi (see, e.g., par.0023/ll.15) shows that the at least one dummy solder 150 is made of Sn-Bi-X, where is X is Ag or Fe.
With regards to other language recited in claim 13, see the comments stated above in paragraph 12.
Claims 1-4, 10, and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2020/0203299) in view of Shi and Araki (JP H08139096 A).
Regarding claim 1, Huang (see, e.g., figs. 3A, 3A-1, and 3B) shows most aspects of the instant invention, including a semiconductor package 300 comprising:
a main body 120/190/… including at least one semiconductor chip 120
For all claims except for claim 10: … indicates 110c unless otherwise explicitly stated
For claim 10: … indicates (110c not including 114, i.e., not including topmost layer of 110c closest to 120 above topmost 113 closest to 120 and hosting 114/115 – henceforth referred to as 110k);
a plurality of connection terminals 172/10/118a provided on a surface of the main body;
For all claims except claim 11: the surface of the main body may correspond to, e.g., the surface of 110c or 110k closest to 190;
For claim 11: the surface of the main body corresponds to the surface of 120 closest to 190
a solder bump array disposed on the plurality of connection terminals and including a plurality of solder bumps 182b configured to electrically connect each of the connection terminals to a respective connection terminal 198a of a device 192 by a solder (see, e.g., pars.0026, 0037, 0042/ll.1-6, 0056/ll.3, 0062/ll.6-8, 0066, and 0070); and
at least one dummy solder 184b connected to the surface of the main body and disposed point-symmetrically about a center of the solder bump array (see, e.g., fig. 3A-1);
wherein:
the plurality of solder bumps 182b of the solder bump array have a first melting point, and the at least one dummy solder 184b has a second melting point (see, e.g., par.0045/ll.1-4)
Huang teaches most aspects of the instant invention. Huang further teaches that that the plurality of solder bumps have a first melting point and the at least one dummy solder has a second melting point, that Huang’s package employs soldering processes, that Huang’s dummy solder and solder bumps are each directly physically coupled to respective underlying conductive layers, and that melting points may vary within Huang’s package (see, e.g., pars.0045/ll.1-4, 0056/ll.1-4, and 0070). Huang, however, fails to specify that the solder bumps are connected to each of the connection terminals of the device by a soldering process and that the second melting point is lower than the first melting point so that when heated the at least one dummy solder melt before the plurality of solder bumps and generate a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process.
Shi, in the same field of endeavor and in a similar device to Huang, teaches a device wherein a plurality of solder bumps 140 of a solder bump array have a first melting point Second Temperature (see, e.g., par.0023/ll.16-18 and 0040/ll.13-15), and an at least one dummy solder 150 has a second melting point First Temperature lower than the first melting point (see, e.g., pars.0023/ll.16-18, 0037/ll.1-7, and 0040/ll.13-15) so that when heated, the at least one dummy solder melt before the plurality of solder bumps and generate a force in a direction in which the plurality of solder bumps contact connection terminals 240 of a device 200 by surface tension during a soldering process (see, e.g., Shi: figs. 3-5 and pars.0038/ll.13-23, 0050/ll.13-19, and 0054/ll.1-9). Shi teaches that such a difference in melting points and melting times improves alignment and attachment of the connection terminals of the device to the plurality of solder bumps (see, e.g., pars.0050/ll.13-19 and 0054). Furthermore, Araki, also in the same field of endeavor and in a similar device to Huang, similarly teaches a device having a plurality of solder bumps of a solder bump array having a first melting point and an at least one dummy solder having a second melting point lower than the first melting point so that when heated the at least one dummy solder melt before the plurality of solder bumps and generate a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process (see, e.g., Araki: figs. 9-11 and pars.0011 and 0040). Araki teaches that such a connection process suppresses positional deviation, significantly improves mounting time, and improves alignment and attachment between the connection terminals of the device and the plurality of solder bumps (see, e.g., Araki: pars.0011 and 0040).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the plurality of solder bumps connected to a respective connection terminal of a device by a soldering process and to have the plurality of solder bumps of the solder bump array have a first melting point, and the at least one dummy solder have a second melting point lower than the first melting point so that when heated, the at least one dummy solder melt before the plurality of solder bumps and generate a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process, as taught by Shi and Araki, so as to suppress positional deviation, significantly improve mounting time, and improves alignment and attachment between the connection terminals of the device and the plurality of solder bumps in Huang’s package.
In reference to the claim language pertaining to “generat[ing] a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process”, the claiming of a new use, new function, or unknown property which is inherently present in the prior art does not necessarily make the claim patentable. In re Best, 195 USPQ 430, 433 (CCPA 1977) and In re Swinehart, 439 F. 2d 210, 169 USPQ 226 (CCPA 1971); please also see MPEP § 2112). Since Huang/Shi/Araki shows all the features of the claimed invention, the characteristic of “generat[ing] a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process” is an inherent property of Huang/Shi/Araki.
In other words, the specific claim limitation of “generat[ing] a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process” is a property of the dummy solder component of Huang/Shi/Araki’s device.
Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best, 562 F.2d at 1255, 195 USPQ at 433. See also Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985).
In the instant case, Shi and Araki acknowledge the presence and effects of surface tension and teach the same solder bump and dummy solder melting points/processes as recited in the claim, therefore, the priorly melted dummy solders will “generate force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process” also recited in the claim.
Accordingly and nevertheless, is noted that Huang/Shi/Araki shows all structural aspects of the semiconductor package according to the claimed invention (see paragraphs 37-43 above), and that the method steps of “electrically connecting each of the connection terminals to a respective connection terminal of a device by a soldering process” and having “when heated, the at least one dummy solder melt before the plurality of solder bumps and generate a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process” are intermediate steps that do not affect the structure of the final device.
Regarding claim 2, Huang (see, e.g., fig. 3A-1) shows that the at least one dummy solder 184b is disposed at an outside of a perimeter of the solder bump array.
Regarding claim 3, Huang (see, e.g., fig. 3A-1) shows that the surface (e.g., surface of 110c closest to 190) of the main body 120/190/110c has a quadrangular shape, and the at least one dummy solder 184b includes a plurality of dummy solders 184b disposed at each of four corners of the quadrangular shape of the surface of the main body.
With regards to other language recited in claim 3, see the comments stated above in paragraph 10. For the express purposes of examination, the claim is interpreted such that the plurality of dummy solders in its totality has elements disposed at each of four corners of the quadrangular shape.
Regarding claim 4, Huang (see, e.g., fig. 3A-1) shows that the surface (e.g., surface of 110c closest to 190) of the main body 120/190/110c has a quadrangular shape, and the at least one dummy solder 184b includes a plurality of dummy solders 184b disposed at each of four sides of the quadrangular shape of the surface of the main body.
With regards to other language recited in claim 4, see the comments stated above in paragraph 11. For the express purposes of examination, the claim is interpreted such that the plurality of dummy solders in its totality has elements disposed at each of four sides of the quadrangular shape.
Regarding claim 5, Huang (see, e.g., fig. 3A and 3B and pars.0066 and 0068/ll.4-6) shows that the at least one dummy solder 184b comprises a plurality of dummy solders 184b, wherein a shape (see, e.g., fig. 3A, teaching a curved top surface and curved sidewall shape) and size T5 or W9 (e.g., a size in a direction parallel to the side surface of 172 closest to 174c) of which is the same as a shape (see, e.g., fig. 3A, teaching a curved top surface and curved sidewall shape) and size T6 or W8 (e.g., a size in a direction parallel to the side surface of 172 closest to 174c) of a solder bump 182b of the plurality of solder bumps 182b.
However, it is noted that the specification fails to provide teachings about the criticality of having the at least one dummy solder having a shape and size of which is the same as a shape and size of a solder bump as claimed in the instant application.
Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the dummy solder or solder bump shape and size disclosed by Huang as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, and the particular dummy solder or solder bump shape and size claimed by applicant is nothing more than one of numerous dummy solder or solder bump shapes and sizes that a person having ordinary skill in the art will find obvious to provide using routine experimentation as a matter of choice or based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976).
Regarding claim 6, Huang (see, e.g., fig. 3B) shows wherein that:
each of the connection terminals 172/10/118a includes a connection pad 118a and a conductive metal post 172 or 172/10 protruding from the connection pad, and each of the solder bumps 182b is disposed on a respective conductive metal post; and
a plurality of dummy connection terminals 174c/10/118b having the same structure as the connection terminals (see, e.g., fig. 3B and pars.0040 and 0043 and that the dummy connection terminals comprise the same general layers and materials in the same order as the connection terminals) are disposed on a surface (e.g., surface of 110c or 110k closest to 190) of the main body 120/190/(110c or 110k) at a positions corresponding to the plurality of dummy solders 184b, and each of the plurality of dummy solders is disposed on a respective metal post 174c or 174c/10 of the dummy connection terminals
With regards to other language recited in claim 6, see the comments stated above in paragraph 12. For the express purposes of examination, the claim is interpreted such that the limitation “the connection terminals” corresponds to the connection terminals upon which a solder bump array is disposed.
Regarding claim 10, Huang (see, e.g., fig. 3B) shows that the main body 120/190/110k further includes a substrate or an interposer (110c including 114, i.e., 110c including topmost layer closest to 120 above topmost 113 closest to 120 and hosting 114/115) including a first surface and a second surface opposite the first surface and the at least one semiconductor chip 120 is mounted on the first surface and the plurality of solder bumps 182b and the least one dummy solder 184b are disposed on the second surface.
Regarding claim 11, Huang (see, e.g., fig. 3B) shows that the surface (surface of 120 closest to 190) of the main body 120/190/110c is a surface of the semiconductor chip 120.
Regarding claim 12, Shi (see, e.g., pars.0037/ll.8 and 0040/ll.15) shows that the first melting point Second Temperature is 210 °C or more, and the second melting point First Temperature is 190 °C or less.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66. Similarly, a prima facie case of obviousness exists where the claimed ranges and prior art ranges do not overlap but are close enough that one skilled in the art would have expected them to have the same properties. Titanium Metals Corp. of Amer.v.Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985).
"[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See also In re Harris, 409 F.3d 1339, 74 USPQ2d 1951 (Fed. Cir. 2005).
Nevertheless, differences in temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). Since the applicant has not established the criticality of the claimed temperatures, i.e., 210 °C or more and 190 °C or less, it would have been obvious to one of ordinary skill in the art to use these values in the device of Huang/Shi/Araki. See also the comments stated above in paragraphs 27-32 with respect to claim 12 regarding criticality, which are considered to be repeated here.
Regarding claim 13, Shi (see, e.g., par.0023/ll.15) shows that the at least one dummy solder 150 is made of Sn-Bi-X, where is X is Ag or Fe.
With regards to other language recited in claim 13, see the comments stated above in paragraph 12.
Claims 1-6 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2022/0302087) in view of Shi and Araki.
Regarding claim 1, Choi (see, e.g., figs. 1 and 6-7) shows most aspects of the instant invention, including a semiconductor package 1000a comprising:
a main body 100/200/300/400 including at least one semiconductor chip 200;
a plurality of connection terminals LSP2/SP1a disposed on a surface of the main body;
a solder bump array disposed on the plurality of connection terminals and including a plurality of solder bumps SB1a configured to electrically connect each of the connection terminals to a respective connection terminal USP1 of a device 100 by a soldering process (see, e.g., pars.0087 and 0090);
at least one dummy solder DB1b connected to the surface of the main body and disposed point-symmetrically about a center of the solder bump array;
wherein:
the plurality of solder bumps SB1a of the solder bump array have a first melting point, and the at least one dummy solder DB1b has a second melting point, wherein it is noted that melting points are inherent properties of solder materials
Choi shows most aspects of the instant invention, and further teaches that a soldering process may be performed to connect the device and connection terminals of the device to the main body surface (see, e.g., pars.0087 and 0090). Choi, however, fails to specify that the second melting point is lower than the first melting point so that when heated the at least one dummy solder melts before the solder bumps and generate a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process.
Shi, in the same field of endeavor and in a similar device to Choi, teaches a device wherein a plurality of solder bumps 140 of a solder bump array have a first melting point Second Temperature (see, e.g., par.0023/ll.16-18 and 0040/ll.13-15), and an at least one dummy solder 150 has a second melting point First Temperature lower than the first melting point (see, e.g., pars.0023/ll.16-18, 0037/ll.1-7, and 0040/ll.13-15) so that when heated, the at least one dummy solder melt before the plurality of solder bumps and generate a force in a direction in which the plurality of solder bumps contact connection terminals 240 of a device 200 by surface tension during a soldering process (see, e.g., Shi: figs. 3-5 and pars.0038/ll.13-23, 0050/ll.13-19, and 0054/ll.1-9). Shi teaches that such a difference in melting points and melting times improves alignment and attachment of the connection terminals of the device to the plurality of solder bumps (see, e.g., pars.0050/ll.13-19 and 0054). Furthermore, Araki, also in the same field of endeavor and in a similar device to Choi, similarly teaches a device having a plurality of solder bumps of a solder bump array having a first melting point and an at least one dummy solder having a second melting point lower than the first melting point so that when heated the at least one dummy solder melt before the plurality of solder bumps and generate a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process (see, e.g., Araki: figs. 9-11 and pars.0011 and 0040). Araki teaches that such a connection process suppresses positional deviation, significantly improves mounting time, and improves alignment and attachment between the connection terminals of the device and the plurality of solder bumps (see, e.g., Araki: pars.0011 and 0040).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the plurality of solder bumps of the solder bump array have a first melting point, and the at least one dummy solder have a second melting point lower than the first melting point so that when heated, the at least one dummy solder melt before the plurality of solder bumps and generate a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process, as taught by Shi and Araki, so as to suppress positional deviation, significantly improve mounting time, and improves alignment and attachment between the connection terminals of the device and the plurality of solder bumps in Choi’s package.
In reference to the claim language pertaining to “generat[ing] a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process”, the claiming of a new use, new function, or unknown property which is inherently present in the prior art does not necessarily make the claim patentable. In re Best, 195 USPQ 430, 433 (CCPA 1977) and In re Swinehart, 439 F. 2d 210, 169 USPQ 226 (CCPA 1971); please also see MPEP § 2112). Since Choi/Shi/Araki shows all the features of the claimed invention, the characteristic of “generat[ing] a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process” is an inherent property of Choi/Shi/Araki.
In other words, the specific claim limitation of “generat[ing] a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process” is a property of the dummy solder component of Choi/Shi/Araki’s device.
Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best, 562 F.2d at 1255, 195 USPQ at 433. See also Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985).
In the instant case, Shi and Araki acknowledge the presence and effects of surface tension and teach the same solder bump and dummy solder melting points/processes as recited in the claim, therefore, the priorly melted dummy solders will “generate force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process” also recited in the claim.
Accordingly and nevertheless, is noted that Choi/Shi/Araki shows all structural aspects of the semiconductor package according to the claimed invention (see paragraphs 64-71 above), and that the method steps of “electrically connecting each of the connection terminals to a respective connection terminal of a device by a soldering process” and having “when heated, the at least one dummy solder melt before the plurality of solder bumps and generate a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process” are intermediate steps that do not affect the structure of the final device.
Regarding claim 2, Choi (see, e.g., figs. 1 and 6-7) shows that the at least one dummy solder DB1b is disposed at an outside of a perimeter of the solder bump array.
Regarding claim 3, Choi (see, e.g., figs. 1 and 6-7) shows that the surface of the main body has a quadrangular shape, and the at least one dummy solder DB1b includes a plurality of dummy solders DB1b disposed at each of four corners of the quadrangular shape of the surface of the main body. Furthermore, Shi (see, e.g., fig. 1A) also shows that the surface 110a has a quadrangular shape, and the at least one dummy solder 150 includes a plurality of dummy solders 150 disposed at each of four corners of the quadrangular shape of the surface of the main body.
With regards to other language recited in claim 3, see the comments stated above in paragraph 10. For the express purposes of examination, the claim is interpreted such that the plurality of dummy solders in its totality has elements disposed at each of four corners of the quadrangular shape.
Regarding claim 4, Choi (see, e.g., figs. 1 and 6-7) shows that the surface of the main body has a quadrangular shape, and the at least one dummy solder DB1b includes a plurality of dummy solders DB1b disposed at each of four sides of the quadrangular shape of the surface of the main body. Furthermore, Shi (see, e.g., fig. 1A) also shows that the surface 110a has a quadrangular shape, and the at least one dummy solder 150 includes a plurality of dummy solders 150 disposed at each of four sides of the quadrangular shape of the surface of the main body.
With regards to other language recited in claim 4, see the comments stated above in paragraph 11. For the express purposes of examination, the claim is interpreted such that the plurality of dummy solders in its totality has elements disposed at each of four sides of the quadrangular shape.
Regarding claim 5, Choi (see, e.g., figs. 1 and 6-7 and pars.0076-0078) shows that the at least one dummy solder DB1b comprises a plurality of dummy solders DB1b, a shape and size of which is the same as a shape and size of a solder bump SB1a of the plurality of solder bumps SB1a.
However, it is noted that the specification fails to provide teachings about the criticality of having the at least one dummy solder having a shape and size of which is the same as a shape and size of a solder bump as claimed in the instant application.
Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the dummy solder or solder bump shape and size disclosed by Huang as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, and the particular dummy solder or solder bump shape and size claimed by applicant is nothing more than one of numerous dummy solder or solder bump shapes and sizes that a person having ordinary skill in the art will find obvious to provide using routine experimentation as a matter of choice or based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976).
Regarding claim 6, Choi (see, e.g., figs. 1 and 6-7) shows that:
each of the connection terminals LSP2/SP1a includes a connection pad LSP2 and a conductive metal post SP1a protruding from the connection pad, and each of the solder bumps SB1a is disposed on a respective conductive metal post; and
a plurality of dummy connection terminals LDP2b/DP1b having the same structure as the connection terminals are disposed on the surface of the main body at a positions corresponding to the plurality of dummy solders DB1b, and each of the plurality of dummy solders is disposed on a respective metal post DP1b of the dummy connection terminals
With regards to other language recited in claim 6, see the comments stated above in paragraph 12. For the express purposes of examination, the claim is interpreted such that the limitation “the connection terminals” corresponds to the connection terminals upon which a solder bump array is disposed.
Regarding claim 11, Choi (see, e.g., figs. 1 and 6-7) shows that the surface of the main body 100/200/300/400 is a surface of the at least one semiconductor chip 200.
Regarding claim 12, Shi (see, e.g., pars.0037/ll.8 and 0040/ll.15) shows that the first melting point Second Temperature is 210 °C or more, and the second melting point First Temperature is 190 °C or less.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66. Similarly, a prima facie case of obviousness exists where the claimed ranges and prior art ranges do not overlap but are close enough that one skilled in the art would have expected them to have the same properties. Titanium Metals Corp. of Amer.v.Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985).
"[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See also In re Harris, 409 F.3d 1339, 74 USPQ2d 1951 (Fed. Cir. 2005).
Nevertheless, differences in temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). Since the applicant has not established the criticality of the claimed temperatures, i.e., 210 °C or more and 190 °C or less, it would have been obvious to one of ordinary skill in the art to use these values in the device of Huang/Shi/Araki. See also the comments stated above in paragraphs 27-32 with respect to claim 12 regarding criticality, which are considered to be repeated here.
Regarding claim 13, Shi (see, e.g., par.0023/ll.15) shows that the at least one dummy solder 150 is made of Sn-Bi-X, where is X is Ag or Fe.
With regards to other language recited in claim 13, see the comments stated above in paragraph 12.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2020/0203299) in view of Choi, Shi, and Araki.
Regarding claim 15, Huang (see, e.g., figs. 3A, 3A-1, and 3B) shows most aspects of the instant invention, including a semiconductor package 300 comprising:
at least one semiconductor chip 120;
a chip carrier 110c including a first surface (surface of 110c closest to 120) to which the at least one semiconductor chip is bonded; and
a mold 150 that seals the at least one semiconductor chip and the first surface with a mold material;
wherein:
the chip carrier includes a redistribution layer 117, a plurality of first connection terminals 115 for connection with the at least one semiconductor chip, and a plurality of second connection terminals 172/10/118a on a second surface opposite to the first surface for connection with a device 190;
the plurality of first connection terminals 115 are electrically connected to terminals 130 of the semiconductor chip (see, e.g., pars.0026-0027, 0042, and 0075/ll.6-7);
each of the second connection terminals includes a connection pad 118a connected to the redistribution layer and a metal post 172 or 172/10 disposed on the connection pad, and a solder bump 182b having a diameter is disposed on each metal post (see, e.g., par.0037);
the chip carrier includes at least two dummy solders 184b at an outside of a perimeter of the plurality of second connection terminals on the second surface; and
the solder bumps have a first melting point, and the at least two dummy solders have a second melting point (see, e.g., par.0045/ll.1-4)
Huang teaches most aspects of the instant invention, including that a mold seals the at least one semiconductor chip and the first surface with a polymer material (see, e.g., par.0032). Huang, however, fails to explicitly specify that the mold is a resin mold sealing the at least one semiconductor chip and the first surface with specifically a resin material. Choi, in the same field of endeavor and in a similar device to Huang, teaches resin mold and resin material to be equivalent to and interchangeable with polymer mold and polymer material for use in sealing at least one semiconductor chip and a first surface in a semiconductor package comprising semiconductor chips, dummy bumps, solder bumps, and other features similar to Huang (see, e.g., Choi: fig. 1 and par.0074).
Choi is evidence showing that one of ordinary skill in the art would appreciate that a mold comprising a resin material would be equivalent to a mold comprising a polymer material, and that such differences would result in no unexpected changes in the performance of the semiconductor package of Huang. That is, the mold structures of both Huang and Choi would yield the predictable result of providing an insulating material capable of encapsulating and separating conductive and/or solder-including features in a semiconductor package.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Huang’s mold comprise a resin material, as taught by Choi, or a polymer, as taught by Huang, because these were recognized as equivalents in the semiconductor art, and selecting among known equivalents for their known intended use would be within the level of ordinary skill in the art. Furthermore, both mold structures would yield the predictable result of providing an insulating material capable of encapsulating and separating conductive and/or solder-including features in a semiconductor package. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Furthermore, although Huang shows that the solder bump has a diameter, Huang fails to explicitly specify that the solder bump has a diameter of 10 to 30 µm. Choi, in the same field of endeavor and in a similar package to Huang, teaches that solder bumps may have a diameter in the range of 10 to 30 µm, and further teaches that having a solder bump diameter in such a range (e.g., 15 µm) ensures that the solder bumps do not occupy too much area whilst suppressing the electrical resistance of separate conductive components in the package (see, e.g., Choi: par.0045).
Accordingly, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Huang’s solder bump have a diameter of 10 to 30 µm, as taught by Choi, so as to optimize the area consumed by the solder bumps while suppressing the electrical resistance of separate conductive components in Huang’s package.
Moreover, Huang teaches that that the solder bumps have a first melting point and the at least two dummy solders have a second melting point, that Huang’s package employs soldering processes, that Huang’s dummy solders and solder bumps are each directly physically coupled to respective underlying conductive layers in a device, and that melting points may vary within Huang’s package (see, e.g., pars.0045/ll.1-4, 0056/ll.1-4, and 0070). Huang, however, fails to specify that the second melting point is lower than the first melting point so that when heated the at least two dummy solder melts before the solder bumps to generate a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process.
Shi, in the same field of endeavor and in a similar device to Huang, teaches a device wherein a plurality of solder bumps 140 of a solder bump array have a first melting point Second Temperature (see, e.g., par.0023/ll.16-18 and 0040/ll.13-15), and at least two dummy solders 150 have a second melting point First Temperature lower than the first melting point (see, e.g., pars.0023/ll.16-18, 0037/ll.1-7, and 0040/ll.13-15) so that when heated, the at least two dummy solders melt before the solder bumps to generate a force in a direction in which the plurality of solder bumps contact connection terminals 240 of a device 200 by surface tension during a soldering process (see, e.g., Shi: figs. 3-5 and pars.0038/ll.13-23, 0050/ll.13-19, and 0054/ll.1-9). Shi teaches that such a difference in melting points and melting times improves alignment and attachment of the connection terminals of the device to the plurality of solder bumps (see, e.g., pars.0050/ll.13-19 and 0054). Furthermore, Araki, also in the same field of endeavor and in a similar device to Huang, similarly teaches a device having a plurality of solder bumps of a solder bump array having a first melting point and a dummy solder having a second melting point lower than the first melting point so that when heated the dummy solder melts before the solder bumps to generate a force in a direction in which the plurality of solder bumps contact connection terminals of a device by surface tension during a soldering process (see, e.g., Araki: figs. 9-11 and pars.0011 and 0040). Araki teaches that such a connection process suppresses positional deviation, significantly improves mounting time, and improves alignment and attachment between the connection terminals of the device and the plurality of solder bumps (see, e.g., Araki: pars.0011 and 0040).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the solder bumps have a first melting point, and the at least two dummy solders have a second melting point lower than the first melting point so that when heated, the at least two dummy solders melt before the solder bumps and generate to force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process, as taught by Shi and Araki, so as to suppress positional deviation, significantly improve mounting time, and improves alignment and attachment between the connection terminals of the device and the plurality of solder bumps in Huang’s package.
In reference to the claim language pertaining to “generat[ing] a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process”, the claiming of a new use, new function, or unknown property which is inherently present in the prior art does not necessarily make the claim patentable. In re Best, 195 USPQ 430, 433 (CCPA 1977) and In re Swinehart, 439 F. 2d 210, 169 USPQ 226 (CCPA 1971); please also see MPEP § 2112). Since Huang/Choi/Shi/Araki shows all the features of the claimed invention, the characteristic of “generat[ing] a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process” is an inherent property of Huang/Choi/Shi/Araki.
In other words, the specific claim limitation of “generat[ing] a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process” is a property of the dummy solder component of Huang/Choi/Shi/Araki’s device.
Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best, 562 F.2d at 1255, 195 USPQ at 433. See also Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985).
In the instant case, Shi and Araki acknowledge the presence and effects of surface tension and teach the same solder bump and dummy solder melting points/processes as recited in the claim, therefore, the priorly melted dummy solders will “generate force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process” also recited in the claim.
Accordingly and nevertheless, is noted that Huang/Choi/Shi/Araki shows all structural aspects of the semiconductor package according to the claimed invention (see paragraphs 91-103 above), and that the method steps of having “when heated, the at least two dummy solders melt before the solder bumps to generate a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process” are intermediate steps that do not affect the structure of the final device.
Nevertheless, differences in diameter will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). Since the applicant has not established the criticality of the claimed diameter, i.e., a diameter of 10 to 30 µm, it would have been obvious to one of ordinary skill in the art to use these values in the device of Huang/Choi/Shi/Araki. See also the comments stated above in paragraphs 27-32 with respect to claim 12 regarding criticality, which are considered to be repeated here.
Regarding claim 16, Choi (see, e.g., figs. 1 and 6-7) shows that:
the chip carrier 200 further includes a plurality of dummy connection terminals UDP1b/DP1b/DB1b/LDP2b having the same structure as the second connection terminals USP1/SP1/SB1/LSP2, wherein the plurality of dummy connection terminals are located outside of the plurality of second terminals on the second surface and are arranged point-symmetrically about a center of the solder bumps SB1; and
the at least two dummy solders DB1b have the same size and shape as the solder bumps SB1 and are provided on metal posts DP1b of the dummy connection terminals (see, e.g., fig. 1 and pars.0076-0078)
However, it is noted that the specification fails to provide teachings about the criticality of having the at least two dummy solders having the same size and shape as the solder bumps as claimed in the instant application.
Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the dummy solder or solder bump shape and size disclosed by Huang as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, and the particular dummy solder or solder bump shape and size claimed by applicant is nothing more than one of numerous dummy solder or solder bump shapes and sizes that a person having ordinary skill in the art will find obvious to provide using routine experimentation as a matter of choice or based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976).
With regards to other language recited in claim 16, see the comments stated above in paragraph 14.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Shi and Araki.
Regarding claim 15, Choi (see, e.g., figs. 1 and 6-7) shows most aspects of the instant invention, including a semiconductor package 1000a comprising:
at least one semiconductor chip 300;
a chip carrier 200 including a first surface to which the at least one semiconductor chip is bonding;
a resin mold 510 that seals the at least one semiconductor chip and the first surface with a resin material;
wherein:
the chip carrier 200 includes a redistribution layer (unlabeled, shown to include 230), a plurality of first connection terminals USP2/SB2/SP2 for connection with the at least one semiconductor chip 300, and a plurality of second connection terminals USP1/SP1/SB1/LSP2 on a second surface opposite to the first surface for connection with a device 100;
the plurality of second connection terminals are electrically connected to terminals (e.g., LSP3) of the semiconductor chip (see, e.g., pars.0065 and 0090);
each of the second connection terminals includes a connection pad LSP2 connected to the redistribution layer (unlabeled, shown to include 230) and a metal post SP1 disposed on the connection pad, and a solder bump SB1 having a diameter of 10 to 30 µm disposed on each metal post (see, e.g., pars.0045 and 0078); and
the chip carrier includes at least two dummy solders DB1b at an outside of a perimeter of the plurality of second connection terminals on the second surface
wherein:
the first solder bumps SB1 have a first melting point and the at least two dummy solder DB1 have a second melting point, wherein it is noted that melting points are inherent properties of solder materials
Choi shows most aspects of the instant invention, and further teaches that a soldering process may be performed to connect the device to the chip carrier (see, e.g., pars.0087 and 0090). Choi, however, fails to specify that the second melting point is lower than the first melting point so that when heated the at least two dummy solder melts before the solder bumps to generate a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process.
Shi, in the same field of endeavor and in a similar device to Choi, teaches a device wherein a plurality of solder bumps 140 of a solder bump array have a first melting point Second Temperature (see, e.g., par.0023/ll.16-18 and 0040/ll.13-15), and at least two dummy solders 150 have a second melting point First Temperature lower than the first melting point (see, e.g., pars.0023/ll.16-18, 0037/ll.1-7, and 0040/ll.13-15) so that when heated, the at least two dummy solders melt before the solder bumps to generate a force in a direction in which the plurality of solder bumps contact connection terminals 240 of a device 200 by surface tension during a soldering process (see, e.g., Shi: figs. 3-5 and pars.0038/ll.13-23, 0050/ll.13-19, and 0054/ll.1-9). Shi teaches that such a difference in melting points and melting times improves alignment and attachment of the connection terminals of the device to the plurality of solder bumps (see, e.g., pars.0050/ll.13-19 and 0054). Furthermore, Araki, also in the same field of endeavor and in a similar device to Choi, similarly teaches a device having a plurality of solder bumps of a solder bump array having a first melting point and a dummy solder having a second melting point lower than the first melting point so that when heated the dummy solder melts before the solder bumps to generate a force in a direction in which the plurality of solder bumps contact connection terminals of a device by surface tension during a soldering process (see, e.g., Araki: figs. 9-11 and pars.0011 and 0040). Araki teaches that such a connection process suppresses positional deviation, significantly improves mounting time, and improves alignment and attachment between the connection terminals of the device and the plurality of solder bumps (see, e.g., Araki: pars.0011 and 0040).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the solder bumps have a first melting point, and the at least two dummy solders have a second melting point lower than the first melting point so that when heated, the at least two dummy solders melt before the solder bumps and generate to force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process, as taught by Shi and Araki, so as to suppress positional deviation, significantly improve mounting time, and improves alignment and attachment between the connection terminals of the device and the plurality of solder bumps in Choi’s package.
In reference to the claim language pertaining to “generat[ing] a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process”, the claiming of a new use, new function, or unknown property which is inherently present in the prior art does not necessarily make the claim patentable. In re Best, 195 USPQ 430, 433 (CCPA 1977) and In re Swinehart, 439 F. 2d 210, 169 USPQ 226 (CCPA 1971); please also see MPEP § 2112). Since Choi/Shi/Araki shows all the features of the claimed invention, the characteristic of “generat[ing] a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process” is an inherent property of Choi/Shi/Araki.
In other words, the specific claim limitation of “generat[ing] a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process” is a property of the dummy solder component of Choi/Shi/Araki’s device.
Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best, 562 F.2d at 1255, 195 USPQ at 433. See also Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985).
In the instant case, Shi and Araki acknowledge the presence and effects of surface tension and teach the same solder bump and dummy solder melting points/processes as recited in the claim, therefore, the priorly melted dummy solders will “generate force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process” also recited in the claim.
Accordingly and nevertheless, is noted that Choi/Shi/Araki shows all structural aspects of the semiconductor package according to the claimed invention (see paragraphs 111-118 above), and that the method steps of having “when heated, the at least two dummy solders melt before the solder bumps to generate a force in a direction in which the plurality of solder bumps contact connection terminals of the device by surface tension during a soldering process” are intermediate steps that do not affect the structure of the final device.
Nevertheless, differences in diameter will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). Since the applicant has not established the criticality of the claimed diameter, i.e., a diameter of 10 to 30 µm, it would have been obvious to one of ordinary skill in the art to use these values in the device of Choi/Shi/Araki. See also the comments stated above in paragraphs 27-32 with respect to claim 12 regarding criticality, which are considered to be repeated here.
Regarding claim 16, Choi (see, e.g., figs. 1 and 6-7) shows that:
the chip carrier 200 further includes a plurality of dummy connection terminals UDP1b/DP1b/DB1b/LDP2b having the same structure as the second connection terminals USP1/SP1/SB1/LSP2, wherein the plurality of dummy connection terminals are located outside of the plurality of second terminals on the second surface and are arranged point-symmetrically about a center of the solder bumps SB1; and
the at least two dummy solders DB1b have the same size and shape as the solder bumps SB1 and are provided on metal posts DP1b of the dummy connection terminals (see, e.g., fig. 1 and pars.0076-0078)
With regards to other language recited in claim 16, see the comments stated above in paragraph 14.
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Shi/Alley in view of Imura (JP 4677152 B2).
Regarding claim 2, Shi/Alley shows most aspects of the instant invention (see paragraphs 18-0 above). Furthermore, Shi (see, e.g., fig. 1A) shows that the at least one dummy solder 150 is disposed at an outside of the solder bump array. Shi, however, fails to specify that the dummy solder may be disposed at an outside of a perimeter of the solder bump array. Imura, in the same field of endeavor and in a similar device to Shi/Alley, teaches that disposing at least one dummy solder at an outside of a perimeter of a solder bump array disperses external stress, improves bonding strength, and prevents peeling off of the solder bump array (see, e.g., Imura: fig. 9 and pars.0021 and 0034).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the at least one dummy solder disposed at an outside of a perimeter of the solder bump array, as taught by Imura, so as to disperse external stress, improve bonding strength, and prevent peeling off of the solder bump array in Shi/Alley’s package.
Regarding claim 3, Imura (see, e.g., fig. 9) shows that the surface of the main body 101 has a quadrangular shape, and the at least one dummy solder 105 includes a plurality of dummy solders 105 disposed at each of four corners of the quadrangular shape of the surface of the main body. Furthermore, Shi (see, e.g., fig. 1A) shows that the surface 110a has a quadrangular shape, and the at least one dummy solder 150 includes a plurality of dummy solders 150 disposed at each of four corners of the quadrangular shape of the surface of the main body.
With regards to other language recited in claim 3, see the comments stated above in paragraph 10. For the express purposes of examination, the claim is interpreted such that the plurality of dummy solders in its totality has elements disposed at each of four corners of the quadrangular shape.
Regarding claim 4, Imura (see, e.g., fig. 9) shows that the surface of the main body 101 has a quadrangular shape, and the at least one dummy solder 105 includes a plurality of dummy solders 105 disposed at each of four sides of the quadrangular shape of the surface of the main body. Furthermore, Shi (see, e.g., fig. 1A) shows that the surface 110a has a quadrangular shape, and the at least one dummy solder 150 includes a plurality of dummy solders 150 disposed at each of four sides of the quadrangular shape of the surface of the main body.
With regards to other language recited in claim 4, see the comments stated above in paragraph 11. For the express purposes of examination, the claim is interpreted such that the plurality of dummy solders in its totality has elements disposed at each of four sides of the quadrangular shape.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Shi/Alley in view of Jufeng [Shenzhen Jufeng Solder Co., Ltd. (2022, October 18). Sn64Bi35Ag1 Mid Temperature Lead Free Solder Paste. JFSolder.] and BBIEN [Shenzhen BBIEN Technology Co.,Ltd . (2022, March 30). 179degree tin bismuth silver solder paste Sn64Bi35Ag1. BBIENSolder.].
Regarding claim 14, Shi/Alley shows most aspects of the instant invention (see paragraphs 18-0 and 27-34 above). Furthermore, Shi (see, e.g., par.0023/ll.15) shows that the at least one dummy solder 150 is made of Sn-Bi-Ag, wherein an Ag or Fe content is 6 wt% or less. Shi, however, fails to explicitly specify that a Bi content is 35 to 40 wt%. Jufeng teaches a solder made of Sn-Bi-Ag, wherein a Bi content is 35 to 40 wt% and an Ag content is 6 wt% or less (see, e.g., Jufeng: par.01). Jufeng teaches that such a solder material has a melting point in the same range as Shi, wherein such a solder material additionally boasts an outstanding wetting property and soldering performance (see, e.g., Jufeng: pars.01-02). BBIEN similarly teaches an Sn-Bi-Ag solder material having a Bi content is 35 to 40 wt% and an Ag or Fe content is 6 wt% or less and a melting point in the range of Shi, wherein BBIEN teaches that such a solder composition can be applied to reflow soldering and additionally asserts excellent wetting, high oxidation resistance, excellent soldering performance, and high reflow yield (see, e.g., BBIEN: pars.0028-0030).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to employ the solder composition of Jufeng and BBIEN in the dummy solder of Shi, inherently having a Bi content of 35 to 40 wt%, as taught by Jufeng and BBIEN, so as to utilize a solder composition already in Shi’s melting point and Ag wt% ranges and having excelling wetting, soldering performance, high oxidation resistance, and high reflow yield.
Nevertheless, differences in concentration or wt% will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). Since the applicant has not established the criticality of the claimed concentrations or wt%, i.e., a Bi content of 35 to 40 wt% and an Ag or Fe content of 6 wt% or less, it would have been obvious to one of ordinary skill in the art to use these values in the device of Huang/Shi/Araki. See also the comments stated above in paragraphs 27-32 with respect to claim 12 regarding criticality, which are considered to be repeated here.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Huang/Shi/Araki in view of Jufeng and BBIEN.
Regarding claim 14, Huang/Shi/Araki shows most aspects of the instant invention (see paragraphs 37-44 and 57-62 above). Furthermore, Shi (see, e.g., par.0023/ll.15) teaches that the at least one dummy solder 150 is made of Sn-Bi-Ag, wherein an Ag or Fe content is 6 wt% or less. Huang/Shi/Araki, however, fails to explicitly specify that a Bi content is 35 to 40 wt%. Jufeng teaches a solder made of Sn-Bi-Ag, wherein a Bi content is 35 to 40 wt% and an Ag content is 6 wt% or less (see, e.g., Jufeng: par.01). Jufeng teaches that such a solder material has a melting point in the same range as Shi, wherein such a solder material additionally boasts an outstanding wetting property and soldering performance (see, e.g., Jufeng: pars.01-02). BBIEN similarly teaches an Sn-Bi-Ag solder material having a Bi content is 35 to 40 wt% and an Ag or Fe content is 6 wt% or less and a melting point in the range of Shi, wherein BBIEN teaches that such a solder composition can be applied to reflow soldering and additionally asserts excellent wetting, high oxidation resistance, excellent soldering performance, and high reflow yield (see, e.g., BBIEN: pars.0028-0030).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to employ the solder composition of Jufeng and BBIEN in the dummy solder of Huang/Shi/Araki, inherently having a Bi content of 35 to 40 wt%, as taught by Jufeng and BBIEN, so as to utilize a solder composition already in Huang/Shi/Araki’s melting point and Ag wt% ranges and having excelling wetting, soldering performance, high oxidation resistance, and high reflow yield.
Nevertheless, differences in concentration or wt% will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). Since the applicant has not established the criticality of the claimed concentrations or wt%s, i.e., a Bi content of 35 to 40 wt% and an Ag or Fe content of 6 wt% or less, it would have been obvious to one of ordinary skill in the art to use these values in the device of Huang/Shi/Araki. See also the comments stated above in paragraphs 27-32 with respect to claim 12 regarding criticality, which are considered to be repeated here.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Choi/Shi/Araki in view of Jufeng and BBIEN.
Regarding claim 14, Choi/Shi/Araki shows most aspects of the instant invention (see paragraphs 64-72 and 84-89 above). Furthermore, Shi (see, e.g., par.0023/ll.15) teaches that the at least one dummy solder 150 is made of Sn-Bi-Ag, wherein an Ag or Fe content is 6 wt% or less. Choi/Shi/Araki, however, fails to explicitly specify that a Bi content is 35 to 40 wt%. Jufeng teaches a solder made of Sn-Bi-Ag, wherein a Bi content is 35 to 40 wt% and an Ag content is 6 wt% or less (see, e.g., Jufeng: par.01). Jufeng teaches that such a solder material has a melting point in the same range as Shi, wherein such a solder material additionally boasts an outstanding wetting property and soldering performance (see, e.g., Jufeng: pars.01-02). BBIEN similarly teaches an Sn-Bi-Ag solder material having a Bi content is 35 to 40 wt% and an Ag or Fe content is 6 wt% or less and a melting point in the range of Shi, wherein BBIEN teaches that such a solder composition can be applied to reflow soldering and additionally asserts excellent wetting, high oxidation resistance, excellent soldering performance, and high reflow yield (see, e.g., BBIEN: pars.0028-0030).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to employ the solder composition of Jufeng and BBIEN in the dummy solder of Choi/Shi/Araki, inherently having a Bi content of 35 to 40 wt%, as taught by Jufeng and BBIEN, so as to utilize a solder composition already in Choi/Shi/Araki’s melting point and Ag wt% ranges and having excelling wetting, soldering performance, high oxidation resistance, and high reflow yield.
Nevertheless, differences in concentration or wt% will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). Since the applicant has not established the criticality of the claimed concentrations or wt%s, i.e., a Bi content of 35 to 40 wt% and an Ag or Fe content of 6 wt% or less, it would have been obvious to one of ordinary skill in the art to use these values in the device of Choi/Shi/Araki. See also the comments stated above in paragraphs 27-32 with respect to claim 12 regarding criticality, which are considered to be repeated here.
Claims 16 is rejected under 35 U.S.C. 103 as being unpatentable over Huang/Choi/Shi/Araki in view of Kawashima (JP 2005012065 A).
Regarding claim 16, Huang/Choi/Shi/Araki shows most aspects of the instant invention (see paragraphs 91-105 above). Huang (see, e.g., figs. 3A, 3A-1, and 3B) further shows that:
the chip carrier 110c further includes a plurality of dummy connection terminals 174c/10/118b having the same structure as the second connection terminals 172/10/118a, wherein the plurality of dummy connection terminals are located outside of the plurality of second terminals on the second surface and are arranged point-symmetrically about a center of the solder bumps 182b; and
the at least two dummy solders 184b have a same size and shape as the solder bumps 182b and are provided on metal posts 174c of the dummy connection terminals pars.0066 and 0068/ll.4-6
Although Huang teaches most aspects of the instant invention, Huang fails to specify that the at least two dummy solders have the same size and shape as the solder bumps. Kawashima, in the same field of endeavor and having a similar structure to Huang, teaches that dummy solders and solder bumps may comprise a variety of shapes and sizes and that when dummy solders have the same size and shape as solder bumps, uniformity of the surface they are disposed on is maintained and stress may be suppressed from being concentrated on specific regions of the overall device (see, e.g., Kawashima: pars.0015-0016).
Kawashima is evidence showing that one of ordinary skill in the art would appreciate that dummy solders having the same size and shape as solder bumps would be equivalent to dummy solders not having the same size and shape as solder bumps, and that such differences would result in no unexpected changes in the performance of the package of Huang/Choi/Shi/Araki. That is, the solder bump and dummy solder shapes and sizes of both Huang and Kawashima would yield the predictable result of providing suitably-formed solder bumps and dummy solders capable of electrical interconnection with other conductive features in a semiconductor package or electrical isolation from conductive features in a semiconductor package.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either dummy solders having the same size and shape as solder bumps, as taught by Kawashima, or dummy solders not having the same size and shape as solder bumps, as taught by Huang, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitably-formed solder bumps and dummy solders capable of electrical interconnection with other conductive features in a semiconductor package or electrical isolation from conductive features in a semiconductor package. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Moreover, Kawashima is evidence that it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the at least two dummy solders have the same size and shape as the solder bumps, e.g., by having the solder bumps comprise the same quarter-circle shape and size of the dummy solders of Huang, as taught by Kawashima, so as to maintain uniformity of the second surface and suppress stress from being concentrated on specific regions of Huang’s overall package.
However, it is noted that the specification fails to provide teachings about the criticality of having the at least two dummy solders having the same size and shape as the solder bumps as claimed in the instant application.
Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the dummy solder or solder bump shape and size disclosed by Huang as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, and the particular dummy solder or solder bump shape and size claimed by applicant is nothing more than one of numerous dummy solder or solder bump shapes and sizes that a person having ordinary skill in the art will find obvious to provide using routine experimentation as a matter of choice or based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976).
With regards to other language recited in claim 16, see the comments stated above in paragraph 14.
Conclusion
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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