Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/15/26 has been entered.
This office action has been issued in response to the amendment filed 3/27/26. Claims 10-29 are pending in this application. Applicant's arguments have been carefully considered, but are not all persuasive. The examiner appreciates Applicant's effort to distinguish over the cited prior art by amending the claims in an attempt to distinguish or clarify the claimed invention, however, upon further consideration and/or search, the claims remain unpatentable over the cited prior art for the reasons articulated in the “response to arguments” section below. All claims pending in the instant application remain rejected and clarification and/or elaboration regarding why the claims are not in condition for allowance will hereafter be provided in order to efficiently further prosecution.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 10, 19, 28 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention. The claim limitation: “wherein the first memory controller services the memory requests without monitoring, coordinating, or responding to a power state or a memory-transaction activity state of the second master circuit” as currently drafted, is not supported by the original disclosure because the original disclosure does not appear to teach that the memory controller does not monitor, coordinate with nor respond to any power state of memory-transaction activity of another master circuit. Rather the original disclosure describes a memory controller in a power domain separate & independent from the power domains of master circuits. Specifically, [0032] of the specification teaches: “[0032] FIG. 2 is flowchart for power management and memory access in an IC, in accordance with some examples of the present disclosure. The IC has multiple master modules, such as a processor system, programmable logic, accelerator, or another module. The IC further has a memory controller that the master modules may use to access memory, which memory may be on-chip or on a separate IC. The master modules are in one or more power domains on the IC (and in some instances, each master module is in a dedicated power domain separate from other domains of the other master modules), and the memory controller is in a power domain on the IC that is separate and independent from the one or more power domains in which the master modules are disposed. The memory controller is not included or disposed in a master module. For example, the memory controller can be in a physical block dedicated to the memory controller. Power modes of the master modules may be controlled, such as by a management unit coordinating with the master modules. Each master module can have different power modes, such as suspended mode, powered down mode, active mode, powered up, etc., into which the respective master module may be selectively entered based on the control of the master module.. As such the new limitation(s) amount to new matter. Dependent claims 11-18,20-27, 29 are rejected on dependency merits.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 10-29 are rejected under 35 U.S.C. 103 as being unpatentable over Rakshani et al. (US PGPUB # 20100005328) in view of Man et al (US PGPUB # 20140089688) further in view of Kardach (US PGPUB # 20030163745). With respect to independent claim 10, 19, 28 Rakshani/Man/Kardach discloses: A method of operating an integrated circuit [integrated circuit (IC) and means for operating - Rakshani fig 2, paragraph 0083-0087], the method comprising:
selectively entering a first master circuit and a second master circuit [multiple functional units (master circuits) occupy different power “islands” aka domains on a chip/IC – Rakshani fig 2, paragraph 0083-0087 in view of 0037-0039] of a plurality of master circuits of the integrated circuit into one of a plurality of power modes [power states – Rakshani 0063-0065; different functional blocks/clusters may selectively enter into different power modes/states – Rakshani 0077, claims 1 & 9]; and
accessing memory by the first master circuit via a first memory controller of the integrated circuit independent of the selected one of the plurality of power modes of the second master circuit [Rakshani does not explicitly teach this limitation. However, it is taught by Man as: SOC/memory-controller architecture with cores 410 as masters and an IC memory controller 440 in an independent domain – Man fig 4] [die includes memory controller & memory and may be in its own (power) domain - Man 0012] [Rakshani teaches that a memory controller, for example, can be the only functional unit in a power island, Rakshani implicitly teaches and strongly suggests that another functional unit, such as the a processor/core/CPU and a programmable logic circuit which are also disposed in their own separate power islands, will access memory via this memory controller in a separate power island/domain - Rakshani fig 2, paragraph 0083-0087 in view of 0037-0039. This understanding is supported at least by 0012 of Man which teaches that a processor package, or integrated circuit, can include multiple semiconductor die, including a CPU/processing system die, a memory & memory controller die, and other/additional/programmable circuitry logic die, with each die operating in its own power domain, disclosed as “each die may also be considered an independent domain” – as such, the CPU die or the other/additional/programmable circuitry logic die would access memory via the memory & memory controller die which would reside in its own power domain - Man 0012],
wherein the first master circuit is configured to access memory while the second master circuit is in a different power mode and is inactive with respect to memory transactions [Rakshani/Man does not explicitly teach this limitation. Nevertheless in the same field of endeavor Kardach teaches means for reducing power in a computer system with bus mastering devices (master circuits) wherein a bus master is allowed to access memory while a CPUis inactive with respect to memory transactions – Kardach 0011, 0015, 0023, claim 11], and wherein the first memory controller is operable to service memory requests from one or more active master circuits without synchronizing power states across the plurality of master circuits [Rakshani does not explicitly disclose a memory controller operable to service memory requests from one or more active master circuits without synchronizing power states across the plurality of master circuits. 0012 of Man teaches that a processor package, or integrated circuit, can include multiple semiconductor die, including a CPU/processing system die, a memory & memory controller die, and other/additional/programmable circuitry logic die, with each die operating in its own power domain, disclosed as “each die may also be considered an independent domain” – as such, the CPU die or the other/additional/programmable circuitry logic die would access memory via the memory & memory controller die which would reside in its own power domain and Man’s integrated memory controller 440 is located in the uncore and handles memory requests from cores in different domains, the PCU manages power per domain, and not by forcing all cores into a common state before servicing memory - Man 0012, 0039-0040] [Kardach claim 4, 11, 14 teaches the memory subsystem handling/servicing bus master access requests without waking the processor or synchronizing its power state] [separate and independent power domains - Rakshani 0084; Rakshani fig 2 teaches functional unit 1 in power island 1 may be a memory controller and memory unit comprised of cluster 115.1 as a memory controller (in view of Rakshani 0096 in view of 0037-0038) operable to access a functional unit/cluster which may include a memory unit 215.2 or 215.3 so that a functional unit 2 or 3 in power island 2 or 3 requiring access to memory in functional unit 1 in power island 1 would need to make use of a memory controller in power island 1 to access a memory in power island 1] ,
wherein the first memory controller services the memory requests without monitoring, coordinating, or responding to a power state or a memory-transaction activity state of the second master circuit [This appears to be a limitation that is not supported by the original disclosure, as such a 112 new matter rejection has been made above. Furthermore the combination of Rakshani/Man/Kardach renders this limitation obvious to the extent that Rakshani teaches independent per-island power control and that the memory controller and master circuits reside in separate/independent power domains, Man likewise teaches per-domain controllers and independent power budgets, and Kardach further teaches bus master accesses being handled without waking or snooping the CPU, without the controller responding to the CPU’s power or activity state - Kardach claim 4, 11, 14 teaches the memory subsystem handling/servicing bus master access requests without waking the processor or synchronizing its power state] [separate and independent power domains - Rakshani 0084; Rakshani fig 2 teaches functional unit 1 in power island 1 may be a memory controller and memory unit comprised of cluster 115.1 as a memory controller (in view of Rakshani 0096 in view of 0037-0038) operable to access a functional unit/cluster which may include a memory unit 215.2 or 215.3 so that a functional unit 2 or 3 in power island 2 or 3 requiring access to memory in functional unit 1 in power island 1 would need to make use of a memory controller in power island 1 to access a memory in power island 1].
Rakshani does not explicitly disclose accessing memory by the first master circuit via a first memory controller of a integrated circuit independent of a selected one of the plurality of power modes of the second master circuit although it appears that Rakshani suggests this limitation as indicated in above
Nevertheless, in the same field of endeavor Man teaches sharing power between domains in a processor package (Man title) wherein multiple (power) domains exist in an IC or integrated circuit, also known as a processor package, and wherein different (master & memory control) circuits are disposed in various power domains (Man 0012, 0021). SOC/memory-controller architecture with cores 410 as masters and an IC memory controller 440 in an independent domain – Man fig 4
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to access memory by a first master circuit via a first memory controller of an IC independent of a selected one of a plurality of power modes of a second master circuit in the invention of Rakshani as taught by Man because this would be advantageous for optimizing power sharing/use among functional components in a processor package (Man 0011-0012).
Rakshani/Man does not explicitly teach wherein the first master circuit is configured to access memory while the second master circuit is in a different power mode and is inactive with respect to memory transactions. Nevertheless in the same field of endeavor Kardach teaches means for reducing power in a computer system with bus mastering devices (master circuits) wherein a bus master is allowed to access memory while a CPUis inactive with respect to memory transactions – Kardach 0011, 0015, 0023, claim 11. Therefore Rakshani/Man/Kardach teach all limitations of the instant claim.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to configure a first master circuit to access memory while a second master circuit is in a different power mode and is inactive with respect to memory transactions in the invention of Rakshani/Man as taught by Kardach because this would be advantageous for minimizing power consumption of the memory system (Kardach 0011, 0015).
With respect to dependent claim 11, 20 Rakshani/Man/Kardach discloses wherein the first memory controller is not included in any of the plurality of master circuits [memory controller is in uncore and is not part of the cores – Man fig 4] [functional unit (FU) 1 is not part of FU2…FUn – Rakshani fig 2] [0012 of Man which teaches that a processor package, or integrated circuit, can include multiple semiconductor die, including a CPU/processing system die, a memory & memory controller die, wherein the memory controller is not included in a CPU/processing system die, and other/additional/programmable circuitry logic die, with each die operating in its own power domain, disclosed as “each die may also be considered an independent domain” – as such, the CPU die or the other/additional/programmable circuitry logic die would access memory via the memory & memory controller die which would reside in its own power domain - Man 0012].
With respect to dependent claim 12, 21 Rakshani/Man/Kardach discloses wherein accessing the memory by the first master circuit comprises communicating with the first memory controller via a configurable interconnect network of the integrated circuit [processor package includes interconnect network on the chip/processor package to facilitate communication between functional components - Man 0012, 0021 in view of fig 1] [functional units may include, for example and without limitation, a general purpose processor, a mathematical processor, a state machine, a digital signal processor, a video processor, an audio processor, a logic unit, a logic element, a multiplexer, a demultiplexer, a switching unit, a switching element, an input/output (I/O) element, a peripheral controller, a bus, a bus control – Rakshani 0038].
With respect to dependent claim 13, 22 Rakshani/Man/Kardach discloses wherein the configurable interconnect network is in a power domain separate from the power domain of the first master circuit, the second master circuit, and the first memory controller chip [processor package includes interconnect network on the chip/processor package to facilitate communication between functional components - Man 0012, 0021 in view of fig 1] [functional units may include, for example and without limitation, …. a bus, a bus control – Rakshani 0038; each functional unit occupy different power “islands” aka domains – Rakshani fig 2, paragraph 0083-0087 in view of 0037-0039].
With respect to dependent claim 14, 23 Rakshani/Man/Kardach discloses accessing the memory by the first master circuit via a second memory controller of the integrated circuit and the configurable interconnect network, wherein the second memory controller is in a power domain separate from a power domain of the first master circuit [redundant functional clusters may include second memory control functional unit - Rakshani 0178-0180 in view of Man 0012, 0021; all power domains may be separate/independent – Rakshani fig 2, paragraph 0037-0038, 0049, 0084 in view of Man 0012, 0021 ].
With respect to dependent claim 15, 24 Rakshani/Man/Kardach discloses wherein the power domain of the second memory controller differs from the power domain of the first memory controller [redundant functional clusters may include second memory control functional unit - Rakshani 0178-0180 in view of Man 0012, 0021; all power domains may be separate/independent – Rakshani fig 2, paragraph 0037-0038, 0049, 0084 in view of Man 0012, 0021].
With respect to dependent claim 16, 25 Rakshani/Man/Kardach discloses wherein the power domain of the second master circuit differs from the power domain of the second memory controller [all power domains may be separate/independent – Rakshani fig 2, paragraph 0037-0038, 0049, 0084 in view of Man 0012, 0021].
With respect to dependent claim 18, 27 Rakshani/Man/Kardach discloses wherein the selected one of the plurality of power modes of the first master circuit differs from the selected one of the plurality of power modes of the second master circuit [power states – Rakshani 0063-0065; different functional blocks/clusters may selectively enter into different power modes/states – Rakshani 0077, claims 1 & 9].
With respect to dependent claim 29 Rakshani/Man/Kardach discloses wherein accessing the memory by the first master circuit comprises communication with the first memory controller via a configurable interconnect network of the integrated circuit, and wherein the configurable interconnect network is in a power domain separate from a power domain of each of the first master circuit, the second master circuit, and the first memory controller [Man fig 4] [processor package includes interconnect network on the chip/processor package to facilitate communication between functional components - Man 0012, 0021 in view of fig 1] [functional units may include, for example and without limitation, …. a bus, a bus control – Rakshani 0038; each functional unit occupy different power “islands” aka domains – Rakshani fig 2, paragraph 0083-0087 in view of 0037-0039
Claims 17, 26 are rejected under 35 U.S.C. 103 as being unpatentable over Rakshani/Man/Kardach further in view of Jayasimha (US PGPUB # 20130073878).
With respect to dependent claim 17, 26 Rakshani/Man/Kardach does not explicitly disclose the limitations of the instant claim. Nevertheless in the same field of endeavor Jayasimha teaches an interconnect power manager wherein different/multiple traffic types/classes are handled by virtual paths/routes/channels Therefore Rakshani/Man/Kardach in view of Jayasimha discloses wherein the communication via the configurable interconnect network includes use of at least one of a plurality of virtual channels of a physical channel of the configurable interconnect network [Jayasimha 0079-0081 in view of 0067]. It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to enable handling multiple traffic classes via virtual channels in the invention of Rakshani/Man/Kardach as taught by Jayasimha because this would be advantageous for providing a system designer with finer control over routing traffic between initiators and targets – Jayasimha 0111.
Response to Arguments
Applicant's arguments have been fully considered but are not persuasive in view of the prior art. All claims pending in the instant application remain rejected. Please note that any rejections/objection not maintained from the previous Office Action have been rectified either by applicant's amendment and/or persuasive argument(s).
Regarding applicant’s arguments on page 7-9, that amended limitations are not taught by the cited art [The examiner respectfully submits that amended grounds of rejection necessitated by amendments to the claims have rendered the remarks moot/unpersuasive, particularly in view of what appears to be new matter in the claims and at least for illustrative purposes the application of the combination of prior art including Rakshani/Man/Kardach as integrated into the rationale above. Specifically, it appears that the combination of Rakshani/Man/Kardach teaches the new limitation because Rakshani teaches independent per-island power control and that the memory controller and master circuits reside in separate/independent power domains, Man likewise teaches per-domain controllers and independent power budgets, and Kardach further teaches bus master accesses being handled without waking or snooping the CPU, as such the controller does not respond to the processor power or memory transaction activity state when servicing bus-master requests. In view of the teachings it would have been obvious to one of ordinary skill in the art to implement the memory controller such that it arbitrates and services memory requests solely based on requests from the active masters without additional monitoring or coordination logic tied to the power state of memory transaction activity of inactive masters since any such monitoring or coordination is unnecessary for correct operation and would only add complexity and power overhead].
Remaining arguments are understood to be predicated on the previous arguments being persuasive and thus are unpersuasive at least on dependency merits.
All remarks are understood to have been addressed herein. If any issues remain which may be clarified by the examiner, the applicant is invited to contact the examiner to set up a telephone interview.
When responding to the office action, any new claims and/or limitations should be accompanied by a reference as to where the new claims and/or limitations are supported in the original disclosure.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARWAN AYASH whose telephone number is (571)270-1179. The examiner can normally be reached 9a-530p M-R.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rocio del Mar Perez-Velez can be reached on 571-270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Marwan Ayash/Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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