DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8, and 10-17 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Klair et al., US PGPUB No. 2023/0252212.
In reference to claim 1, Klair teaches a method for verifying functionality of a circuit design, comprising:
performing a test of the circuit design to identify a circuit design error within a first duration of the test (Figure 2, Paragraphs [0027] and [0034] full simulation, user has simulated the circuit design and suspects one or more sub-designs of the circuit design as the source of errors being observed, the time of the full simulation in Figure 2 shows it fully from right to left);
generating waveform data for a plurality of signals of the circuit design, the waveform data comprising values of the plurality of signals, generated from the test (Paragraph [0033], generate a testbench for a sub-design of a circuit design, where the circuit design includes a plurality of sub-designs. The simulation system is capable of generating a testbench for a selected sub-design where the resulting testbench, when executed for a given window of time and independently of the larger circuit design from which the selected sub-design was extracted, will generate output data that matches the output data generated by the sub-design when simulated as part of the larger circuit design);
generating a stimulus file based on the waveform data, the stimulus file comprising the values of a subset of the plurality of signals and configured to be used to simulate the circuit design to reproduce the circuit design error (translating the switching activity 416 from the switching activity file into a vector source file or other format that may be used to drive a testbench. The vector source file, for example, defines the event-based stimuli to be exercised by the sub-design testbench); and
performing one or more first simulations of the circuit design using the stimulus file to reproduce the circuit design error, each performed within a second duration shorter than the first duration (Paragraph [0033] generate output data that matches the output data generated by the sub-design when simulated as part of the larger circuit design. For example, referring to FIGS. 2 and 3, the resulting testbench 1 for sub-design 1 will generate output data (e.g., the waveform corresponding to time window replay 1) that matches the output of sub-design 1 generated during simulation of circuit design 106 for the same window of time, replay 1 being shorter than full simulation).
In reference to claim 2, Klair teaches wherein the circuit design is implemented in a hardware description language (HDL) (Paragraph [0026]); And wherein the performing the test comprises simulating the circuit design in a second simulation, wherein each of the one or more first simulations has a shorter duration than a duration of the second simulation (Figure 2, Paragraph [0033] full simulation is longer than replay 1, 2, and 3).
In reference to claim 3, Klair teaches wherein the performing the test comprises:
synthesizing the circuit design to be implemented in a field-programmable gate array
(FPGA) device; testing the synthesized circuit design in the FPGA device; and obtaining the values of the plurality of signals of the circuit design using a logic analyzer provided in the FPGA device (Paragraph [0089]).
In reference to claim 4, Klair teaches wherein the stimulus file comprises a register transfer level (RTL) verification stimulus of the circuit design (Paragraph [0026])
In reference to claim 5, Klair teaches wherein the performing one or more first simulations of the circuit design using the stimulus file comprises: determining whether or not the one or more first simulations reproduce the circuit design error using the stimulus file; and
modifying the subset of the plurality of signals included in the stimulus file in response to determining that the one or more first simulations do not reproduce the circuit design error using the stimulus file (Paragraph [0063] user may modify the source vector files).
In reference to claim 6, Klair teaches wherein the modifying the subset of the plurality of
signals comprises at least one of: adding one or more signals to the subset of plurality of signals; or removing one or more signals from the subset of plurality of signals (user modifying the source vector files would necessarily include adding or removing signal data)
In reference to claim 7, Klair teaches wherein the generating the waveform data comprises: generating a value changed dump comprising the values of the plurality of signals (Paragraph [0046]).
In reference to claim 8, Klair wherein the stimulus file comprises teaches a first section defining the subset of the plurality of signals; and a second section defining the values of the subset of the plurality of signals in a temporal order for simulating the circuit design in the one or more first simulations (Paragraph [0046]).
In reference to claims 10-17 drawn to a computer system (Klair, Figure 7) for performing all of the functional limitations as found in claims 1-8, the same rejections apply.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Klair et al., US PGPUB No. 2023/0252212.
In reference to claim 9 and 18, Klair teaches claims 1 and 10 respectively above. Klair does not teach modifying the circuit design to correct the circuit design error based on the one or more first simulations. However, correcting circuit design errors based on simulation results by modifying the circuit design is notoriously well known in the art. OFFICIAL NOTICE IS TAKEN. Accordingly, it would have been obvious for one of ordinary skill in the art at the time of invention to modify the circuit design to correct the circuit design error based on the one or more first simulations because error free circuit designs are desirable when producing circuit chips.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON BOWERS whose telephone number is (571)272-1888. The examiner can normally be reached Flex M-F 7am-6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.B/ Examiner, Art Unit 2851
/JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851
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