Prosecution Insights
Last updated: April 19, 2026
Application No. 18/226,321

Semiconductor Device and Method of Manufacturing the Same

Non-Final OA §103§112
Filed
Jul 26, 2023
Examiner
YUSHINA, GALINA G
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Infineon Technologies Austria AG
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
96%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allow Rate
838 granted / 1059 resolved
+11.1% vs TC avg
Strong +17% interview lift
Without
With
+17.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
38 currently pending
Career history
1097
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
47.7%
+7.7% vs TC avg
§102
13.9%
-26.1% vs TC avg
§112
35.4%
-4.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1059 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restriction and Status of Claims The current application contains device claims and method claims that are commonly subjected to Restriction Requirements, at least, due to different classification (such as H10D 64/01 (manufacturer or treatment) or H10D 84/141 (VDMOS)), which is viewed as an element of an examination burden. However, original claims of the current application are built such that method claims do not have limitations specifically directed to any particular method and mainly repeat limitations of device claims. Accordingly, the current Office Action examines device and method claims together. Claims 1-19 are examined on merits herein. Claim Objections Claims 5, 6, 9, 16, and 19 are objected to because of the following informalities: Claim 5 recites in line 3 and Claim 16 recites in line 4: “a source region and/or body region”. Examiner suggests changing the recitations to: “a source region and/or a body region”. Claim 6 recites in line 2: “in a vertical top view” and recites in line 4: “vertically below”. Because “vertically” in line 4 means a cross-sectional view, Examiner suggests changing the recitation of line 2 into: “in a top view” – preventing confusion between two references to “vertical”. Claim 9 recites in lines 3-4 and Claim 19 recites in lines 4-5: “first conductor line has a lateral width smaller than a lateral width of the plurality of device cells”. Examiner suggests changing the recitations to: “first conductor line has a lateral width smaller than a lateral width of each of the plurality of device cells”, since “a lateral width of the plurality of device cells” may also be viewed as combined a width of cells. Appropriate corrections are required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1-19 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. In re Claim 1: Line 10 of Claim 1 recites: “the first interconnect is laterally offset to the field electrode trench”. The recitation related to a lateral offset is unclear, since the first interconnect and the field electrode trench are located in volumes vertically shifted from one another. Appropriate correction is required to clarify the claim language. For this Office Action, line 10 was interpreted as: “in a top view, the first interconnect is laterally offset from the field electrode trench”. In re Claim 1: Lines 11-12 of Claim 1 recite: “the lower metallization layer is not connected to the upper metallization layer in a region vertically above the field electrode trench”, while lines 8-9 of Claim 1 recite: “a first interconnect electrically connecting the lower metallization layer to the upper metallization layer”. The combination of the recitations is unclear, since an electrical connection cited by lines 8-9 creates electrical connections of entireties of the lower and upper metallization layers (both inherently being electrically conductive layers). Appropriate correction is required to clarify the claim language. For this Office Action, based on the specification of the application (including drawings) lines 11-12 of Claim 1 were interpreted as: “there is no mechanical connection between the lower and upper metallization layers in a region directly above the field electrode trench”. In re Claim 6: Line 1 of Claim 6 recites: “a body region of the device cell”. There is a lack of antecedent basis for citing: “body region” - with an article “a”, since Claim 6 depends on Claim 5, which recites: “(a) body region”. Appropriate correction is required. In re Claim 7: Claim 7 recites: “a high dose implant is disposed in the interruption region, which is made of the same doping type but with a higher doping concentration than the body region”. The recitation is not clear since leads to a question: What elements are compared based on doping concentrations – the body region and the high dose implant or the body region and the interruption region? In addition, there is a lack of antecedent basis for citing: “the same doping type” - with an article: “the”, since earlier Claim 7, or any claim on which Claim 7 depends, does not recite: “a doping type” of the body region. Appropriate correction is required to clarify the claim language. For this Office Action, based on the specification of the application, the cited limitation was interpreted as: “a high dose implant is disposed in the interruption region and has a same doping type but a higher doping concentration than the body region”. In re Claim 10: Claim 10 recites (lines 1-2): “in a vertical cross-section parallel to the first lateral direction, the insulating layer extends as a continuous layer”. The recitation is unclear, since a vertical cross-section can be only orthogonal to a lateral direction. Appropriate correction is required to clarify the claim language. For this Office Action, the cited limitation was interpreted as: “the insulating layer extends as a continuous layer parallel to the first lateral direction”. In re Claim 14: Claim 14 recites: “the first interconnect is laterally offset to the field electrode trench” and: “the lower metallization layer is not connected to the upper metallization layer in a region vertically above the field electrode trench”. The recitations are unclear for the same reasons that were explained for Claim 1, and for this Office Action, both recitations were interpreted similar to corresponding interpretations of limitations of Claim 1. In re Claim 17: Line 2 of Claim 17 recites: “a body region”. There is a lack of antecedent basis for using an article “a” in the above recitation, since Claim 17 depends on Claim 16, which already recites “(a) body region”. In re Claim 18: Claim 18 has a same issue as Claim 7, and for this Office Action, it was interpreted in a similar way. In re Claims 2-5, 8-9, 15-16, and 19: Claims 2-5, 8-9, 15-16, and 19 are rejected under 35 U.S.C. 112(b) due to dependency either on Claim 1 or on Claim 14. The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. Claim 8 is rejected under 35 U.S.C. 112(d) as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Applicant may cancel the claim, amend the claim to place the claim in proper dependent form, rewrite the claim in independent form, or present a sufficient showing that the dependent claim complies with the statutory requirements. In re Claim 8: Claim 8 recites (line 1): “a plurality of device cells are disposed”. Claim 8 depends on Claim 3, which recites: “a device cell”, and, as such, with respect to “device cell”, Claim 8 fails to further limit Claim 3. Appropriate correction is required to clarify the claimed subject matter. For this Office Action, in order to avoid a rejection under 35 U.S.C. 112(d), the cited limitation of Claim 8 was interpreted as: “the device cell is one of a plurality of device cells”; the new recitation can be viewed as clarifying “a device cell”, not as a recitation failing to further limit a corresponding limitation of Claim 3; at the same time, the suggested limitation also indicates existence of a plurality of device cells. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. As far as the claims are understood, Claims 1-2, 13-14, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Altstaetter et al. (US 2020/0052077) in view of Ghani et al. (US 2020/0212200). In re Claim 1, Altstaetter teaches a semiconductor device, comprising (Fig. 2) a field electrode 131 in a needle-shaped field electrode trench 134 (paragraphs 0072, 0079) extending from a frontside (being a top side) of a semiconductor body 190 (paragraph 0050) into the semiconductor body 190; a lower metallization layer 170 (in a region above 190, paragraphs 0065, 0083, 0097-0098, with paragraph 0098 teaching that 170 can be made from tungsten) on the frontside of the semiconductor body and electrically connected to the field electrode 131 (paragraph 0073); an insulating layer 1012 (paragraph 0064) on the lower metallization layer 170; an upper metallization layer 101 (paragraph 0051) on the insulating layer 1012; and a first interconnect (not shown in any figure) electrically connecting the lower metallization layer 170 to the upper metallization layer 101 (paragraph 0065). Altstaetter does not teach, at least, explicitly, that the first interconnect is laterally offset to the field electrode trench and that the lower metallization layer is not connected to the upper metallization layer in a region vertically above the field electrode trench (e.g., in accordance with the claim interpretation, Altstaetter does not teach, at least explicitly, that in a top view of the device, the first interconnect is laterally offset from the field electrode trench and that there is no mechanical connection between the lower and upper metallization layers in a region vertically directly above the field electrode trench”). Chani teaches (Annotated Fig. 59D, paragraphs 0601-0607) Annotated Fig. 59D PNG media_image1.png 548 526 media_image1.png Greyscale that an interconnect - Interconnect (as in Annotated Fig. 59D) from an upper structure (layer) to a lower metallization – Lower metallization (as in Annotated Fig. 59D) is made in a region laterally shifted from a trench – Trench (as in Annotated Fig. 59d) the trench filled with an electrically conductive material, while there is no mechanical connection between the lower metallization layer and the upper structure/layer in a region directly above the trench. Altstaetter and Ghani teach analogous arts directed to an interconnect to a lower metallization layer that is electrically connected to a conductive material within a trench, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Altstaetter device in view of the Ghani teaching, since they are from the same field of endeavor, and Ghani created a successfully operated device. It would have been obvious for one of ordinary skill in the art before filing the application to modify the Altstaetter semiconductor device, in view of the Ghani teaching, by creating the first interconnect latterly offset from the field electrode trench in a top view, while not creating a mechanical connection between the lower and upper metallization layers in a region directly above the field electrode trench, when such design/dispositions is(are) desired by a manufacturer. Note that in accordance with MPEP 2144.04 VI. C: Rearrangement of Parts, the court has held that rearrangement of parts (in the particular case, changing the position of the interconnect, if needed) that would not modify the device operation is unpatentable because it requires only ordinary skill in the art: In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950). In re Claim 2, Altstaetter/Chani teaches the semiconductor device of Claim 1 as cited above. Altstaetter further teaches (Fig. 2) that the upper metallization layer 101 extends in the region vertically above the field electrode trench 134 and is isolated there from the lower metallization layer 170 by the insulating layer 1012. In re Claim 13, Altstaetter/Ghani teaches the semiconductor device of Claim 1 as cited above. Altstaetter further teaches (paragraphs 0096-0098) that the lower metallization layer 170 is made of tungsten. In re Claim 14, Altstaetter teaches a method for manufacturing a semiconductor device, the method comprising (Fig. 2): forming (obviously) a field electrode 131 in a needle-shaped field electrode trench 134 (paragraphs 0072, 0079) extending from a frontside of a semiconductor body 190 into the semiconductor body 190 (paragraph 0050); forming (obviously) a lower metallization layer 170 (in a region directly above 190, paragraphs 0065, 0083, 0097-0098, 170 being made from tungsten) on the frontside of the semiconductor body 190 and electrically connected to the field electrode 131 (paragraph 0073); forming (obviously) an insulating layer 1012 (paragraph 0064) on the lower metallization layer 170; forming (obviously) an upper metallization layer 101 (paragraph 0051) on the insulating layer 1012; and forming a first interconnect electrically connecting the lower metallization layer to the upper metallization layer (the interconnect is not shown in any figure of Altstaetter, but is formed between the lower and upper metallization layers as described in paragraph 0065). Altstaetter does not teach at least, explicitly, that the first interconnect is formed to be laterally offset to the field electrode trench and that the lower metallization layer is formed not connected to the upper metallization layer in a region vertically above the field electrode trench (e.g., in accordance with the claim interpretation, Altstaetter does not teach, at least explicitly, that in a top view of the device, the first interconnect is laterally offset from the field electrode trench and that there is no mechanical connection between the lower and upper metallization layers in a region directly vertically above the field electrode trench”). Ghani teaches (Annotated Fig. 59D, paragraphs 0601-0607) forming an interconnect – Interconnect - from an upper structure (layer) to a lower metallization – Lower metallization (as in Annotated Fig. 59D), wherein the interconnect is formed in a region laterally shifted from a trench that is filled with a conductive material, while there is no mechanical connection between the lower metallization layer and the upper structure/layer in a region directly above the trench. It would have been obvious for one of ordinary skill in the art before filing the application to modify the Altstaetter semiconductor device and method of its manufacturing, in view of the Ghani teaching, by creating the first interconnect latterly offset from the field electrode trench in a top view, while not creating a mechanical connection between the lower and upper metallization layers in a region directly above the field electrode trench, when such design/dispositions is(are) desired by a manufacturer. Note that in accordance with MPEP 2144.04 VI. C: Rearrangement of Parts, the court has held that rearrangement of parts (in the particular case, changing the position of the interconnect, if needed) that would not modify the device operation is unpatentable because it requires only ordinary skill in the art: In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950). In re Claim 19, Altstaetter/Ghani teaches the method of Claim 14 as cited above. Altsaetter teaches the method, further comprising: forming (obviously) a first conductor line 170 (Fig. 2) in the lower metallization layer 170 and extending across a plurality of device cells 120 (paragraph 0055) of the semiconductor device, the first conductor line having a lateral width – as a lateral width of contact region 171 (Fig. 4, paragraph 0084) smaller than a lateral width of the plurality of device cells 120 (Fig. 4); and electrically connecting the first conductor line 170 to the field electrode 134 (as shown for Claim 14). Allowable Subject Matter Claims 3 and 15, as interpreted, contain allowable subject matter. Claims 4-12 and 16-18 depend on Claims 4 and 15, accordingly. Reason for Indicating Allowable Subject Matter Re Claim 3: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 3 as: “the first interconnect is arranged outside of the device cell”, in combination with other limitations of Claim 3 and with all limitations of Claim 1 (as interpreted), on which Claim 3 depends. Re Claim 15: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 15 as: “simultaneously forming with the first conductor line a gate conductor line that electrically contacts a gate region of the semiconductor device”, in combination with other limitations of Claim 15 and with all limitations of Claim 14, as interpreted. The prior arts of record, in addition to the prior arts cited by the current Office Action above, also include: Blank et al. (US 2019/0305092), Decker et al. (US 2015/0333,060), Haase (US 2022/0052164), Hirler et al. (US 11,133,391), Tihanyl (US 5,973,360), Laforet et al. (US 2017/0104078), Zeng et al. (US 2015/02321765), Hirler et al. (US 9,722,036), and Siemieniec et al. (US 2017/0250256). Conclusion Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible). Examiner interviews are available. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300; a fax phone number of Galina Yushina is 571-270-8440. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center - for more information about Patent Center and visit https://www.uspto.gov/patents/docx - for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800, United States Patent and Trademark Office E-mail: galina.yushina@USPTO.gov Phone: 571-270-7440 Date: 11/19/25
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Prosecution Timeline

Jul 26, 2023
Application Filed
Nov 30, 2025
Non-Final Rejection — §103, §112
Apr 08, 2026
Response Filed

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
96%
With Interview (+17.2%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 1059 resolved cases by this examiner. Grant probability derived from career allow rate.

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