DETAILED ACTION
Drawings
1. Figure 1A should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 - 23 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by CHANG et al. (2023/0343838).
With regard to claim 1, CHANG et al. disclose a semiconductor device (for example, fig.3 having one or more transistors functioning as a semiconductor device) comprising:
an input metal line (referred to as “M3A” by examiner’s annotation shown in fig. 3 below; wherein the input metal line M3A is a portion of the metal line M3) at a front side (referred to as “FS” by examiner’s annotation shown in fig. 3 below) of the semiconductor device (for example, the semiconductor device including one or more transistors; for example, see fig. 3); and at least one 1st output metal line (referred to as “BM2A” by examiner’s annotation shown in fig. 3 below; wherein the output metal line BM2A is a portion of the metal line BM2) at a back side (referred to as “FS” by examiner’s annotation shown in fig. 3 below) of the semiconductor device (for example, the semiconductor device including one or more transistors; for example, see fig. 3), wherein the input metal line (M3A) is inherently configured to receive an input signal of a 1st logic circuit (referred to as “T1” by examiner’s annotation shown in fig. 3 below; wherein the transistor T1 is the fundamental switch in logic circuits, acting as tiny voltage control gates that turn current flow on or off, functioning as a 1st logic circuit based on an FT via transmits a logic signal; for example, see paragraph [0038]), and wherein the 1st output metal line (BM2A) is inherently configured to output an output signal of the 1st logic circuit (T1).
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With regard to claim 2, CHANG et al. disclose the 1st logic circuit is a 1st inverter circuit comprising a 1st p-type field-effect transistor (FET) and a 1st n-type FET. (the FET can be a complementary metal-oxide-semiconductor (CMOS) FET wherein CMOSFET is inverter circuit inherently including p-type and n-type field-effect transistors; for example, see paragraph [0037]).
With regard to claim 3, CHANG et al. disclose an input contact structure or via (referred to as “V1” by examiner’s annotation shown in fig. 3 below) at the back side (BS) of the semiconductor device; and at least one 2nd output metal line (referred to as “M3B)” by examiner’s annotation shown in fig. 3 below) at the front side (FS) of the semiconductor device, wherein the input contact structure or via (V1) is inherently configured to receive the output signal of the 1st logic circuit (T1) as an input signal of a 2nd logic circuit (T2), and wherein the 2nd output metal line (M3B) is inherently configured to output an output signal of the 2nd logic circuit (T2).
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With regard to claim 4, CHANG et al. disclose the input contact structure or via (V1) is extended to the front side (FS) of the semiconductor device.
With regard to claim 5, CHANG et al. disclose the 2nd logic circuit comprises a 2nd inverter comprising a 2nd p-type FET and a 2nd n-type FET. (the FET can be a complementary metal-oxide-semiconductor (CMOS) FET wherein CMOSFET is inverter circuit inherently including p-type and n-type field-effect transistors; for example, see paragraph [0037]).
With regard to claim 6, CHANG et al. disclose an input contact structure or via (referred to as “V1” by examiner’s annotation shown in fig. 3 below) at the back side (BS) of the semiconductor device; and at least one 2nd output metal line (referred to as “M3B” by examiner’s annotation shown in fig. 3 below) at the front side (FS) of the semiconductor device, wherein the input contact structure or via (V1) is inherently configured to receive the output signal of the 1st logic circuit (T1) as an input signal of a 2nd logic circuit (T2), and wherein the 2nd output metal line (M3B) is inherently configured to output an output signal of the 2nd logic circuit (T2).
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With regard to claim 7, CHANG et al. disclose a 1st gate structure (referred to as “G1” by examiner’s annotation shown in fig. 3 below) connected to the input metal line (M3A) to receive the input signal of the 1st logic circuit (T1); a 1st source/drain region (referred to as “S/D1” by examiner’s annotation shown in fig. 3 below); and a 2st source/drain region (referred to as “S/D2” by examiner’s annotation shown in fig. 3 below), wherein the at least one 1st output metal line comprises: a 1st backside metal line (referred to as “BM1A” by examiner’s annotation shown in fig. 3 below) connected to the 1st source/drain region (S/D1); and a 2st backside metal line (referred to as “BM2A2” by examiner’s annotation shown in fig. 3 below) connected (indirectly connected and connected via a channel region of the transistor) to the 2st source/drain region (S/D2).
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With regard to claim 8, CHANG et al. disclose an input contact structure or via (referred to as “V1” by examiner’s annotation shown in fig. 3 below) at the back side (BS) of the semiconductor device; a 2nd gate structure (referred to as “V1” by examiner’s annotation shown in fig. 3 below) connected to the input contact structure or via (V1) to receive the output signal of the 1st logic circuit (T1) as an input signal of a 2nd logic circuit (T2); a 3rd source/drain region (referred to as “S/D3” by examiner’s annotation shown in fig. 3 below); a 4th source/drain region (referred to as “S/D4” by examiner’s annotation shown in fig. 3 below); and at least one 2nd output metal line (M3B as shown in fig. 3 below) at the front side (FS) of the semiconductor device, wherein the 2nd output metal line (M3B) is connected to at least one of the 3rd source/drain region (S/D3) to receive and output an output signal of the 2nd logic circuit (T2).
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With regard to claim 9, CHANG et al. disclose a semiconductor device (for example, fig.3 having one or more transistors functioning as a semiconductor device) comprising:
a 1st frontside metal line (referred to as “M3A1” by examiner’s annotation shown in fig. 3 below; wherein the 1st frontside metal line M3A1 is a portion of the metal line M3) at a front side (referred to as “FS” by examiner’s annotation shown in fig. 3 below) of the semiconductor device (for example, fig.3 having one or more transistors functioning as the semiconductor device); and
a 1st backside metal line (referred to as “BM2A1” by examiner’s annotation shown in fig. 3 below; wherein the 1st frontside metal line BM2A1 is a portion of the metal line BM2) at a back side (referred to as “BS” by examiner’s annotation shown in fig. 3 below) of the semiconductor device (for example, fig.3 having one or more transistors functioning as the semiconductor device), wherein the 1st backside metal line (BM2A1) is connected to the 1st frontside metal line (M3A1).
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With regard to claim 10, CHANG et al. disclose a 1st front-end-of-line (FEOL) structure comprising a 1st gate structure (referred to as “G1” by examiner’s annotation shown in fig. 3 below), and connected to the 1st frontside metal line (M3A1) and the 1st backside metal line (BM2A1).
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With regard to claim 11, CHANG et al. disclose the 1st source/drain region (S/D1) and the 1st gate structure (G1) forms a lower field-effect transistor.
With regard to claim 12, CHANG et al. disclose a 1st front-end-of-line structure (referred to as “E1” by examiner’s annotation shown in fig. 3 below) comprising: at least one of a 1st lower source/drain region (referred to as “S/D11” by examiner’s annotation shown in fig. 3 below) and a 1st lower gate structure (referred to as “G1A” by examiner’s annotation shown in fig. 3 below); and at least one of a 1st upper source/drain region (referred to as “S/D12” by examiner’s annotation shown in fig. 3 below) and a 1st upper gate structure (referred to as “G1B” by examiner’s annotation shown in fig. 3 below) stacked above the 1st lower source/drain region (S/D11) and the 1st lower gate structure (G1A), respectively, wherein the at least one of the 1st lower source/drain region (S/D11) and the 1st lower gate structure (G1A) is connected to the at least one of the 1st upper source/drain region (S/D11) and the 1st upper gate structure (G1B), respectively.
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With regard to claim 13, CHANG et al. disclose a 2nd frontside metal line (referred to as “M3A2” by examiner’s annotation shown in fig. 3 below) at the front side (FS) of the semiconductor device; and a 2nd backside metal line (referred to as “BM2A2” by examiner’s annotation shown in fig. 3 below) at the back side (BS) of the semiconductor device, wherein the 2nd backside metal line (BM2A2) is connected to the 2nd frontside metal line (M3A2), and wherein the 1st frontside metal line (M3A1) and the 1st backside metal line (BM2A1) correspond to a 1st semiconductor cell (referred to as “T1” by examiner’s annotation shown in fig. 3 below), and the 2nd frontside metal line (M3A2) and the 2nd backside metal line (BM2A2) correspond to a 2nd semiconductor cell (referred to as “T2” by examiner’s annotation shown in fig. 3 below).
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With regard to claim 14, CHANG et al. disclose one of a connection (referred to as “M3B1” by examiner’s annotation shown in fig. 3 below) between the 1st and 2nd frontside metal lines (M3A2, M3A1) and a connection (referred to as “M3B2” by examiner’s annotation shown in fig. 3 below) between the 1st and 2nd backside metal lines (BM2A2, BM2A1) is inherently configured to be selectively enabled (in order to provide a signal power to the gate of the transistors).
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With regard to claim 15, CHANG et al. disclose at least one backside power rail (referred to as “BM2B” by examiner’s annotation shown in fig. 3 below).
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With regard to claim 16, CHANG et al. disclose a 2nd front-end-of-line (FEOL) structure comprising of a 2nd source/drain region (referred to as “S/D2” by examiner’s annotation shown in fig. 3 below), and connected to the 2nd frontside metal line (M3A2) and the 2nd backside metal line (BM2A2).
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With regard to claim 17, CHANG et al. disclose the 2nd source/drain region (S/D2) and the 2nd gate structure (G2) forms a lower field-effect transistor.
With regard to claim 18, CHANG et al. disclose 1st FEOL structure comprising 1st gate structure (referred to as “G1” by examiner’s annotation shown in fig. 3 below), and connected to the 1st frontside metal line (M3A1) and the 1st backside metal line (BM2A1), and wherein the 1st FEOL structure (the 1st FEOL structure comprising 1st gate structure G1) and 2nd FEOL structure (2nd front-end-of-line structure comprising of a 2nd source/drain region S/D2) are connected to each other through the 1st and 2nd frontside metal lines (M3A1, M3A2).
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With regard to claim 19, CHANG et al. disclose the 1st FEOL structure (E1) comprises: at least one of a 1st lower source/drain region (referred to as “S/D11” by examiner’s annotation shown in fig. 3 below) and a 1st lower gate structure (referred to as “G1A” by examiner’s annotation shown in fig. 3 below); and at least one of a 1st upper source/drain region (referred to as “S/D12” by examiner’s annotation shown in fig. 3 below) and a 1st upper gate structure (referred to as “G1B” by examiner’s annotation shown in fig. 3 below) stacked above the 1st lower source/drain region (S/D11) and the 1st lower gate structure (G1A), respectively, wherein the at least one of the 1st lower source/drain region (S/D11) and the 1st lower gate structure (G1A) is connected to the at least one of the 1st upper source/drain region (S/D12) and the 1st upper gate structure (G1B), respectively, wherein the 2nd FEOL structure (referred to as “E2” by examiner’s annotation shown in fig. 3 below) comprises: at least one of a 2nd lower source/drain region (referred to as “S/D21” by examiner’s annotation shown in fig. 3 below) and a 2nd lower gate structure (referred to as “G2A” by examiner’s annotation shown in fig. 3 below); and at least one of a 2nd upper source/drain region (referred to as “S/D22” by examiner’s annotation shown in fig. 3 below) and a 2nd upper gate structure (referred to as “G2B” by examiner’s annotation shown in fig. 3 below) stacked above the 2nd lower source/drain region (S/D21) and the 2nd lower gate structure (G2A), respectively, and wherein the at least one of the 2nd lower source/drain region (S/D21) and the 2nd lower gate structure (G2A) is connected to the at least one of the 2nd upper source/drain region (S/D22) and the 2nd upper gate structure (G2B), respectively.
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With regard to claim 20, CHANG et al. disclose one of a connection (referred to as “M3B1” by examiner’s annotation shown in fig. 3 below) between the 1st and 2nd frontside metal lines (M3A2, M3A1) and a connection (referred to as “M3B2” by examiner’s annotation shown in fig. 3 below) between the 1st and 2nd backside metal lines (BM2A2, BM2A1) is inherently configured to be selectively enabled (in order to provide a signal power to the gate of the transistors).
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With regard to claim 21, CHANG et al. disclose a semiconductor device (for example, fig.3 having one or more transistors functioning as a semiconductor device) comprising:
a 1st front-end-of-line structure (referred to as “E1” by examiner’s annotation shown in fig. 3 below) comprising at least one of a 1st source/drain region (referred to as “S/D1” by examiner’s annotation shown in fig. 3 below) and a 1st gate structure (referred to as “G1” by examiner’s annotation shown in fig. 3 below);
a 1st frontside metal line (referred to as “M3A1” by examiner’s annotation shown in fig. 3 below); and
a 1st backside metal line (referred to as “BM2A1” by examiner’s annotation shown in fig. 3 below), wherein the 1st FEOL structure (E1) is configured to be selectively connected to the 1st frontside metal line (M3A1).
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With regard to claim 22, CHANG et al. disclose a 2.sup.nd FEOL structure (referred to as “E2” by examiner’s annotation shown in fig. 3 below) comprising at least one of a 2nd source/drain region (referred to as “S/D2” by examiner’s annotation shown in fig. 3 below) and a 2nd gate structure (referred to as “G2” by examiner’s annotation shown in fig. 3 below); a 2nd frontside metal line (referred to as “M3A2” by examiner’s annotation shown in fig. 3 below); and a 2nd backside metal line (referred to as “BM2A2” by examiner’s annotation shown in fig. 3 below), wherein the 2nd FEOL structure (E2) is selectively connected to the 2nd frontside metal line (M3A2), and wherein the 1st frontside metal line (M3A1) and the 1st backside metal line (BM2A1) correspond to a 1st semiconductor cell (referred to as “T1” by examiner’s annotation shown in fig. 3 below), and the 2nd frontside metal line (M3A2) and the 2nd backside metal line (BM2A2) correspond to a 2nd semiconductor cell (referred to as “T2” by examiner’s annotation shown in fig. 3 below).
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With regard to claim 23, CHANG et al. disclose one of a connection (referred to as “M3B1” by examiner’s annotation shown in fig. 3 below) between the 1st and 2nd frontside metal lines (M3A2, M3A1) and a connection (referred to as “M3B2” by examiner’s annotation shown in fig. 3 below) between the 1st and 2nd backside metal lines (BM2A2, BM2A1) is inherently configured to be selectively enabled (in order to provide a signal power to the gate of the transistors).
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Conclusion
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TAN N TRAN/
Primary Examiner, Art Unit 2812
Prosecution Insights