DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 5, 24, 25 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by CHANG et al. (2023/0343838).
With regard to claim 1, CHANG et al. disclose a semiconductor device (for example, fig.3 having one or more transistors functioning as a semiconductor device) comprising:
a 1st source/drain region (referred to as “S/D1” by examiner’s annotation shown in fig. 3 below) and a 2ⁿᵈ source/drain region (referred to as “S/D2” by examiner’s annotation shown in fig. 3 below) spaced apart from the 1st source/drain region (S/D1) in a 1st direction (a horizontal direction);
an input metal line (referred to as “M3A” by examiner’s annotation shown in fig. 3 below; wherein the input metal line M3A is a portion of the metal line M3) at a front side (referred to as “FS” by examiner’s annotation shown in fig. 3 below) of the semiconductor device (for example, the semiconductor device including one or more transistors; for example, see fig. 3); and
at least one 1st output metal line (referred to as “BM2A” by examiner’s annotation shown in fig. 3 below; wherein the output metal line BM2A is a portion of the metal line BM2) at a back side (referred to as “FS” by examiner’s annotation shown in fig. 3 below) of the semiconductor device (for example, the semiconductor device including one or more transistors; for example, see fig. 3), wherein the input metal line (M3A) is inherently configured to receive an input signal of a 1st logic circuit (referred to as “T1” by examiner’s annotation shown in fig. 3 below; wherein the transistor T1 is the fundamental switch in logic circuits, acting as tiny voltage control gates that turn current flow on or off, functioning as a 1st logic circuit based on an FT via transmits a logic signal; for example, see paragraph [0038]), and wherein the 1st output metal line (BM2A) is inherently configured to output an output signal of the 1st logic circuit (T1);
wherein the 1st output metal line (BM2A) comprises a 1st backside metal line (referred to as “BM2A1” by examiner’s annotation shown in fig. 3 below) electrically connected to the 1st source/drain region (S/D1) and a 2ⁿᵈ backside metal line (referred to as “BM2A2” by examiner’s annotation shown in fig. 3 below) electrically connected to the 2ⁿᵈ source/drain region (S/D2), and
wherein the 2ⁿᵈ backside metal line (BM2A2) is spaced apart from the 1st backside metal line (BM2A1) in the 1st direction (the horizontal direction).
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With regard to claim 2, CHANG et al. disclose the 1st logic circuit is a 1st inverter circuit comprising a 1st p-type field-effect transistor (FET) and a 1st n-type FET. (the FET can be a complementary metal-oxide-semiconductor (CMOS) FET wherein CMOSFET is inverter circuit inherently including p-type and n-type field-effect transistors; for example, see paragraph [0037]).
With regard to claim 3, CHANG et al. disclose an input contact structure or via (referred to as “V1” by examiner’s annotation shown in fig. 3 below) at the back side (BS) of the semiconductor device; and at least one 2nd output metal line (referred to as “M3B)” by examiner’s annotation shown in fig. 3 below) at the front side (FS) of the semiconductor device, wherein the input contact structure or via (V1) is inherently configured to receive the output signal of the 1st logic circuit (T1) as an input signal of a 2nd logic circuit (T2), and wherein the 2nd output metal line (M3B) is inherently configured to output an output signal of the 2nd logic circuit (T2).
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With regard to claim 4, CHANG et al. disclose the input contact structure or via (V1) is extended to the front side (FS) of the semiconductor device and wherein the 2ⁿᵈ backside metal line (BM2A2) is free of vertical overlap with the 1st backside metal line (BM2A1).
With regard to claim 5, CHANG et al. disclose the 2nd logic circuit comprises a 2nd inverter comprising a 2nd p-type FET and a 2nd n-type FET. (the FET can be a complementary metal-oxide-semiconductor (CMOS) FET wherein CMOSFET is inverter circuit inherently including p-type and n-type field-effect transistors; for example, see paragraph [0037]).
With regard to claim 24, CHANG et al. disclose a backside contact structure (referred to as “BM1A1” by examiner’s annotation shown in fig. 3 below) on a bottom surface of the 1st source/drain region (S/D1), wherein the 1st backside metal line (BM2A1) is electrically connected to the 1st source/drain region (S/D1) through the backside contact structure (BM1A1), and wherein the 1st source/drain region (S/D1) vertically overlaps at least one of the 1st backside metal line (BM2A1) and the backside contact structure (BM1A1).
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With regard to claim 25, CHANG et al. disclose 1st and 2ⁿᵈ power rails (metal lines M1, M2 as shown in fig. 3) extending in parallel with at least one of the 1st backside metal line (BM2A1), the 2nd backside metal line (BM2A2), and the input metal line (M3A), wherein the 1st and 2ⁿᵈ power rails (M1, M2) extend at the front side (FS) of the semiconductor device.
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Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21 – 23, 26 - 27 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHEN et al. (20210375853).
With regard to claim 21, CHEN et al. disclose a semiconductor device (for example, figs. `1B, 1C) comprising:
a 1st front-end-of-line structure (a structure including a first transistor T1, forming on the top side of the substrate 120, functioning as a 1st front-end-of-line structure) comprising a 1st source/drain region (113) and a 1st gate structure (GB);
a 2ⁿᵈ FEOL structure (a structure including a second transistor T2, forming on the top side of the substrate 120, functioning as a 2ⁿᵈ front-end-of-line structure) comprising a 2ⁿᵈ source/drain region (114) and a 2ⁿᵈ gate structure (GC);
a 1st frontside metal line (MD_1) and a 2ⁿᵈ frontside metal line (M0_1, or MD_2) at a front side of the semiconductor device; and
a 1st backside metal line (referred to as “BM0_1A” by examiner’s annotation shown in fig. 1C below; wherein the 1st backside metal line BM0_1A, fig. 1C below, is a portion of the metal line BM0_1, as shown in fig. 1B) and a 2nd backside metal line (referred to as “BM0_1B” by examiner’s annotation shown in fig. 1C below; wherein the 1st backside metal line BM0_1B, fig. 1C below, is a portion of the metal line BM0_1, as shown in fig. 1B) at a back side of the semiconductor device,
wherein the 1st source/drain region (113) is electrically connected to the 2ⁿᵈ source/drain region (114) through the 1st and 2ⁿᵈ frontside metal lines (MD_1, MD_2, M0_1).
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With regard to claim 22, CHEN et al. disclose the 1st frontside metal line (MD_1) and the 1st backside metal line (BM0_1A) correspond to a 1st semiconductor cell (1st semiconductor cell including a first transistor T1), and the 2ⁿᵈ frontside metal line (MD_2, or M0_1) and the 2ⁿᵈ backside metal line (BM0_1B) correspond to a 2ⁿᵈ semiconductor cell (2ⁿᵈ semiconductor cell including a second transistor T2).
With regard to claim 23, CHEN et al. disclose one (M0_1) of connection (M0_1, VD-1, VD-2) between the 1st and 2ⁿᵈ frontside metal lines (MD_1, MD_2) and a connection (referred to as "C1" by examiner's annotation shown in fig. 1C below) between the 1st and 2ⁿᵈ backside metal lines (BM0_1A, BM0_1B) is inherently configured to be selectively enabled (in order to provide a signal power to the transistors).
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With regard to claim 26, CHEN et al. disclose the 1st source/drain region (113)
is electrically connected to the 2ⁿᵈ source/drain region (114) through the 1st and 2ⁿᵈ backside metal lines (BM0_1A, BM0_1b)
With regard to claim 27, CHEN et al. disclose a 1st backside contact structure (VB_1) on a bottom surface of the 1st source/drain region (113), wherein the 1st source/drain region (113) is electrically connected to the 1st backside metal line (BM0_1A) through the 1st
backside contact structure (VB_1); and a 2ⁿᵈ backside contact structure (VB_2) on a bottom surface of the 2ⁿᵈ source/drain region (114), wherein the 2ⁿᵈ source/drain region (114) is electrically connected to the 2ⁿᵈ backside metal line (BM0_1B) through the 2ⁿᵈ backside contact structure (VB_2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 - 11, 13 - 18 are rejected under 35 U.S.C. 103 as being unpatentable over CHANG et al. (2023/0343838) in view of Or-Bach et al. (8237228).
With regard to claim 9, CHANG et al. disclose a semiconductor device (for example, fig.3 having one or more transistors functioning as a semiconductor device) comprising:
a 1st frontside metal line (referred to as “M3A1” by examiner’s annotation shown in fig. 3 below; wherein the 1st frontside metal line M3A1 is a portion of the metal line M3) at a front side (referred to as “FS” by examiner’s annotation shown in fig. 3 below) of the semiconductor device (for example, fig.3 having one or more transistors functioning as the semiconductor device); and
a 1st backside metal line (referred to as “BM2A1” by examiner’s annotation shown in fig. 3 below; wherein the 1st frontside metal line BM2A1 is a portion of the metal line BM2) at a back side (referred to as “BS” by examiner’s annotation shown in fig. 3 below) of the semiconductor device (for example, fig.3 having one or more transistors functioning as the semiconductor device), wherein the 1st backside metal line (BM2A1) is connected to the 1st frontside metal line (M3A1).
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CHANG et al. do not clearly disclose a 1st front-end-of-line (FEOL) structure comprising:
a 1st lower source/drain region having a 1st conductivity type; and a 1st upper source/drain region on the 1st lower source/drain region, the 1st upper source/drain region having a 2nd conductivity type opposite the 1st conductivity type, wherein the 1st lower source/drain region is electrically connected to the 1st upper source/drain region.
However, Or-Bach et al. discloses a 1st front-end-of-line (FEOL) structure (a structure having transistors forming on the top surface of the substrate, functions as a 1st front-end-of-line structure) comprising: a 1st lower source/drain region (referred to as “D1” by examiner’s annotation shown in fig. 50D below) having a 1st conductivity type (N-type conductivity); and a 1st upper source/drain region (referred to as “D2” by examiner’s annotation shown in fig. 50D below) on the 1st lower source/drain region (D1), the 1st upper source/drain region (D2) having a 2nd conductivity type (P-type conductivity) opposite the 1st conductivity type (N-type conductivity), wherein the 1st lower source/drain region (D1) is electrically connected to the 1st upper source/drain region (D2).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the CHANG et al.’s device to have a 1st front-end-of-line (FEOL) structure comprising: a 1st lower source/drain region having a 1st conductivity type; and a 1st upper source/drain region on the 1st lower source/drain region, the 1st upper source/drain region having a 2nd conductivity type opposite the 1st conductivity type, wherein the 1st lower source/drain region is electrically connected to the 1st upper source/drain region as taught by Or-Bach et al. in order to ensure the NMOS and PMOS transistors sharing contacts to make the shared connection for the output for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 10, CHANG et al. disclose the 1st lower source/drain region (referred to as “S1” by examiner’s annotation shown in fig. 50D below) and the 1st upper source/drain region (referred to as “S2” by examiner’s annotation shown in fig. 50D below) are both electrically connected to the 1st frontside metal line (M3A1) and the 1st backside metal line (BM2A1).
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With regard to claim 11, Or-Bach et al. disclose the 1st FEOL structure further comprises a 1st lower gate structure adjacent to the 1st lower source/drain region (D1) and a 1st upper gate structure (5016) adjacent to the 1st upper source/drain region (D1), wherein the 1st lower source/drain region (D1) and the 1st lower gate structure (5016) forms either form a lower field-effect transistor (NMOS functioning as a lower field-effect transistor), and wherein the 1st upper source/drain region (D2) and the 1st upper gate structure (5014) form an upper field-effect transistor (PMOS a upper field-effect transistor) stacked on the lower field-effect transistor.
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With regard to claim 13, CHANG et al. disclose a 2nd frontside metal line (referred to as “M3A2” by examiner’s annotation shown in fig. 3 below) at the front side (FS) of the semiconductor device; and a 2nd backside metal line (referred to as “BM2A2” by examiner’s annotation shown in fig. 3 below) at the back side (BS) of the semiconductor device, wherein the 2nd backside metal line (BM2A2) is electrically connected to the 2nd frontside metal line (M3A2), and wherein the 1st frontside metal line (M3A1) and the 1st backside metal line (BM2A1) correspond to a 1st semiconductor cell (referred to as “T1” by examiner’s annotation shown in fig. 3 below), and the 2nd frontside metal line (M3A2) and the 2nd backside metal line (BM2A2) correspond to a 2nd semiconductor cell (referred to as “T2” by examiner’s annotation shown in fig. 3 below).
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With regard to claim 14, CHANG et al. disclose one of a connection (referred to as “M3B1” by examiner’s annotation shown in fig. 3 below) between the 1st and 2nd frontside metal lines (M3A2, M3A1) and a connection (referred to as “M3B2” by examiner’s annotation shown in fig. 3 below) between the 1st and 2nd backside metal lines (BM2A2, BM2A1) is inherently configured to be selectively enabled (in order to provide a signal power to the gate of the transistors).
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With regard to claim 15, CHANG et al. disclose at least one backside power rail (referred to as “BM2B” by examiner’s annotation shown in fig. 3 below).
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With regard to claim 16, CHANG et al. disclose a 2nd front-end-of-line (FEOL) structure comprising of a 2nd source/drain region (referred to as “S/D2” by examiner’s annotation shown in fig. 3 below), and electrically connected to the 2nd frontside metal line (M3A2) and the 2nd backside metal line (BM2A2).
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With regard to claim 17, CHANG et al. disclose the 2nd source/drain region (S/D2) and the 2nd gate structure (G2) forms a lower field-effect transistor.
With regard to claim 18, CHANG et al. disclose the 1st FEOL structure (the 1st FEOL structure comprising 1st gate structure G1) and 2nd FEOL structure (2nd front-end-of-line structure comprising of a 2nd source/drain region S/D2) are electrically connected to each other through the 1st and 2nd frontside metal lines (M3A1, M3A2).
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Allowable Subject Matter
7. Claims 7, 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 7, 8 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as a 1st gate structure electrically connected to the input metal line to receive the input signal of the 1st logic circuit, wherein the 1st gate structure is adjacent to each of the 1st and 2ⁿᵈ source/drain regions, and wherein at least a portion of the 1st gate structure is between, in a top view, the 1st backside metal line and the 2ⁿᵈ backside metal line as recited in claim 7.
Response to Amendment
8. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
9. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TAN N TRAN/
Primary Examiner, Art Unit 2812
Prosecution Insights