DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al. (US 2020/0105663).
Regarding claim 1, Tsai teaches (FIG. 16):
A semiconductor package, comprising:
a first redistribution substrate (206);
a semiconductor chip (224) on the first redistribution substrate;
a connection structure on the first redistribution substrate and spaced apart from the semiconductor chip, the connection structure including a connection substrate and a post on the connection substrate (100/236);
a second redistribution substrate (238) on the semiconductor chip and the connection structure; and
a molding layer (232) between the first redistribution substrate and the second redistribution substrate, the molding layer encapsulating the semiconductor chip and the connection structure, wherein:
the connection substrate includes a conductive pattern that vertically penetrates the connection substrate (108/110), the post is in contact with a top surface of the conductive pattern, and a width of the post is less than a width of the connection substrate (FIG. 16).
Regarding claim 2, Tsai teaches:
The semiconductor package as claimed in claim 1, wherein the connection substrate includes: a core layer (102); an upper layer that covers a top surface of the core layer (112 top); and a lower layer (112 bottom) that covers a bottom surface of the core layer, a lateral surface of the core layer, a lateral surface of the upper layer, and a lateral surface of the lower layer being vertically aligned with each other (FIG. 16).
Regarding claim 3, Tsai teaches:
The semiconductor package as claimed in claim 2, wherein the conductive pattern includes: a first conductive pattern (108) that vertically penetrates the core layer of the connection substrate; and a plurality of second conductive patterns (110) that penetrate the upper layer and the lower layer of the connection substrate, the first conductive pattern connecting the plurality of second conductive patterns to each other (FIG. 16).
Regarding claim 4, Tsai teaches:
The semiconductor package as claimed in claim 3, wherein the first conductive pattern has a width that is constant between the top surface and the bottom surface of the core layer of the connection substrate (FIG. 16).
Regarding claim 5, Tsai teaches:
The semiconductor package as claimed in claim 3, wherein each of the plurality of second conductive patterns have a width that decreases with distance from the core layer of the connection substrate (FIG. 16).
Regarding claim 6, Tsai teaches:
The semiconductor package as claimed in claim 1, wherein the conductive pattern includes: a via (108) that penetrates the connection substrate; and an upper pad (110) and a lower pad (110) that protrude from the connection substrate, the post being in contact with a top surface of the upper pad (FIG. 16).
Regarding claim 7, Tsai teaches:
The semiconductor package as claimed in claim 1, wherein the connection substrate is spaced apart from a lateral surface of the molding layer (FIG. 16).
Regarding claim 8, Tsai teaches:
The semiconductor package as claimed in claim 1, wherein: a top surface of the post is coplanar with a top surface of the molding layer, and the top surface of the post and the top surface of the molding layer are in contact with a bottom surface of the second redistribution substrate (FIG. 16).
Regarding claim 9, Tsai teaches (FIG. 16):
A semiconductor package, comprising:
a first redistribution substrate (206);
a semiconductor chip (224) on the first redistribution substrate;
a second redistribution substrate (238) on the semiconductor chip;
a connection structure (100) spaced apart from the semiconductor chip and connecting the first redistribution substrate and the second redistribution substrate to each other, the connection structure including a connection substrate and a post (236) on the connection substrate; and
a molding layer (232) between the first redistribution substrate and the second redistribution substrate, the molding layer surrounding the post and the semiconductor chip, wherein the connection substrate includes:
a core layer (102);
a first conductive pattern (108) that vertically penetrates the core layer;
an upper layer (112) that covers a top surface of the core layer;
a plurality of second conductive patterns (110) that penetrate the upper layer and the lower layer, the plurality of second conductive patterns being connected to the first conductive pattern, and each of the plurality of second conductive patterns having a width that decreases with distance from the core layer (FIG. 16).
Regarding claim 10, Tsai teaches:
The semiconductor package as claimed in claim 9, wherein the post is spaced apart from the upper layer of the connection substrate (FIG. 16).
Regarding claim 11, Tsai teaches:
The semiconductor package as claimed in claim 9, wherein a width of the post is less than a width of the connection substrate (FIG. 16).
Regarding claim 12, Tsai teaches:
The semiconductor package as claimed in claim 9, wherein the first conductive pattern has a width that is constant between the top surface and the bottom surface of the core layer of the connection substrate (FIG. 16).
Regarding claim 13, Tsai teaches:
The semiconductor package as claimed in claim 9, wherein a lateral surface of the core layer of the connection substrate, a lateral surface of the upper layer of the connection substrate, and a lateral surface of the lower layer of the connection substrate are vertically aligned with each other (FIG. 16).
Regarding claim 14, Tsai teaches:
The semiconductor package as claimed in claim 9, wherein the second conductive pattern has a plurality of pads that protrude from a top surface and a bottom surface of the connection substrate (FIG. 16).
Regarding claim 15, Tsai teaches:
The semiconductor package as claimed in claim 9, wherein the post is in contact with a top surface of one of the plurality of second conductive patterns that penetrates the upper layer of the connection substrate (FIG. 16).
Regarding claim 16, Tsai teaches:
The semiconductor package as claimed in claim 9, wherein the connection substrate is spaced apart from a lateral surface of the molding layer (FIG. 16).
Regarding claim 17, Tsai teaches:
The semiconductor package as claimed in claim 9, wherein: a top surface of the post is coplanar with a top surface of the molding layer, and the top surface of the post and the top surface of the molding layer are in contact with a bottom surface of the second redistribution substrate (FIG. 16).
Regarding claim 18, Tsai teaches (FIG. 16):
A semiconductor package, comprising:
a first redistribution substrate (206);
a first semiconductor chip (224) mounted on the first redistribution substrate;
a connection substrate (100) on the first redistribution substrate and surrounding the first semiconductor chip;
a post (236) on the connection substrate;
a molding layer (232) that surrounds the first semiconductor chip, the post, and the connection substrate; and
a second redistribution substrate (238) on the molding layer, wherein:
the connection substrate includes:
a core layer (102);
an upper layer (112) on a top surface of the core layer;
a lower layer (112) on a bottom surface of the core layer;
a first conductive pattern (108) that vertically penetrates the core layer; and
a plurality of second conductive patterns (110) that correspondingly penetrate the upper layer and the lower layer, a lateral surface of the core layer, a lateral surface of the upper layer, and a lateral surface of the lower layer are vertically aligned with each other, and a width of the first conductive pattern is constant between the top surface and the bottom surface of the core layer (FIG. 16).
Regarding claim 19, Tsai teaches:
The semiconductor package as claimed in claim 18, wherein each second conductive pattern of the plurality of second conductive patterns has a width that decreases with distance from the core layer of the connection substrate (FIG. 16).
Regarding claim 20, Tsai teaches:
The semiconductor package as claimed in claim 18, wherein a width of the post is less than a width of the connection substrate (FIG. 16).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jerry O'Connor can be reached at (571) 272-6787. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CORY W ESKRIDGE/Primary Examiner, Art Unit 3624