DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Claim 11 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on January 7, 2026.
Note from the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 and 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
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Claims 1-2, 7, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Green et al. (US 20160343809 A1), hereinafter referred to as “Green”;
[Salmon (US 20220217845 A1), hereinafter referred to as “Salmon”, and Cavanaugh et al. (US 20220205847 A1), hereinafter referred to as “Cavanaugh”, are utilized herein as evidence].
Regarding claim 1, Green discloses a semiconductor device (figs. 1 and 2, 100; see [0004]-[0005]) comprising:
a silicon carbide substrate (fig. 2, 212; see [0025]);
a nitride semiconductor layer (fig. 2, 214; see [0025]: “[b]uffer layer 214 may be a multi-layer structure, where each of the semiconductor layers of buffer layer 214 may include an epitaxially grown group III nitride epitaxial layer”) provided on a top surface (fig. 2, 213) of the silicon carbide substrate (see [0025]: “[b]uffer layer 214 is formed on upper surface 213 of host substrate 212”);
a transistor (fig. 2, 120; see [0032]) comprising a source electrode (fig. 2, 124), a gate electrode (fig. 2, 126), a drain electrode (fig. 2, 122), a portion of a channel layer (fig. 2, 216; see [0025]: note that the various nitride layers (214, 216, 218, etc.) are formed over the entirety of host substrate 212 (and are included in semiconductor substrate 110); see [0031] and note that the various nitride layers are inactivated outside of active region 114 by an ion implantation procedure; the transistor is formed within active region 114), a 2DEG electron gas layer (fig. 2, 217; see [0028]), and a barrier layer (fig. 2, 218; see [0028]), all being provided on the nitride semiconductor layer (see fig. 2 and [0027]: “channel layer 216 is formed over buffer layer 214”);
and an element (fig. 2, 130; see [0020]: inductor 130 is formed on the semiconductor substrate 110 which includes host substrate 212 (see [0025])) provided on or above the silicon carbide substrate;
wherein the silicon carbide substrate has a portion of a hole (fig. 2, 160; see [0023]) that is provided between the transistor and the element (see annotated fig. 2, a portion of cavity 160 lies between transistor 120 and inductor 130);
the language “formed by removing at least a part of the silicon carbide substrate from a bottom surface of the silicon carbide substrate” is directed towards the process of manufacturing the semiconductor device. It is well settled that “product by process” limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Pilkington 162 USPQ 145, 147; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. The applicant must show that different methods of manufacturing produce articles having inherently different characteristics, Ex parte Skinner 2 USPQ 2d 1788.
As such, the claim language does not distinguish from the device of Green, who teaches the structure as claimed;
and an internal thermal conductivity of the hole is smaller than a thermal conductivity of the silicon carbide substrate (see [0042]-[0043]; cavity 160 is filled with dielectric medium 166 which is air;
see evidentiary reference Salmon [0138]: “[a]ir has a thermal conductivity of 0.028 W/m° K”.; also see evidentiary reference Cavanaugh [0017]: “silicon carbide has a thermal conductivity of 200 W/m*K”; therefore, the thermal conductivity of air is far less than the thermal conductivity of silicon carbide).
Regarding claim 2, Green discloses the semiconductor device according to claim 1, further comprising: a metal layer (fig. 2, 142; see [0044]: “[m]etal used to form back metal 140 and/or backside contact 142 may be used to fill or coat the sidewalls of the inside of through wafer via 168 and to contact drain electrode 122, source electrode 124, first interconnect metal 128 and/or top interconnect structure(s) 134 to provide electrical coupling between drain electrode 122, source electrode 122, first interconnect metal 128, top interconnect structure(s) 134, back metal 140 and/or backside contact 142”) electrically connected to the transistor (fig. 2, 120; note that Green [0032] discloses that the transistor 120 includes the electrodes and semiconductor layers included in active region 114; see Green [0044] and note that the transistor is electrically coupled to backside contact 142 via through wafer via 168) via a via hole (fig. 2, 168; see [0044]) that penetrates through the silicon carbide substrate and the nitride semiconductor layer (see fig. 2, [0025], [0031], and [0044]: through wafer vias 168 penetrate through host substrate 212 and the inactivated nitride semiconductor layers (including the inactivated portion of buffer layer 214) in isolation region 112 to electrically couple the transistor to the backside contact 142) .
Regarding claim 7, Green discloses the semiconductor device according to claim 1, wherein at least a part of the inside of the hole (fig. 2, 160) is an air gap (see [0042]-[0043]: cavity 160 is filled with dielectric 166, and dielectric 166 is air).
Regarding claim 9, Green discloses the semiconductor device according to claim 1, wherein the element (fig. 2, 130) is a passive element (see [0020] and note that Green discloses that inductor 130 is a passive element).
Claim 1, 8, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Naito (US 20080210989 A1), hereinafter referred to as “Naito”;
[Salmon and Cavanaugh are utilized herein as evidence].
Regarding claim 1, Naito discloses a semiconductor device (figs. 1 and 2) comprising:
a silicon carbide substrate (fig. 1, 10; see [0045]);
a nitride semiconductor layer (fig. 1, 18; see [0022] and [0045]: the compound semiconductor layer 21 comprises electron supply layer 18 and is made of gallium nitride (GaN); see the paragraphs directly preceding [0045] (i.e. [0043]-[0044]) and note that the subject matter of [0045] applies to the first embodiment of the invention (shown in fig. 1)) provided on a top surface of the silicon carbide substrate (see fig. 2 and [0022]; electron supply layer 18 is provided on a top surface of substrate 10);
a transistor (fig. 1, 40; see [0023]: “[s]ets of source electrodes 22, gate electrodes 26 and drain electrodes 24 form first and second FETs 40 and 42”) provided on the nitride semiconductor layer (see fig. 1);
and an element (fig. 1, 42; see [0023]) provided on or above the silicon carbide substrate (see fig. 1);
wherein the silicon carbide substrate has a hole (fig. 1, 32; see [0024]) that is provided between the transistor and the element (see fig. 1: via hole 32 is provided between first and second FETs 40 and 42);
the language “formed by removing at least a part of the silicon carbide substrate from a bottom surface of the silicon carbide substrate” is directed towards the process of manufacturing the semiconductor device. It is well settled that “product by process” limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Pilkington 162 USPQ 145, 147; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. The applicant must show that different methods of manufacturing produce articles having inherently different characteristics, Ex parte Skinner 2 USPQ 2d 1788.
As such, the claim language does not distinguish from the device of Naito, who teaches the structure as claimed;
and an internal thermal conductivity of the hole is smaller than a thermal conductivity of the silicon carbide substrate (see fig. 1 and [0024]: backside metal layer 30 covers the sidewalls of via holes 32 as shown in fig. 1, however Naito is silent as to the material occupying the remaining space in via holes 32 (as shown in fig. 1); therefore, we can conclude that the remaining space within via holes 32 is occupied by air;
see evidentiary reference Salmon [0138]: “[a]ir has a thermal conductivity of 0.028 W/m° K”.; also see evidentiary reference Cavanaugh [0017]: “silicon carbide has a thermal conductivity of 200 W/m*K”; therefore, the thermal conductivity of air is far less than the thermal conductivity of silicon carbide).
Regarding claim 8, Naito discloses the semiconductor device according to claim 1, wherein the silicon carbide substrate (fig. 1, 10; see [0045]) has a plurality of holes (fig. 2, 32; c.f. fig. 1 and note that the plurality of via holes 32 in fig. 2 extend through substrate 10; see [0022] and note that fig. 1 is a cross-sectional view of fig. 2), and in a front surface of the nitride semiconductor layer (fig. 1, 18), all shortest straight lines from respective points of the transistor (fig. 2, 40; see [0023]) to the element (fig. 2, 42; see [0023]) pass through regions (see fig. 2; such regions are defined by pad 34) where the plurality of holes are projected onto the front surface (see fig. 2; c.f. fig. 1: via holes 32 are projected onto a front surface of electron supply layer 18 within isolation region 28; see [0023]-[0024] and note that isolation region 28 comprises an inactivated portion of electron supply layer 18 ([0022] confirms that electron supply layer 18 is included in compound semiconductor layer 21);
see fig. 2 and note that all shortest straight lines from respective points of first FET 40 ([0023] confirms that both first and second FETs 40 and 42 are defined solely by “source electrodes 22, gate electrodes 26 and drain electrodes 24”) to second FET 42 pass through regions wherein via holes 32 are projected onto said front surface of electron supply layer 18).
Regarding claim 10, Naito discloses the semiconductor device according to claim 1, wherein the element (fig. 1, 42; see [0023]) is an active element (see [0004] and [0023]; first and second FETs 40 and 42 are formed within respective active regions 27 and are both active elements).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
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Claims 1-2 and 5-6 are rejected under 35 U.S.C. 103 as obvious over Okamoto (JP 2011192836 A), hereinafter referred to as “Okamoto” (note that all page and line citations from Okamoto reference the copy of Okamoto included with this office action), in view of Barth et al. (US 20100078776 A1), hereinafter referred to as “Barth”;
[Sharma et al. (US 20220084817 A1), hereinafter referred to as “Sharma”, and Cavanaugh are utilized herein as evidence].
Regarding claim 1, Okamoto discloses teachings related to monolithic microwave integrated circuits (see Okamoto page 1: “Background Art”) and specifically a semiconductor device (Okamoto fig. 2F (r); see Okamoto page 2, lines 20-21, and page 5, lines 14-19, and note that fig. 2F (r) shows the completed first embodiment of the invention disclosed in Okamoto) comprising:
a silicon carbide substrate (Okamoto fig. 2F (r), 1; see Okamoto page 5, lines 14-15);
a nitride semiconductor layer (Okamoto fig. 2F (r), 2; see Okamoto page 5, line 1: layer 2 is made of Gallium nitride (GaN)) provided on a top surface of the silicon carbide substrate (see Okamoto fig. 2F (r));
a transistor (see Okamoto fig. 2A (c) and page 2, lines 34-38, and page 3, lines 1-5; the HEMT transistor comprises source electrode 5s, drain electrode 5d, and gate electrode 5g all provided on active region 3 which comprises an activated portion of gallium nitride layer 2 (see Okamoto page 2, lines 31-33); c.f. Okamoto fig. 2F (r) and note the location of the transistor on SiC substrate 1) provided on the nitride semiconductor layer;
and an element (see annotated Okamoto fig. 2F (r) and page 3, lines 6-16, and page 3, line 21, and page 4, lines 2-4: the element is a MIM capacitor which consists of the indicated lower electrode 11, the indicated portion of dielectric layer 12 which acts as a capacitive insulating film, and an indicated portion of Nickel layer 14 as an upper electrode; note that the MIM capacitor is provided on the SiC substrate 1) provided on or above the silicon carbide substrate.
Okamoto fails to disclose wherein the silicon carbide substrate has a hole that is provided between the transistor and the element, the hole is formed by removing at least a part of the silicon carbide substrate from a bottom surface of the silicon carbide substrate and an internal thermal conductivity of the hole is smaller than a thermal conductivity of the silicon carbide substrate.
Barth discloses shielding techniques for high-frequency components on an integrated circuit (see Barth [0006]; see Barth fig. 1 for a representative integrated circuit). Specifically, Barth discloses an RF shield (Barth fig. 2c, 8; c.f. Barth fig. 1) surrounding a high frequency generating component within a semiconductor substrate (Barth fig. 5j, 10; see Barth [0043]: “[t]he substrate 10 is typically a semiconductor wafer”; also see Barth [0010], [0042], and [0057], and note that fig. 5j is a cross-sectional view of the RF shield shown in Barth fig. 2c), the RF shield comprising backside redistribution lines (Barth figs. 2c, 52; c.f. Barth fig 5j; also see [0030]) surrounding an RF component (Barth fig. 2c, 1; see Barth [0043]), the redistribution lines being connected to through substrate conductors (Barth fig. 2c, 25; c.f. Barth fig. 5j; also note that through substrate conductors 25 comprise first conductive layer 41). The RF shield serves to protect other adjacent IC components (see Barth fig. 1: e.g. 2, 3, 4, 5) from damaging electromagnetic radiation produced by the RF component (Barth, fig. 2c, 1; c.f. Barth fig. 1; see Barth [0021]). The through substrate conductors of the RF shield are disposed within through substrate openings (Barth fig. 5f, 35; c.f. Barth fig. 5j; see Barth [0013] and note that Barth figs. 5a-5j show fabrication stages of the same RF shield) at regular intervals around the perimeter of the RF component (see Barth fig. 2c), the through substrate openings extending to first metal lines (Barth fig. 5j, 63) within interconnect layers (Barth fig. 5j, 60) of the integrated circuit. Aside from the through substrate conductors (i.e. first conductive layer 41 in Barth fig. 5j), the through substrate openings are also filled with several elements such as a sidewall dielectric layer (Barth fig. 5j, 26; see [0052]; note that despite its name, the sidewall dielectric layer “is deposited conformally over all three exposed surfaces of the through substrate opening 35” in order to electrically isolate material within the through substrate opening 35), a barrier liner (Barth fig. 5j, 48; see [0053]), and an interior insulating layer (Barth fig. 5j, 45, see Barth [0057]).
The through substrate opening of Barth comprising a metal line acting as an etch stop (see Barth [0050] and Barth fig. 5c; note that landing pad 63a is a bottom surface of first metal line 63 and acts as an etch stop for the through substrate opening; thus metal line 63 (and landing pad 63a) is a necessary component of the through substrate hole) above a through substrate opening filled with a sidewall dielectric layer, a barrier layer, a conductive layer, and an insulating layer, are incorporated into the semiconductor device of Okamoto between the HEMT transistor and the MIM capacitor wherein the through substrate opening extends through the various backside layers, SiC substrate, and GaN layer, and wherein the metal line (i.e. etch stop) is provided above GaN layer 2 and below dielectric layer 12 (see Okamoto fig. 2F (r)). Therefore, the combination discloses wherein the silicon carbide substrate has a hole (see Barth fig. 5j: the hole comprises the through substrate opening 35 filled with sidewall dielectric layer 26, barrier layer 48, first conductive layer 41, and third insulating layer 45) that is provided between the transistor (see annotated Okamoto fig. 2F (r)) and the element (MIM capacitor in annotated fig. 2F (r));
the language “formed by removing at least a part of the silicon carbide substrate from a bottom surface of the silicon carbide substrate” is directed towards the process of manufacturing the semiconductor device. It is well settled that “product by process” limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Pilkington 162 USPQ 145, 147; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. The applicant must show that different methods of manufacturing produce articles having inherently different characteristics, Ex parte Skinner 2 USPQ 2d 1788.
As such, the claim language does not distinguish from the combined device of Okamoto and Barth, which teaches the structure as claimed;
and an internal thermal conductivity of the hole is smaller than a thermal conductivity of the silicon carbide substrate (see Barth fig. 5j and note that sidewall dielectric layer 26 comprises an interior of the hole in the combined device; see Barth [0039]: “[t]he sidewall dielectric layer 26 is an oxide such as silicon oxide”;
see evidentiary reference Sharma: [0056]: “silicon oxide has thermal conductivity in the range of 0.2 to 2 Watt × meter.sup.−1 Kelvin.sup.−1”.; c.f. evidentiary reference Cavanaugh [0017]: “silicon carbide has a thermal conductivity of 200 W/m*K”; therefore, the thermal conductivity of silicon oxide is far less than the thermal conductivity of silicon carbide).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Okamoto with the teachings of Barth in order to minimize electromagnetic interference between the transistor and the element (see Barth [0021]).
Regarding claim 2, Okamoto and Barth disclose the semiconductor device according to claim 1, further comprising:
a metal layer (Okamoto fig. 2F (r), 34; see Okamoto page 5, lines 14-19: layer 34 is made of gold (Au); also note that via wiring 36 is formed of gold film 34 and seed metal film 33) electrically connected to the transistor (see Okamoto fig. 2A (c) and page 2, lines 34-38, and page 3, lines 1-5; the HEMT transistor comprises source electrode 5s, drain electrode 5d, and gate electrode 5g all provided on active region 3 which comprises an activated portion of gallium nitride layer 2 (see Okamoto page 2, lines 31-33) ; c.f. Okamoto fig. 2F (r) and note the location of the transistor on SiC substrate 1) via a via hole (Okamoto fig. 2F (r), 1b; see Okamoto page 4, lines 2-7: note that the nickel film 14 is used as an etch stopper for both via holes 1a and 1b; Okamoto discloses that film 14 “becomes part of the upper electrode” of the MIM capacitor; see further Okamoto page 4, lines 10-23, and note that film 16 becomes source wiring 16s which connects source electrode 5s of the HEMT transistor with etch stopper 14e via seed metal 15; see Okamoto page 5, lines 22-23, and note that via wiring 36 is connected to upper electrode 14a of the indicated MIM capacitor; this implies that the portion of via wiring 36 in via hole 1b connects with etch stopper 14e since etch stopper 14e and upper electrode 14a are made from the same material; thus, via wiring 36 connects source electrode 5s through via hole 1b; also note that the disclosed HEMT transistor would be inoperable if not electrically connected to via wiring 36) that penetrates through the silicon carbide substrate and the nitride semiconductor layer (see Okamoto fig. 2F (r): via hole 1b penetrates through SiC substrate 1 and GaN layer 2).
Regarding claim 5, Okamoto and Barth disclose the semiconductor device according to claim 2, wherein the hole (see Barth fig. 5j: the hole comprises the through substrate opening filled with sidewall dielectric layer 26, barrier layer 48, first conductive layer 41, and third insulating layer 45) penetrates through the silicon carbide substrate and the nitride semiconductor layer (see annotated Okamoto fig. 2F (r) and note that, in the combined device, the through substrate opening penetrates through the SiC substrate 1 and GaN layer 2), and the semiconductor device further comprises a pad (Barth fig. 5j, 63; note that, in the combined device, the through substrate opening comprises metal line 63 provided above the through substrate opening (and SiC substrate 1; see annotated figure above) and below the dielectric layer (i.e. dielectric layer 12 as shown in Okamoto fig. 2F (r)) that is provided on or above the silicon carbide substrate, overlaps with the hole as viewed from a thickness direction of the silicon carbide substrate (see annotated figure above) , and is in contact with the hole (see Barth fig. 5j; the metal line 63 is in contact with the through substrate opening).
Regarding claim 6, Okamoto and Barth disclose the semiconductor device according to claim 5, wherein the pad (Barth fig. 5j, 63; note that, in the combined device, the through substrate opening comprises a metal line (acting as an etch stop) provided above the through substrate opening (and SiC substrate 1; see annotated figure above) and below the dielectric layer (i.e. dielectric layer 12 as shown in Okamoto fig. 2F (r)) is electrically separated from the metal layer (Okamoto fig. 2F (r), 34; see Okamoto page 5, lines 14-19: layer 34 is made of gold (Au);
see annotated figure above; see Barth [0052] and note that sidewall dielectric layer 26 electrically isolates other interior contents of the through substrate opening from active devices; see Barth [0035] and note that the metallization layers (including first metal line 63) in interconnect layers 60 are used to interconnect the components of the integrated circuit (also note that the interconnect layers 60 in Barth fig. 4A describe identical structures as the interconnect layers 60 in Barth fig. 5j); therefore, sidewall dielectric layer 26 electrically separates the metal line (first metal line 63 from Barth) from the metal layer (Okamoto fig 2F (r), 34) in the combined device).
Claims 3 and 4 are rejected under 35 U.S.C. 103 as obvious over Green in view of Hosoi et al. (JP 2009231371 A), hereinafter referred to as “Hosoi” (note that all page and line citations from Hosoi reference the copy of Hosoi included with this office action).
Regarding claim 3, Green discloses the semiconductor device according to claim 1.
Green fails to explicitly disclose wherein the hole is provided from a bottom surface of the silicon carbide substrate to the middle of the silicon carbide substrate and does not penetrate through the silicon carbide substrate and the nitride semiconductor layer.
Hosoi discloses a semiconductor chip (Hosoi fig. 4a, 3; see Hosoi page 7, line 26: “semiconductor chip 3”; see Hosoi page 3, lines 27-31, and note that the semiconductor chip may include an integrated circuit with various elements (see Hosoi page 7, lines 23-25, and note that semiconductor substrate 11 in the embodiment of fig. 4 is the same as earlier disclosed embodiments); also see Hosoi page 7, lines 18-20, and note that fig. 4a is a plan view of the bottom surface of the disclosed semiconductor chip and fig. 4b is cross-sectional view of said semiconductor chip) including a semiconductor substrate (Hosoi fig. 4b, 11; see Hosoi page 3, lines 24-26), wherein through holes (Hosoi fig. 4b, 21; see Hosoi page 4, lines 7-17; see Hosoi page 7, lines 23-25, and note that through holes 21 in the embodiment of fig. 4 are the same as earlier disclosed embodiments) and a heat radiation hole (Hosoi fig. 4b, 61; see Hosoi page 7, lines 33-43) extend from a backside of the semiconductor substrate (see Hosoi fig. 4b, page 3, lines 16-17, and page 7, lines 33-35) and wherein the heat radiation hole is provided from a bottom surface of the substrate to the middle of the substrate (see Hosoi fig. 4b and page 7, lines 33-35; the heat radiation hole 61 extends from the bottom surface of substrate 11 to the middle of substrate 11 and does not penetrate through substrate 11) and does not penetrate through the substrate.
The heat radiation hole of Hosoi is incorporated as the substrate cavity of Green within the silicon carbide host substrate, wherein the heat radiation hole is incorporated between the transistor (Green fig. 2, 120) and the element (Green fig. 2, 130). The combination, thus, discloses wherein the hole (Hosoi fig. 4b, 61; see Hosoi page 7, lines 33-43) is provided from a bottom surface of the silicon carbide substrate (Green fig. 2, 212; see Green fig. 2, [0025], [0031], and [0044]; note that the various nitride layers (214, 216, 218, etc.) are formed over the entirety of host substrate 212; see Green [0031] and note that the various nitride layers are inactivated outside of active region 114 by an ion implantation procedure) to the middle of the silicon carbide substrate (see Hosoi page 7, lines 33-34: “heat radiation hole 61 of the connection terminal 57c reaches the central portion … of the semiconductor substrate 11”) and does not penetrate through the silicon carbide substrate and the nitride semiconductor layer (Green fig. 2, 214; see Green [0025]; in the combined device, heat radiation hole of Hosoi penetrates to the middle of the silicon carbide substrate of the device of Green and does not penetrate through the nitride semiconductor layer overlaying the silicon carbide substrate; further, the teachings of Green regarding the substrate cavity being filled with air (see Green [0042]-[0043]) are retained in the combined device such that the heat radiation hole of Hosoi is filled with air).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Green with the heat radiation hole as taught in Hosoi to dissipate heat by radiation and conduction (see Hosoi page 8, lines 4-8) and reduce the manufacturing time required to form the cavity (thereby conserving costs during fabrication); and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the substrate cavity of Green (Green fig. 2, 160) with the heat radiation hole of Hosoi (Hosoi fig. 4b, 61) to obtain predictable results (i.e. reduced manufacturing time).
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Regarding claim 4, the combined device of Green and Hosoi discloses the semiconductor device according to claim 3, further comprising:
a metal layer (Green fig. 2, 142; see Green [0039]) electrically connected to the transistor (Green fig. 2, 120; note that Green [0032] discloses that the transistor 120 includes the electrodes and semiconductor layers included in active region 114; see Green [0044] and note that the transistor is electrically coupled to backside contact 142 via through wafer via 168) via a via hole (Green fig. 2, 168; see [0044]) that penetrates through the silicon carbide substrate and the nitride semiconductor layer (see Green fig. 2, [0025], [0031], and [0044]: through wafer vias 168 penetrate through host substrate 212 and the inactivated nitride semiconductor layers (including the inactivated portion of buffer layer 214) in isolation region 112 to electrically couple transistor 120 to backside contact 142).
The combined device of Green and Hosoi does not explicitly disclose wherein a planar area of the hole in the bottom surface of the silicon carbide substrate is smaller than a planar area of the via hole in the bottom surface of the silicon carbide substrate.
Hosoi discloses a semiconductor chip (Hosoi fig. 4a, 3; see Hosoi page 7, line 26: “semiconductor chip 3”; see Hosoi page 3, lines 27-31, and note that the semiconductor chip may include an integrated circuit with various elements (see Hosoi page 7, lines 23-25, and note that semiconductor substrate 11 in the embodiment of fig. 4 is the same as earlier disclosed embodiments); also see Hosoi page 7, lines 18-20, and note that fig. 4a is a plan view of the bottom surface of the disclosed semiconductor chip and fig. 4b is cross-sectional view of said semiconductor chip) including a semiconductor substrate (Hosoi fig. 4b, 11; see Hosoi page 3, lines 24-26), wherein through holes (Hosoi fig. 4b, 21; see Hosoi page 4, lines 7-17; see Hosoi page 7, lines 23-25, and note that through holes 21 in the embodiment of fig. 4 are the same as earlier disclosed embodiments) and a heat radiation hole (Hosoi fig. 4b, 61; see Hosoi page 7, lines 33-43) extend from a backside of the semiconductor substrate (see Hosoi fig. 4b, page 3, lines 16-17, and page 7, lines 33-35) and wherein a planar area of the hole (Hosoi fig. 4b, 61; c.f. Hosoi fig. 4a) in the bottom surface of the semiconductor substrate (Hosoi fig. 4b, 11) is smaller than a planar area of the via hole (Hosoi fig. 4b, 21; c.f. Hosoi fig. 4a) in the bottom surface of the semiconductor substrate (see annotated Hosoi fig. 4a and fig. 4b; see Hosoi page 4, lines 7-17; note that through holes 21 are indicated in fig. 4a by through wirings 25 which fill through holes 21 (see Hosoi fig. 4b); the two larger concentric circles (one of which is indicated in the annotated fig. 4a above) at opposite ends of Line CC in fig. 4a depict the planar areas of through holes 21 on the bottom surface of semiconductor substrate 11; the planar area of the heat radiation hole 61 on the bottom surface of substrate 11 is shown at the center of line CC (c.f. Hosoi fig. 4b); note that the planar area of the heat radiation hole 61 is smaller than the planar area of the through holes 21 in the bottom surface of substrate 11).
The through hole of Hosoi is incorporated as the via hole of the combined device of Green and Hosoi wherein the combination discloses wherein a planar area of the hole (Hosoi fig. 4b, 61) in the bottom surface of the silicon carbide substrate (Green fig. 2, 212) is smaller than a planar area of the via hole (Hosoi fig. 4b, 21) in the bottom surface of the silicon carbide substrate (note that the combination preserves the relative planar areas of the heat radiation hole and the through hole from Hosoi).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Green and Hosoi with the through hole as taught in Hosoi because the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the through wafer via of Green (Green fig. 2, 168) with the through hole of Hosoi (Hosoi fig. 4b, 21) to obtain the predictable result of coupling a frontside integrated circuit element (e.g. a transistor) with a backside metal connection (it should be noted that via holes and their function in connecting elements through a semiconductor substrate are well known in the art).
Conclusion
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/HAMNER FITZHUGH COLLINS IV/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818