DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) rejected have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 12-14, 17-19 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Won et al. 20210376038.
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Regarding claim 1, figs. 9A, B and 15 of Won discloses a display panel comprising:
a substrate 100 comprising a central area MDA and a corner area (CDA1/2) extending from a corner of the central area;
a pixel circuit PC1/WL1 (par [0153]) disposed in the central area and a display element (par [0076]) connected to the pixel circuit (see figs. 7-8);
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a voltage supply line ELVSS which is disposed in the corner area, electrically connected to one electrode 230 of the display element and supplies a common voltage ELVSS to the one electrode (opposite electrode 230) of the display element; and
a driving circuit PC2/WL2 (par [0153]) which is disposed in the corner area, and supplies an electrical signal to the pixel circuit (WL2 connected to WL1), and includes a driving circuit transistor,
wherein the driving circuit PC2/WL2 is spaced apart from the central area with the voltage supply line therebetween.
Regarding claim 17, Won discloses a display panel comprising:
a substrate comprising a central area MDA and a corner area extending from a corner of the central area, wherein the corner area comprises a first corner area CDA2 adjacent to the central area and a second corner area CDA1 outside the first corner area;
a pixel circuit PC1 (par [0153]) disposed in the central area and a display element connected to the pixel circuit (fig. 8);
a voltage supply line ELVSS which is disposed in the first corner area, electrically connected to one electrode 230 of the display element, and supplies a common voltage VSS to the one electrode 230 of the pixel circuit;
a driving circuit PC2 (par [0153]) which is disposed in the second corner area, and supplies an electrical signal to the pixel circuit, and includes a driving circuit transistor; and
an input line WL2 which is disposed outside the voltage supply line ELVSS in the corner area and transmits a signal to the driving circuit (fig. 9A).
Regarding claim 21, (see rejection of claim 1 above) Won discloses an electronic device comprising:
a display apparatus comprising:
a display panel comprising:
a substrate comprising a central area and a corner area extending from a corner of the central area;
a pixel circuit disposed in the central area and a display element connected to the pixel circuit;
a voltage supply line which is disposed in the corner area, electrically connected to one electrode of the display element and supplies a common voltage to the one electrode of the display element; and
driving circuit which is disposed in the corner area, supplies an electrical signal to the pixel circuit, and includes a driving circuit transistor,
wherein the driving circuit is spaced apart from the central area with the voltage supply line therebetween.
Regarding claim 2, fig. 9A of Won discloses wherein the corner area comprises a first corner area CDA2 adjacent to the central area and a second corner area CDA1 outside the first corner area, wherein the voltage supply line is disposed in the first corner area, and the driving circuit is disposed in the second corner area.
Regarding claim 3, par [0178] of Won discloses further comprising a thin- film encapsulation layer disposed on the display element, wherein the thin-film encapsulation layer comprises a first inorganic encapsulation layer, an organic encapsulation layer on the first inorganic encapsulation layer, and a second inorganic encapsulation layer on the organic encapsulation layer.
Regarding claim 4, par [0178] of Won necessary discloses wherein the first inorganic encapsulation layer and the second inorganic encapsulation layer contact each other in the first corner area and the second corner area (as the organic light emitting device are in those areas).
Regarding claim 6, it is necessary the case that Won discloses wherein, in a cross- sectional view, the first inorganic encapsulation layer and the second inorganic encapsulation layer are spaced apart from each other in a portion of the first corner area (as the organic encapsulation layer is in between).
Regarding claim 12, fig. 10A of Won discloses further comprising: a first input line SL2-1 (portion at the border of CDA1 and CDA2) disposed in the first corner area; a second input line SL2-1 (portion at the end of CDA1) disposed in the second corner area and connected to the driving circuit; and a third input line (portion of SL2-1 in between) connecting the first input line to the second input line.
Regarding claim 13, Won discloses wherein each of the first input line, the second input line, and the third input line is spaced apart from the central area with the voltage supply line therebetween (see fig. 10A and fig. 15 together).
Regarding claim 14, fig. 10B of Won discloses wherein the first input line is disposed in a same layer (SL layer) as the second input line and is disposed in a different layer (in layer 119 which is different) from the third input line (which is SL layer).
Regarding claim 18 (see rejection of claims 3 and 5), Won discloses further comprising a thin-film encapsulation layer comprising a first inorganic encapsulation layer disposed on the display element, an organic encapsulation layer on the first inorganic encapsulation layer, and a second inorganic encapsulation layer on the organic encapsulation layer, wherein the organic encapsulation layer is disposed in the central area and the corner area, and does not overlap the driving circuit.
Regarding claim 19, fig. 11B of Won discloses wherein the input line comprises a first input line CNT3a disposed in the first corner area, a second input line CNT3b disposed in the second corner area and connected to the driving circuit, and a third input line BL3 connecting the first input line to the second input line, wherein the third input line comprises a 3-1st input line BL3 disposed in a layer at a lower level than the first input line, and a 3-2nd input line WL disposed in a layer at a higher level than the first input line.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 7-8 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Won.
Regarding claim 5, Won discloses claim 4, but does no explicitly discloses wherein the organic encapsulation layer overlaps at least a part of the voltage supply line and does not overlap the driving circuit.
However, par [0178] Because the organic light emitting device may be easily damaged by moisture or oxygen from the outside, an encapsulation layer (not illustrated) may cover and protect the organic light emitting device to protect. The encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and/or a second inorganic encapsulation layer.
Note fig. 15 of Won discloses that the ELVSS in CD2 which has OLED and fig. 9A of Won disclose that driving circuit is in CDA1 without OLED.
Therefore, it would have been obvious to form structure of Won wherein the organic encapsulation layer overlaps at least a part of the voltage supply line and does not overlap the driving circuit as the driving circuit does not require full protection as that of OLED from moisture.
Regarding claim 7, fig. 15 of Won discloses further comprising a dam (organic encapsulation layer which a type of a dam).
It would have been obvious to form the dam provided over the voltage supply line ELVSS to at least partially overlap the voltage supply line, the dam being disposed between the pixel circuit and the driving circuit (as the pixel circuit is part driving OLED need encapsulant as state in par [0178] and driving circuit does not need full protection of OLED therefore no full encapsulant as stated in par [0178]).
Regarding claim 8, fig. 4A of Won discloses wherein the second corner area comprises a plurality of extending areas, and the driving circuit comprises a plurality of sub-driving circuits (it can be divide in sub parts as shown in fig. 9B showing many parts), and it would have been obvious to form a structure wherein at least one of the plurality of sub-driving circuits is disposed in each of the plurality of extending areas in order to have each WL extending area in order to supply WL signal to the pixels, and Won discloses wherein a separation area is defined between adjacent extending areas among the plurality of extending areas.
Regarding claim 20 (see rejection of claim 8), Won discloses wherein the second corner area comprises a plurality of extending areas, and the driving circuit comprises a plurality of sub-driving circuits, wherein at least one of the plurality of sub-driving circuits is disposed in each of the plurality of extending areas, and wherein a separation area is defined between adjacent extending areas among the plurality of extending areas.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST.
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/VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893
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