DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
The applicant amended claims 1, 3-4, 9-10, 13-14, 16, and 18 in the reply dated 25 June 2026. Claim 2 has been cancelled.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 8-9, 13-15, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al (US 20200105583 A1, hereinafter “Wang”).
Regarding Claim 1 – Wang discloses a semiconductor device comprising: a substrate (50 [0034] and Figs. 1 and 26) extending a first direction (X-direction in annotated Fig. 26) and a second direction perpendicular to the first direction (Y-direction in annotated Fig. 26); active patterns positioned on the substrate (Fins 52 [0034] and Fig. 26); a first isolation layer (Combination of 56 and 154 [0078], First in annotated Fig. 26) and a second isolation layer (Combination of 56 and 154 [0078], Second in annotated Fig. 26) positioned between the active patterns (Fig. 26); a first protection liner formed within a first recess of the first isolation layer such that the first isolation layer contacts and surrounds lateral surfaces of the first protection liner (164 [0082] and First in annotated Fig. 26); a second protection liner formed within a second recess of the second isolation layer such that the second isolation layer contacts and surrounds lateral surfaces of the second protection liner (164 [0082] and Second in annotated Fig. 26); channel patterns positioned on the active patterns (Exposed region of 52 in 90 [0071] and Fig. 20B, and region overlapped by 66 in Fig. 1 [0057]); source/drain patterns positioned on both sides of the channel patterns (82 [0071] and Fig. 1); and a first gate electrode positioned above the first protection liner and the second protection liner (170 [0086] and Fig. 26 replaced by metal gate [0087]), and surrounding the channel patterns (70 [0057] and Fig. 1), wherein the first isolation layer has a first width in the second direction (W1 in annotated Fig. 26), wherein the second isolation layer has a second width (W2 in annotated Fig. 26), in the second direction, wider than the first width (W2 > W1 as indicated by section cut lines in Fig. 26), wherein a first height (H1) from the substrate to the first protection liner is greater than a second height (H2) from the substrate to the second protection liner (H1 > H2 in annotated Fig. 26), wherein the first isolation layer is a first monolithic insulating region (Layer 154 may comprise the same dielectric material as layer 54 [0078], and 54 and 56 may comprise the same dielectric material, for example silicon oxide or nitride [0041], making 56 and 154 monolithic in structure), wherein the second isolation layer is a second monolithic insulating region (Layer 154 may comprise the same dielectric material as layer 54 [0078], and 54 and 56 may comprise the same dielectric material, for example silicon oxide or nitride [0041], making 56 and 154 monolithic in structure), wherein side surfaces and a bottom surface of the first recess are defined by the first isolation layer (Fig. 26), and the first protection liner covers the side surfaces and the bottom surface of the first recess (Fig. 26), and wherein side surfaces and a bottom surface of the second recess are defined by the second isolation layer (Fig. 26), and the second protection liner covers the side surfaces and the bottom surface of the second recess (Fig. 26).
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Regarding Claim 3 – Wang discloses the semiconductor device of claim 1, wherein the depth of the second recess is greater than the depth of the first recess (D2>D1 in annotated Fig. 26).
Regarding Claim 8 – Wang discloses the semiconductor device of claim 1, wherein in the second direction, the width of the second protection liner is greater than the width of the first protection liner (W2 > W1, annotated Fig. 26).
Regarding Claim 9 – Wang discloses the semiconductor device of claim 1, wherein the first protection liner and the second protection liner include silicon nitride (64 [0053]).
Regarding Claim 13 – Wang discloses a semiconductor device comprising: a substrate (50 [0034] and Figs. 1 and 26) extending a first direction (X-direction in annotated Fig. 26) and a second direction (Y-direction in annotated Fig. 26) perpendicular to the first direction (Annotated Fig. 26); active patterns positioned on the substrate (Fins 52 [0034] and Fig. 26); a first isolation layer and a second isolation layer positioned between the active patterns (Combination of 56 and 154 [0078] between 52 in Fig. 26); a first protection layer including a first protection liner, the first protection layer formed within a first recess of the first isolation layer (164 in First [0082] and annotated Fig. 26); a second protection layer including a second protection liner, the second protection layer formed within a second recess of the second isolation layer (164 in Second [0082] and annotated Fig. 26); channel patterns positioned on the active patterns (Exposed region of 52 in 90 [0071] and Fig. 20B, and region overlapped by 66 in Fig. 1 [0057]); source/drain patterns positioned on both sides of the channel patterns (82 [0071] and Fig. 1); and a first gate electrode positioned on the active patterns, the first protection layer, and the second protection layer (170 [0086] and Fig. 26 replaced by metal gate [0087]), and surrounding the channel patterns (70 [0057] and Fig. 1), wherein the first isolation layer is a first monolithic insulating region (Layer 154 may comprise the same dielectric material as layer 54 [0078], and 54 and 56 may comprise the same dielectric material, for example silicon oxide or nitride [0041], making 56 and 154 monolithic in structure), wherein the second isolation layer is a second monolithic insulating region (Layer 154 may comprise the same dielectric material as layer 54 [0078], and 54 and 56 may comprise the same dielectric material, for example silicon oxide or nitride [0041], making 56 and 154 monolithic in structure), wherein side surfaces and a bottom surface of the first recess are defined by the first isolation layer (Fig. 26), and the first protection liner covers the side surfaces and the bottom surface of the first recess (Fig. 26), and wherein side surfaces and a bottom surface of the second recess are defined by the second isolation layer (Fig. 26), and the second protection liner covers the side surfaces and the bottom surface of the second recess (Fig. 26).
Regarding Claim 14 – Wang discloses the semiconductor device of claim 13, wherein the first isolation layer has a first width and a second isolation layer has a second width wider than the first width in the second direction (W2 > W1 as indicated by section cut lines in Fig. 26), and wherein the depth of the second protection layer is greater than the depth of the first protection layer (D2 > D1 in annotated Fig. 26).
Regarding Claim 15 – Wang discloses the semiconductor device of claim 14, wherein the width of the second protection layer is greater than the width of the first protection layer in the second direction (W2 > W1, annotated Fig. 26).
Regarding Claim 18 – Wang discloses a semiconductor device comprising: a substrate (50 [0034] and Figs. 1 and 26) extending a first direction (X-direction in annotated Fig. 26) and a second direction perpendicular to the first direction (Y-direction in annotated Fig. 26); active patterns positioned on the substrate (Fins 52 [0034] and Fig. 26); a first isolation layer and a second isolation layer positioned between the active patterns (Combination of 56 and 154 [0078] between 52, First and Second in Fig. 26); a first recess disposed in the upper surface of the first isolation layer (D1 in annotated Fig. 26); a second recess disposed in the upper surface of the second isolation layer (D2 in annotated Fig. 26); a first protection liner covering side surfaces and a bottom surface of the first recess (164 [0082] and First in annotated Fig. 26); a second protection liner covering side surfaces and a bottom surface of the second recess (164 [0082] and Second in annotated Fig. 26); channel patterns positioned on the active patterns (Exposed region of 52 in 90 [0071] and Fig. 20B); source/drain patterns positioned on both sides of the channel patterns (82 [0071] and Fig. 1); and a first gate electrode positioned above the first protection liner and the second protection liner (170 [0086] and Fig. 26 replaced by metal gate [0087]), and surrounding the channel patterns (70 [0057] and Fig. 1), wherein the first isolation layer has a first width in the second direction (W1 in annotated Fig. 26), wherein the second isolation layer has a second width, in the second direction (W2 in annotated Fig. 26), wider than the first width (W2 > W1 as indicated by section cut lines in Fig. 26), wherein the depth of the second recess is greater than the depth of the first recess (D2 > D1 in annotated Fig. 26), wherein the first isolation layer is a first monolithic insulating region (Layer 154 may comprise the same dielectric material as layer 54 [0078], and 54 and 56 may comprise the same dielectric material, for example silicon oxide or nitride [0041], making 56 and 154 monolithic in structure), wherein the second isolation layer is a second monolithic insulating region (Layer 154 may comprise the same dielectric material as layer 54 [0078], and 54 and 56 may comprise the same dielectric material, for example silicon oxide or nitride [0041], making 56 and 154 monolithic in structure), wherein side surfaces and a bottom surface of the first recess are defined by the first isolation layer (Fig. 26), and wherein side surfaces and a bottom surface of the second recess are defined by the second isolation layer (Fig. 26).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-7, 16-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al (US 20200105583 A1, hereinafter “Wang”), in view of Glass et al (US 20180248015 A1, hereinafter “Glass”).
Regarding Claim 4 – Wang discloses all the limitations of claim 2.
Wang fails to disclose a first protection insulation layer is positioned on the first protection liner within the first recess, and wherein a second protection insulation layer is positioned on the second protection liner within the second recess.
However, Glass discloses a first protection insulation layer (222 [0026] and First in annotated Fig. 2K’) is positioned on the first protection liner (260’ [0028] and First in annotated Fig. 2K’) within the first recess, and wherein a second protection insulation layer (222 [0026] and Second in annotated Fig. 2K’) is positioned on the second protection liner (260’ [0028] and Second in annotated Fig. 2K’) within the second recess.
Glass discloses an analogous transistor structure to Wang. Glass teaches a protection liner under a protection insulation layer in the isolation structure for the benefit of reducing sub-channel interface traps (Glass [0028]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Wang and Glass to place a protection liner under the protection insulation layer in the isolation structure for the benefit of reducing sub-channel interface traps.
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Regarding Claim 5 – Wang modified by Glass discloses all the limitations of claim 4.
The combination of Wang and Glass further discloses in the second direction, the width of the second protection insulation layer is wider than the width of the first protection insulation layer (W2 > W1 as indicated by section cut lines in Wang Fig. 26).
Regarding Claim 6 – Wang modified by Glass discloses all the limitations of claim 4.
The combination of Wang and Glass further discloses the depth of the second protection insulation layer is greater than the depth of the first protection insulation layer (D2 > D1 in annotated Wang Fig. 26).
Regarding Claim 7 – Wang modified by Glass discloses all the limitations of claim 4.
The combination of Wang and Glass further implicitly discloses etch selectivity of the first protection insulation layer (222 may be same material as 220, Glass [0026], and 220 may be silicon dioxide, Glass [0020]) and the first protection liner (260 may be silicon nitride, Glass [0028]) are different (Silicon dioxide is known to have high etch selectivity relative to silicon nitride to one of ordinary skill in the art in a wide array of wet and dry chemistries and processes. See MPEP 2144.01.).
Regarding Claim 16 – Wang discloses all the limitations of claim 14.
Wang fails to disclose the first protection layer includes a first protection insulation layer positioned on the first protection liner, and the second protection layer includes a second protection insulation layer positioned on the second protection liner.
However, Glass discloses the first protection layer includes a first protection insulation layer (222 [0026] at First in annotated Fig. 2K’) positioned on the first protection liner, and the second protection layer includes a second protection insulation layer (222 [0026] at Second in annotated Fig. 2K’) positioned on the second protection liner.
Glass discloses an analogous transistor structure to Wang. Glass teaches a protection liner under a protection insulation layer in the isolation structure for the benefit of reducing sub-channel interface traps (Glass [0028]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Wang and Glass to place a protection liner under the protection insulation layer in the isolation structure for the benefit of reducing sub-channel interface traps.
Regarding Claim 17 – Wang modified by Glass discloses all the limitations of claim 16.
The combination of Wang and Glass further discloses the width of the second protection liner is wider than the width of the first protection liner in the second direction (W2 > W1 as indicated by section cut lines in Wang Fig. 26).
Regarding Claim 19 – Wang discloses all the limitations of claim 18.
Wang fails to disclose a first protection insulation layer is positioned on the first protection liner within the first recess, and a second protection insulation layer is positioned on the second protection liner within the second recess.
However, Glass discloses a first protection insulation layer (222 [0026] and First in annotated Fig. 2K’) is positioned on the first protection liner (260’ [0028] and First in annotated Fig. 2K’) within the first recess, and a second protection insulation layer (222 [0026] and Second in annotated Fig. 2K’) is positioned on the second protection liner (260’ [0028] and Second in annotated Fig. 2K’) within the second recess.
Glass discloses an analogous transistor structure to Wang. Glass teaches a protection liner under a protection insulation layer in the isolation structure for the benefit of reducing sub-channel interface traps (Glass [0028]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Wang and Glass to place a protection liner under the protection insulation layer in the isolation structure for the benefit of reducing sub-channel interface traps.
Regarding Claim 20 – Wang modified by Glass discloses all the limitations of claim 19.
The combination of Wang and Glass further discloses the depth of the second protection insulation layer is greater than the depth of the first protection insulation layer (D2 > D1 in annotated Fig. 26).
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al (US 20200105583 A1, hereinafter “Wang”), in view of Bayati et al (US 20240105800 A1, hereinafter “Bayati”).
Regarding Claim 10 – Wang discloses all the limitations of claim 1.
Wang fails to disclose a second gate electrode is spaced apart from the first gate electrode and positioned on the second protection liner; and wherein a gate separation structure is positioned between the first gate electrode and the second gate electrode.
However, Bayati discloses a second gate electrode (118b, Bayati [0036] and Fig. 1A) is spaced apart from the first gate electrode (118a, Bayati [0036] and Fig. 1A) and positioned on the second protection liner (Wang 164 [0082] in place of Bayati 106 [0030]); and wherein a gate separation structure (120, Bayati [0035] and Fig. 1A) is positioned between the first gate electrode and the second gate electrode (Bayati Fig. 1A).
Bayati discloses an analogous transistor structure to Wang. Bayati teaches placing a gate separation structure for the benefit of isolating adjacent transistors (Bayati [0002]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to place a gate separation structure for the benefit of isolating adjacent transistors.
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Regarding Claim 11 – Wang modified by Bayati discloses all the limitations of claim 10.
The combination of Wang and Bayati further discloses the gate separation structure is positioned on the second protection liner (Wang Second 164 in Fig. 26 in place of Bayati 106 in Fig. 1A).
Regarding Claim 12 – Wang modified by Bayati discloses all the limitations of claim 10.
The combination of Wang and Bayati further discloses a gate insulating layer surrounding the channel patterns and positioned between the channel patterns and the first gate electrode (Wang Fig. 1).
Response to Arguments
Applicant's arguments filed 25 June 2026 have been fully considered but they are not persuasive.
The applicant asserts layer 164 is not formed in a recess of the combination of 154 and 56. The examiner respectfully disagrees, as 164 is clearly shown positioned in a space surrounded on all but one side by the combination of 154 and 56. Regardless of processing method, the application relates to a semiconductor device, and the structure of the reference (Wang) indicates positioned inside a recess, as explained above.
In addition, the applicant asserts that Wang does not disclose or suggest “wherein the first isolation layer is a first monolithic insulating region”. However, the structure referenced in Wang as an equivalent isolation layer consists of the combination of 154 and 56, which can be made up of the same material, as referenced above. Therefore, in terms of structure, the isolation layer of Wang consisting of layers 154 and 56 can be monolithic.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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/JASON MCDONALD/Examiner, Art Unit 2898
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