Prosecution Insights
Last updated: July 17, 2026
Application No. 18/226,846

DISPLAY APPARATUS INCLUDING CIRCUIT LAYER

Non-Final OA §102§103
Filed
Jul 27, 2023
Priority
Oct 07, 2022 — RE 10-2022-0128587 +1 more
Examiner
CRAWLEY, KEITH L
Art Unit
2626
Tech Center
2600 — Communications
Assignee
Samsung Display Co., Ltd.
OA Round
3 (Non-Final)
59%
Grant Probability
Moderate
3-4
OA Rounds
5m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 59% of resolved cases
59%
Career Allowance Rate
347 granted / 587 resolved
-2.9% vs TC avg
Strong +26% interview lift
Without
With
+26.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
23 currently pending
Career history
620
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
86.1%
+46.1% vs TC avg
§102
5.9%
-34.1% vs TC avg
§112
3.6%
-36.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 587 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/17/26 has been entered. Priority Acknowledgment is made of applicant's claim for foreign priority based on an applications filed in Korea on 3/6/23 and 10/7/22. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Chen et al. (CN 115004376, filed 4/29/22 and published 9/2/22; *note: Examiner will rely upon US 2024/0397762 as an English translation of CN 115004376). Regarding claim 1, Chen discloses a display device comprising: a substrate comprising a main region comprising: a display area in which emission areas are arranged; and a non-display area disposed around the display area (abstract, figs. 1-2, ¶ 98-101, display region 100 and bezel region 300); a circuit layer disposed on the substrate (figs. 1-2, ¶ 96-98, see also figs. 4-5, ¶ 105-109, e.g., circuit layer 102); and a light-emitting element layer disposed on the circuit layer and comprising light-emitting elements respectively corresponding to the emission areas (figs. 1-2, ¶ 96-98, see also figs. 4-5, ¶ 105-109, e.g., light emitting structure layer 103), wherein a detour area on a side of the display area comprises: a detour middle area at a center (fig. 6, ¶ 127-130; see also ¶ 131-141, e.g., area to immediate left of center line O); a first detour side area parallel to the detour middle area in a first direction and in contact with the non-display area (fig. 6, ¶ 127-130; see also ¶ 131-141, e.g., lower left corner of display area 100); and a second detour side area disposed between the detour middle area and the first detour side area (fig. 6, ¶ 127-130; see also ¶ 131-141, e.g., area between the area to immediate left of center line O and lower left corner), the circuit layer comprises: pixel drivers corresponding to the emission areas and electrically connected to the light-emitting elements of the light-emitting element layer, respectively (figs. 1-5, ¶ 96-98, ¶ 102-109, pixel drive circuits; see also ¶ 114-116); data lines which extend in a second direction crossing the first direction and transmit data signals to the pixel drivers (fig. 1, ¶ 96-97; see also fig. 6, figs. 9G-9I, ¶ 187-196, data lines 60); a first transmission detour line directly and electrically connected to, among the data lines, a first data line disposed in the first detour side area in the display area and extending in the first direction (fig. 6, ¶ 136-141; see also figs. 9E-9I, ¶ 180-181, first connection line 71 with integral protrusions 81; see also ¶ 187-196, data line 60 with integral protrusion 86 connected to protrusion 81 of first connection line 71 via V15); and a second transmission detour line adjacent to, among the data lines, a second data line disposed in the second detour side area, extending in the second direction, and electrically, physically and directly connected to the first transmission detour line in the display area (fig. 6, ¶ 136-141; see also figs. 9E-9I, ¶ 180-181, second connection line 72 with integral protrusions 86; see also ¶ 187-196, second connection lines 72 with integral protrusions 86 connected to protrusion 81 of first connection line 71 via V16), and the first transmission detour line comprises: a first main stream extending in the first direction between the first data line and the second transmission detour line (fig. 6, ¶ 136-141; see also figs. 9E-9I, ¶ 180-181, first connection line 71; see also ¶ 187-196); a first sub-branch disposed in the first detour side area, extending in the second direction from the first main stream, and overlapping a part of the first data line (fig. 6, ¶ 136-141; see also figs. 9E-9I, ¶ 180-181, first connection line 71 with integral protrusions 81; see also ¶ 187-196, data line 60 with integral protrusion 86 connected to protrusion 81 of first connection line 71 via V15); and a second sub-branch disposed in the second detour side area, extending in the second direction from the first main stream, and overlapping a part of the second transmission detour line (fig. 6, ¶ 136-141; see also figs. 9E-9I, ¶ 180-181, first connection line 71 with integral protrusions 81; see also ¶ 187-196, second connection lines 72 with integral protrusions 86 connected to protrusion 81 of first connection line 71 via V16). Regarding claim 2, Chen discloses wherein each of the pixel drivers comprises a data connection electrode electrically connected to one of the data lines through a data connection hole (figs. 1-5, ¶ 96-98, ¶ 102-109, pixel drive circuits; see also figs. 9G-9I, ¶ 187-196, data lines 60 connected with third connection electrode 43 via V13; see also ¶ 114-116), the pixel drivers comprise a first pixel driver adjacent to the first sub-branch of the first transmission detour line (figs. 1-5, ¶ 96-98, ¶ 102-109, pixel drive circuits; see also ¶ 114-116; see also figs. 9G-9I, e.g., M-1th row, N-1th column), the first data line comprises: a first main extension extending in the second direction (fig. 1, ¶ 96-97; see also fig. 6, figs. 9G-9I, ¶ 187-196, data lines 60); a first sub-protrusion adjacent to the first pixel driver, protruding from the first main extension and overlapping the first sub-branch (fig. 6, ¶ 136-141; see also figs. 9E-9I, ¶ 180-181, data line 60 with integral protrusions 86; see also ¶ 187-196, data line 60 with integral protrusion 86 connected to protrusion 81 of first connection line 71 via V15); and a second sub-protrusion adjacent to the first pixel driver, protruding from the first main extension and overlapping the data connection hole of the first pixel driver (figs. 1-5, ¶ 96-98, ¶ 102-109; see also figs. 9G-9I, ¶ 187-196, data lines 60 connected with third connection electrode 43 via V13; see also ¶ 114-116), the first transmission detour line is electrically connected to the first data line through a first detour connection hole overlapping the first sub-branch and the first sub-protrusion (fig. 6, ¶ 136-141; see also figs. 9E-9I, ¶ 180-181, first connection line 71 with integral protrusions 81; see also ¶ 187-196, data line 60 with integral protrusion 86 connected to protrusion 81 of first connection line 71 via V15), and the first detour connection hole is spaced apart from an intersection between the first main stream of the first transmission detour line and the first main extension of the first data line (fig. 6, ¶ 136-141; see also figs. 9E-9I, ¶ 180-181; see also ¶ 187-196, data line 60 with integral protrusion 86 connected to protrusion 81 of first connection line 71 via V15). Regarding claim 3, Chen discloses wherein the pixel drivers further comprise a second pixel driver disposed in the first detour side area, electrically connected to the first data line, and spaced apart from the first pixel driver (figs. 1-5, ¶ 96-98, ¶ 102-109, pixel drive circuits; see also ¶ 114-116; see also figs. 9G-9I, e.g., Mth row, N-1th column), the first data line further comprises a third sub-protrusion and a fourth sub-protrusion adjacent to the second pixel driver and protruding from the first main extension (fig. 6, ¶ 136-141; see also figs. 9E-9I, ¶ 180-181, data line 60 provided with protrusions 85 and 86; see also ¶ 187-196), the third sub-protrusion overlaps a first dummy hole (fig. 6, ¶ 136-141; see also figs. 9E-9I, ¶ 180-181, data line 60 provided with dummy electrodes 85; see also ¶ 187-197, via V17), and the fourth sub-protrusion overlaps the data connection electrode of the second pixel driver (figs. 1-5, ¶ 96-98, ¶ 102-109; see also figs. 9G-9I, ¶ 187-196, data lines 60 connected with third connection electrode 43 via V13; see also ¶ 114-116). Regarding claim 4, Chen discloses wherein the data lines and the second transmission detour line are disposed on a via layer covering the first transmission detour line and the data connection electrode, and the first detour connection hole, a second detour connection hole, and the first dummy hole penetrate the via layer (figs. 9G-9I, ¶ 184-186, fourth insulation layer 114; see also ¶ 187-196). Regarding claim 5, Chen discloses wherein the first dummy hole overlaps a dummy electrode covered with the via layer (figs. 9E-9I, ¶ 180-182, compensation traces 91 with compensation connection electrodes 82; see also ¶ 187-197, 85 connected with 82 via V17). Regarding claim 6, Chen discloses wherein the pixel drivers further comprise a third pixel driver disposed in the second detour side area, adjacent to the second sub-branch of the first transmission detour line, electrically connected to the second data line, and disposed parallel to the first pixel driver in the first direction (figs. 1-5, ¶ 96-98, ¶ 102-109, pixel drive circuits; see also ¶ 114-116; see also figs. 9G-9I, e.g., M-1th row, Nth column), and the second data line comprises: a second main extension extending in the second direction (fig. 1, ¶ 96-97; see also fig. 6, figs. 9G-9I, ¶ 187-196, data lines 60); a fifth sub-protrusion adjacent to the third pixel driver, protruding from the second main extension, and disposed parallel to the first sub-protrusion of the first data line in the first direction (fig. 6, ¶ 136-141; see also figs. 9E-9I, ¶ 180-181, data line 60 provided with protrusions 85; see also ¶ 187-196); and a sixth sub-protrusion adjacent to the third pixel driver, protruding from the second main extension, disposed parallel to the second sub-protrusion of the first data line in the first direction, and overlapping the data connection electrode of the third pixel driver (fig. 6, ¶ 136-141; see also figs. 9E-9I, ¶ 180-181, data line 60 provided with protrusions 86; see also ¶ 187-196), and the fifth sub-protrusion overlaps a second dummy hole penetrating the via layer (fig. 6, ¶ 136-141; see also figs. 9E-9I, ¶ 180-181, data line 60 provided with dummy electrodes 85; see also ¶ 187-197, via V17). Regarding claim 7, Chen discloses wherein the second transmission detour line comprises: a third main extension extending in the second direction (fig. 6, ¶ 136-141; see also figs. 9E-9I, ¶ 180-181, second connection line 72; see also ¶ 187-196); a seventh sub-protrusion adjacent to the third pixel driver, protruding from the third main extension, facing the fifth sub-protrusion of the second data line, and overlapping the second sub-branch (fig. 6, ¶ 136-141; see also figs. 9E-9I, ¶ 180-181; see also ¶ 187-196, second connection lines 72 with integral protrusions 86 connected to protrusion 81 of first connection line 71 via V16); and an eighth sub-protrusion adjacent to the third pixel driver, protruding from the third main extension, and facing the sixth sub-protrusion of the second data line (fig. 6, ¶ 136-141; see also figs. 9E-9I, ¶ 180-181; see also ¶ 187-197, second connection lines 72 with dummy electrodes 85), wherein the first transmission detour line is electrically connected to the second transmission detour line through a second detour connection hole overlapping the second sub-branch and the seventh sub-protrusion (fig. 6, ¶ 136-141; see also figs. 9E-9I, ¶ 180-181; see also ¶ 187-196, second connection lines 72 with integral protrusions 86 connected to protrusion 81 of first connection line 71 via V16), and the eighth sub-protrusion overlaps a third dummy hole penetrating the via layer (fig. 6, ¶ 136-141; see also figs. 9E-9I, ¶ 180-181; see also ¶ 187-197, second connection lines 72 with dummy electrodes 85 and via V17). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Lee et al. (US 2021/0391405). Regarding claim 16, Chen discloses a display device comprising: a substrate comprising: a main region comprising a display area in which emission areas are arranged and a non-display area disposed around the display area (abstract, figs. 1-2, ¶ 98-101, display region 100 and bezel region 300); and a sub-region protruding from a side of the main region (figs. 1-2, ¶ 98-101, display region 100 and bezel region 300; fig. 6, ¶ 127-130; see also ¶ 131-141, e.g., area to immediate left of center line O); a circuit layer disposed on the substrate and comprising pixel drivers respectively corresponding to the emission areas (figs. 1-2, ¶ 96-98, see also figs. 4-5, ¶ 105-109, e.g., circuit layer 102); and a light-emitting element layer disposed on the circuit layer and comprising light-emitting elements respectively corresponding to the emission areas (figs. 1-2, ¶ 96-98, see also figs. 4-5, ¶ 105-109, e.g., light emitting structure layer 103), wherein the circuit layer comprises: the pixel drivers respectively and electrically connected to the light-emitting elements of the light-emitting element layer (figs. 1-5, ¶ 96-98, ¶ 102-109, pixel drive circuits; see also ¶ 114-116); data lines which transmit data signals to the pixel drivers (fig. 1, ¶ 96-97; see also fig. 6, figs. 9G-9I, ¶ 187-196, data lines 60); first dummy lines extending in a first direction crossing the data lines (figs. 9E-9I, ¶ 180-184, first compensation traces 91; see also ¶ 143-147); and second dummy lines extending in a second direction parallel to the data lines and respectively adjacent to the data lines (figs. 9E-9I, ¶ 180-184, second compensation traces 92; see also ¶ 143-147), the data lines and the second dummy lines are disposed on a via layer covering the first dummy lines (figs. 9E-9I, ¶ 180-186, fourth insulation layer 114; see also ¶ 143-147, first and second compensation traces may be disposed in different layers, second compensation traces 92 disposed between adjacent data lines 60), one of the pixel drivers is adjacent to one of the data lines and one of the second dummy lines (figs. 9E-9I, ¶ 180-184; see also ¶ 143-147, second compensation traces 92 disposed between adjacent data lines 60), each of the one of the data lines and the one of the second dummy lines comprises: a main extension extending in the second direction (figs. 9E-9I, ¶ 180-184; see also ¶ 143-147, second compensation traces 92 disposed between adjacent data lines 60); and the one of the data lines comprises a pair of sub-protrusions protruding from the main extension in the first direction, each corresponding to the one of the pixel drivers, and overlapping via holes penetrating the via layer (fig. 6, ¶ 136-141; see also figs. 9E-9I, ¶ 180-181; see also ¶ 187-196, data line 60 with integral protrusion 86 connected to protrusion 81 of first connection line 71 via V15; data lines 60 connected with third connection electrode 43 via V13; see also ¶ 114-116), wherein in the display area, a detour area adjacent to the sub-region comprises a detour middle area disposed at a center in the first direction (fig. 6, ¶ 127-130; see also ¶ 131-141, e.g., area to immediate left of center line O), a first detour side area parallel to the detour middle area in the first direction and in contact with the non- display area (fig. 6, ¶ 127-130; see also ¶ 131-141, e.g., lower left corner of display area 100), and a second detour side area disposed between the detour middle area and the first detour side area (fig. 6, ¶ 127-130; see also ¶ 131-141, e.g., area between the area to immediate left of center line O and lower left corner), the data lines comprise a first data line disposed in the first detour side area and a second data line disposed in the second detour side area (fig. 1, ¶ 96-97; see also fig. 6, figs. 9G-9I, ¶ 187-196, data lines 60), the first dummy lines comprise a first transmission detour line directly and electrically connected to the first data line in the display area (fig. 6, ¶ 136-141, ¶ 143-147; see also figs. 9E-9I, ¶ 180-181, first connection line 71 with integral protrusions 81; see also ¶ 187-196, data line 60 with integral protrusion 86 connected to protrusion 81 of first connection line 71 via V15), the second dummy lines comprise a second transmission detour line adjacent to the second data line and electrically and directly connected to the first transmission detour line in the display area (fig. 6, ¶ 136-141, ¶ 143-147; see also figs. 9E-9I, ¶ 180-181, second connection line 72 with integral protrusions 86; see also ¶ 187-196, second connection lines 72 with integral protrusions 86 connected to protrusion 81 of first connection line 71 via V16), and the first transmission detour line comprises: a first main stream extending in the first direction between the first data line and the second transmission detour line (fig. 6, ¶ 136-141; see also figs. 9E-9I, ¶ 180-181, first connection line 71; see also ¶ 187-196); a first sub-branch disposed in the first detour side area, extending in the second direction from the first main stream, and overlapping a part of the first data line (fig. 6, ¶ 136-141; see also figs. 9E-9I, ¶ 180-181, first connection line 71 with integral protrusions 81; see also ¶ 187-196, data line 60 with integral protrusion 86 connected to protrusion 81 of first connection line 71 via V15); and a second sub-branch disposed in the second detour side area, extending in the second direction from the first main stream, and overlapping a part of the second transmission detour line (fig. 6, ¶ 136-141; see also figs. 9E-9I, ¶ 180-181, first connection line 71 with integral protrusions 81; see also ¶ 187-196, second connection lines 72 with integral protrusions 86 connected to protrusion 81 of first connection line 71 via V16). Chen fails to explicitly disclose the one of the second dummy lines comprises a pair of sub-protrusions protruding from the main extension in the first direction, each corresponding to the one of the pixel drivers, and overlapping via holes penetrating the via layer. Lee teaches the one of the second dummy lines comprises a pair of sub-protrusions protruding from the main extension in the first direction, adjacent to the one of the pixel drivers, and overlapping via holes penetrating the via layer (figs. 7-10, ¶ 131-150, e.g., protrusions overlapping contact holes CNT3 and CNT4). Chen and Lee are both directed to OLED display devices with dummy lines. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Chen with the device of Lee since such a modification provides that a visibility difference may be reduced (Lee, ¶ 152). Response to Arguments Applicant’s arguments with respect to claims 1 and 16 have been considered but are moot in view of the new ground(s) of rejection. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH L CRAWLEY whose telephone number is (571)270-7616. The examiner can normally be reached Monday - Friday 10-6 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae can be reached at 571-272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KEITH L CRAWLEY/Primary Examiner, Art Unit 2626
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Prosecution Timeline

Show 3 earlier events
Nov 18, 2025
Applicant Interview (Telephonic)
Nov 18, 2025
Examiner Interview Summary
Dec 02, 2025
Response Filed
Feb 18, 2026
Final Rejection mailed — §102, §103
Apr 17, 2026
Response after Non-Final Action
May 08, 2026
Request for Continued Examination
May 09, 2026
Response after Non-Final Action
May 14, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
59%
Grant Probability
86%
With Interview (+26.4%)
3y 4m (~5m remaining)
Median Time to Grant
High
PTA Risk
Based on 587 resolved cases by this examiner. Grant probability derived from career allowance rate.

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