DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an applications filed in Korea on 3/6/23 and 10/7/22. It is noted, however, that the certified copy of the KR10-2-22-0128587 application (with priority date 10/7/22) in the file wrapper is not complete and the figures provided do not appear to be from a Korean patent application. Thus Applicant has not filed a certified copy of the KR10-2022-0128587 application as required by 37 CFR 1.55.
Claim Objections
In light of the amendment filed 12/2/25, the objection to claims 6 and 16 for informalities is withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al. (US 2021/0035496).
Regarding claim 1, Cho discloses a display device comprising: a substrate comprising a main region comprising: a display area in which emission areas are arranged; and a non-display area disposed around the display area (figs. 1-2, ¶ 58-65);
a circuit layer disposed on the substrate (figs. 1-2, ¶ 58-65);
and a light-emitting element layer disposed on the circuit layer and comprising light-emitting elements respectively corresponding to the emission areas (figs. 1-2, ¶ 58-65, light-emitting layer disclosed, see also ¶ 102-106),
wherein a detour area on a side of the display area comprises: a detour middle area at a center (figs. 1-2, ¶ 58-65, e.g., central area of display area DA with connection lines DM, see also ¶ 74-88);
a first detour side area parallel to the detour middle area in a first direction and in contact with the non-display area (figs. 1-2, ¶ 58-65, e.g., bottom left corner of DA with connection lines DM, see also ¶ 74-88);
and a second detour side area disposed between the detour middle area and the first detour side area (figs. 1-2, ¶ 58-65, e.g., area between bottom left corner and central area of DA with connection lines DM, see also ¶ 74-88),
the circuit layer comprises: pixel drivers corresponding to the emission areas and electrically connected to the light-emitting elements of the light-emitting element layer, respectively (figs. 10-11, ¶ 102-111, e.g., sub-pixel R, G, and B circuits);
data lines which extend in a second direction crossing the first direction and transmit data signals to the pixel drivers (figs. 2-4, ¶ 74-88, signal lines DL);
a first transmission detour line electrically connected to, among the data lines, a first data line disposed in the first detour side area and extending in the first direction (figs. 2-5, ¶ 74-88, plurality of connection lines DM);
and a second transmission detour line adjacent to, among the data lines, a second data line disposed in the second detour side area, extending in the second direction, and electrically and physically connected to the first transmission detour line in the display area (figs. 2-5, ¶ 74-88, plurality of connection lines DM),
and the first transmission detour line comprises: a first main stream extending in the first direction between the first data line and the second transmission detour line (figs. 2-5, ¶ 74-88, DM2);
a first sub-branch disposed in the first detour side area, extending in the second direction from the first main stream, and overlapping a part of the first data line (figs. 2-5, ¶ 74-88, DM1);
and a second sub-branch disposed in the second detour side area, extending in the second direction from the first main stream, and overlapping a part of the second transmission detour line (figs. 2-5, ¶ 74-88, DM3).
Regarding claim 2, Cho discloses wherein each of the pixel drivers comprises a data connection electrode electrically connected to one of the data lines through a data connection hole (fig. 2, fig. 11, ¶ 80, signal line DL formed of conductive layer 130, see also ¶ 106-119, source electrode SE connected to source area of semiconductor layer ACT through contact hole),
the pixel drivers comprise a first pixel driver adjacent to the first sub-branch of the first transmission detour line (figs. 2-5, ¶ 74-88, DM1; see also fig. 11, ¶ 121, ¶ 127),
the first data line comprises: a first main extension extending in the second direction (figs. 2-4, ¶ 74-88, signal lines DL);
a first sub-protrusion adjacent to the first pixel driver, protruding from the first main extension and overlapping the first sub-branch (fig. 4, ¶ 74-81, DL protrusion connected to DM1 through CNT1);
and a second sub-protrusion adjacent to the first pixel driver, protruding from the first main extension and overlapping the data connection hole of the first pixel driver (fig. 2, fig. 11, ¶ 80, signal line DL formed of conductive layer 130, see also ¶ 106-119, source electrode SE connected to source area of semiconductor layer ACT through contact hole),
the first transmission detour line is electrically connected to the first data line through a first detour connection hole overlapping the first sub-branch and the first sub-protrusion (figs. 3-4, ¶ 74-81, DL protrusion connected to DM1 through CNT1),
and the first detour connection hole is spaced apart from an intersection between the first main stream of the first transmission detour line and the first main extension of the first data line (figs. 2-5, ¶ 74-88, CNT1).
Regarding claim 3, Cho discloses wherein the pixel drivers further comprise a second pixel driver disposed in the first detour side area, electrically connected to the first data line, and spaced apart from the first pixel driver (figs. 10-11, ¶ 102-111, e.g., sub-pixel R, G, and B circuits; see also fig. 2, ¶ 74-75),
the first data line further comprises a third sub-protrusion and a fourth sub-protrusion adjacent to the second pixel driver and protruding from the first main extension (fig. 2, fig. 11, ¶ 80, signal line DL formed of conductive layer 130, see also ¶ 106-119, source electrodes SE connected to source areas of semiconductor layer ACT through contact holes; see also ¶ 121-123, e.g., CP1),
the third sub-protrusion overlaps a first dummy hole (fig. 11, ¶ 121-123, ¶ 127, e.g., layer 140 may include dummy line DP1, CP1 connected to SE through contact hole),
and the fourth sub-protrusion overlaps the data connection electrode of the second pixel driver (fig. 2, fig. 11, ¶ 80, signal line DL formed of conductive layer 130, see also ¶ 106-119, source electrode SE connected to source area of semiconductor layer ACT through contact hole).
Regarding claim 4, Cho discloses wherein the data lines and the second transmission detour line are disposed on a via layer covering the first transmission detour line and the data connection electrode, and the first detour connection hole, a second detour connection hole, and the first dummy hole penetrate the via layer (figs. 4-7, ¶ 74-88, e.g., IL4, see also fig. 11, ¶ 102-111).
Regarding claim 5, Cho discloses wherein the first dummy hole overlaps a dummy electrode covered with the via layer (figs. 4-7, fig. 11, ¶ 121-123, ¶ 127, e.g., layer 140 may include dummy line DP1, CP1 connected to SE through contact hole).
Regarding claim 6, Cho discloses wherein the pixel drivers further comprise a third pixel driver disposed in the second detour side area, adjacent to the second sub-branch of the first transmission detour line, electrically connected to the second data line, and disposed parallel to the first pixel driver in the first direction (figs. 10-11, ¶ 102-111, e.g., sub-pixel R, G, and B circuits; see also ¶ 127; see also figs. 2-5, ¶ 74-88),
and the second data line comprises: a second main extension extending in the second direction (figs. 2-4, ¶ 74-88, signal lines DL);
a fifth sub-protrusion adjacent to the third pixel driver, protruding from the second main extension, and disposed parallel to the first sub-protrusion of the first data line in the first direction (fig. 2, fig. 11, ¶ 80, signal line DL formed of conductive layer 130, see also ¶ 106-119, source electrodes SE connected to source areas of semiconductor layer ACT through contact holes; see also ¶ 121-123, e.g., CP1);
and a sixth sub-protrusion adjacent to the third pixel driver, protruding from the second main extension, disposed parallel to the second sub-protrusion of the first data line in the first direction, and overlapping the data connection electrode of the third pixel driver (fig. 2, fig. 11, ¶ 80, signal line DL formed of conductive layer 130, see also ¶ 106-119, source electrodes SE connected to source areas of semiconductor layer ACT through contact holes; see also ¶ 121-123, e.g., CP1),
and the fifth sub-protrusion overlaps a second dummy hole penetrating the via layer (fig. 11, ¶ 121-123, ¶ 127, e.g., layer 140 may include dummy line DP1, CP1 connected to SE through contact hole).
Regarding claim 7, Cho discloses wherein the second transmission detour line comprises: a third main extension extending in the second direction (figs. 2-5, ¶ 74-88, DM3);
a seventh sub-protrusion adjacent to the third pixel driver, protruding from the third main extension, facing the fifth sub-protrusion of the second data line, and overlapping the second sub-branch (figs. 2-5, ¶ 74-88, DM2);
and an eighth sub-protrusion adjacent to the third pixel driver, protruding from the third main extension, and facing the sixth sub-protrusion of the second data line (figs. 2-5, ¶ 74-88, DM1),
wherein the first transmission detour line is electrically connected to the second transmission detour line through a second detour connection hole overlapping the second sub-branch and the seventh sub-protrusion (figs. 2-6, ¶ 74-88, e.g., CNT2),
and the eighth sub-protrusion overlaps a third dummy hole penetrating the via layer (fig. 11, ¶ 121-123, ¶ 127, e.g., layer 140 may include dummy line DP1, CP1 connected to SE through contact hole).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Lee et al. (US 2021/0391405).
Regarding claim 16, Cho discloses a display device comprising: a substrate comprising: a main region comprising a display area in which emission areas are arranged and a non-display area disposed around the display area (figs. 1-2, ¶ 58-65);
and a sub-region protruding from a side of the main region (figs. 1-2, ¶ 58-65, sub-region SR);
a circuit layer disposed on the substrate and comprising pixel drivers respectively corresponding to the emission areas (figs. 1-2, ¶ 58-65; see also figs. 10-11, ¶ 102-111, e.g., sub-pixel R, G, and B circuits);
and a light-emitting element layer disposed on the circuit layer and comprising light-emitting elements respectively corresponding to the emission areas (figs. 1-2, ¶ 58-65, light-emitting layer disclosed, see also ¶ 102-106),
wherein the circuit layer comprises: the pixel drivers respectively and electrically connected to the light-emitting elements of the light-emitting element layer (figs. 10-11, ¶ 102-111, e.g., sub-pixel R, G, and B circuits);
data lines which transmit data signals to the pixel drivers (figs. 2-4, ¶ 74-88, signal lines DL);
first dummy lines extending in a first direction crossing the data lines (figs. 4-9, ¶ 89-99, fig. 11, ¶ 121-123, ¶ 127, e.g., DP2);
and second dummy lines extending in a second direction parallel to the data lines and respectively adjacent to the data lines (figs. 4-9, ¶ 89-99, fig. 11, ¶ 121-123, ¶ 127, e.g., DP1),
the data lines and the second dummy lines are disposed on a via layer covering the first dummy lines (figs. 4-9, ¶ 89-99, e.g., IL4, see also fig. 11, ¶ 102-111),
one of the pixel drivers is adjacent to one of the data lines and one of the second dummy lines (fig. 2, figs. 4-9, ¶ 89-99, see also fig. 11, ¶ 102-111),
each of the one of the data lines and the one of the second dummy lines comprises: a main extension extending in the second direction (figs. 4-9, ¶ 89-99, fig. 11, ¶ 121-123, ¶ 127, e.g., DP1, DL; see also fig. 2);
and the one of the data lines comprises a pair of sub-protrusions protruding from the main extension in the first direction, adjacent to the one of the pixel drivers, and overlapping via holes penetrating the via layer (fig. 2, fig. 11, see also ¶ 106-119, source electrode SE connected to source area of semiconductor layer ACT through contact hole; see also ¶ 121-123).
Cho fails to explicitly disclose the one of the second dummy lines comprises a pair of sub-protrusions protruding from the main extension in the first direction, adjacent to the one of the pixel drivers, and overlapping via holes penetrating the via layer.
Lee teaches the one of the second dummy lines comprises a pair of sub-protrusions protruding from the main extension in the first direction, adjacent to the one of the pixel drivers, and overlapping via holes penetrating the via layer (figs. 7-10, ¶ 131-150, e.g., protrusions overlapping contact holes CNT3 and CNT4).
Cho and Lee are both directed to OLED display devices with dummy lines. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Cho with the device of Lee since such a modification provides that a visibility difference may be reduced (Lee, ¶ 152).
Regarding claim 17, this claim is rejected under the same rationale as claim 1.
Response to Arguments
Applicant's arguments filed 12/2/25 have been fully considered but they are not persuasive. Regarding claim 1, Applicant argues “Cho does not disclose that the alleged first and second transmission detour lines are electrically connected to each other” and “Cho does not disclose that the alleged first and second transmission detour lines are physically connected to each other in the display area” (Remarks, pp. 17-19).
Examiner disagrees. Examiner notes that ¶ 76 of Applicant’s specification explicitly discusses the use of the phrase “connected” in contrast with the phrase “directly connected” (i.e., without intervening elements). Thus, under the broadest reasonable interpretation of “connected” as is claimed, intervening elements are allowed. Thus, for example, all elements of Cho’s device are “physically connected”.
Applicant’s remaining arguments are moot in view of the new ground(s) of rejection above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH L CRAWLEY whose telephone number is (571)270-7616. The examiner can normally be reached Monday - Friday 10-6 ET.
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/KEITH L CRAWLEY/Primary Examiner, Art Unit 2626