Prosecution Insights
Last updated: July 17, 2026
Application No. 18/226,988

PRINTED CIRCUIT BOARD

Non-Final OA §102§103§112
Filed
Jul 27, 2023
Priority
Mar 31, 2023 — RE 10-2023-0042652
Examiner
MAI, ANH D
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electro-Mechanics Co., Ltd.
OA Round
2 (Non-Final)
38%
Grant Probability
At Risk
2-3
OA Rounds
8m
Est. Remaining
48%
With Interview

Examiner Intelligence

Grants only 38% of cases
38%
Career Allowance Rate
265 granted / 701 resolved
-30.2% vs TC avg
Moderate +10% lift
Without
With
+9.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
36 currently pending
Career history
760
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
82.8%
+42.8% vs TC avg
§102
11.6%
-28.4% vs TC avg
§112
5.0%
-35.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 701 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of the Claims Species 8, as shown in FIGs. 16-17, was elected. Amendment filed on March 17, 2026 is acknowledged. New claim 21 has been added. Claims 1 and 18 have been amended. Non-Elected Species, claims 9 and 12 have been withdrawn from consideration. Claims 1-21 are pending. Action on merits of the Elected Species, claims 1-8, 10-11 and 13-21 follows. Specification The newly submitted title is not descriptive. The title is A PRINTED CIRCUIT BOARD HAVING AN INTECONNECT BRIDGE STRUCTURE EMBEDDED IN THE SUBSTRATE PROVIDING A DIRECT CONNECTION BETWEEN TWO SEMICONDUCTOR CHIPS Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. Claim 21 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. There does not appear to be a written description of the claim limitation “wherein the encapsulant comprises a single layer of the resin” (new claim 21) (emphasis added) in the application as filed. Applicant must cancel the un-support new matters in response to the Office Action. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-8, 10-11, 13-15 and 17-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by HABA (US. Pub. No. 2017/0170121). With respect to claim 1, HABA teaches a printed circuit board as claimed including: a substrate (200) having an upper surface at which a plurality of first pads (406) are disposed; and an interconnect structure (100) including an encapsulant comprising a resin, a plurality of second pads (406) disposed at an upper surface of the encapsulant, and a plurality of metal wires disposed in and in contact with the encapsulant and respectively connected to at least one of the plurality of second pads (406), the interconnect structure (100) disposed on an upper side of the substrate (200), wherein at least a portion of an upper surface of each of the plurality of first and second pads (406) is exposed in an upward direction from the upper surface of each of the substrate (200) and the encapsulant. (See FIGs. 3-4). With respect to claim 2, the plurality of metal wires of HABA include a first metal wire connecting at least two second pads (406), among the plurality of second pads, to each other. With respect to claim 3, the at least two second pads (406) of HABA, connected to each other via the first metal wire, are semiconductor chip mounting pads respectively connected to first (206) and second (208) semiconductor chips. With respect to claim 4, the first metal wire of HABA includes: a first-first wire portion having a predetermined length in a horizontal direction; a first-second wire portion extending from one end of the first-first wire portion and connected to one of the plurality of second pads; and a first-third wire portion extending from the other end of the first-first wire portion and connected to another one of the plurality of second pads. With respect to claim 5, one or more third pads (406) of HABA are further disposed on or in the substrate, and the interconnect structure is disposed on the one or more third pads. With respect to claim 6, the plurality of metal wires of HABA further include a second metal wire connecting at least one second pad (406), among the plurality of second pads, to at least one third pad (406), among the one or more third pads. With respect to claim 7, the at least one second pad (406) of HABA, connected to the second metal wire, is a semiconductor chip mounting pad connected to at least one of first (206) and second (208) semiconductor chips. With respect to claim 8, the second metal wire of HABA includes a second-first wire portion having a predetermined length in a vertical direction, the second-first wire portion having one end and the other end respectively connected to one of the plurality of second pads (406) and one of the one or more third pads (406). With respect to claim 10, a plurality of fourth pads (406) of HABA are further disposed on a lower surface of the substrate, and one or more interconnection layers (304) and one or more via layers, connecting at least one of the one or more third pads to at least one of the plurality of fourth pads, are further disposed in the substrate. With respect to claim 11, the substrate (200) of HABA has a cavity (402) passing through a portion of the substrate (200) from the upper surface of the substrate to a lower surface of the substrate, and the interconnect structure (100) is disposed in the cavity (402) such that the other surface of the encapsulant is attached to a bottom surface of the cavity. With respect to claim 13, the interconnect structure (100) of HABA is in contact with a side surface of the cavity. With respect to claim 14, the interconnect structure (100) of HABA is embedded and disposed on the upper side of the substrate such that at least a portion of the upper surface of each of the plurality of second pads is exposed from the upper surface of the substrate. With respect to claim 15, the printed circuit substrate of HABA further comprises: a first semiconductor chip (206) disposed on the substrate (200) and connected to at least one or more of the plurality of first and second pads; and a second semiconductor chip (208) disposed on the substrate (200) and connected to at least another one or more of the plurality of first and second pads. With respect to claim 17, the plurality of metal wires of HABA are electrically insulated from each other within the interconnect structure. With respect to claim 21, As best understood by the Examiner, the encapsulant of HABA comprises a single layer of resin. With respect to claim 18, HABA teaches a printed circuit substrate as claimed including: a substrate (100); and an interconnect structure disposed at an outermost side of the substrate, the interconnect structure including a plurality of metal wires (102) without a via, wherein at least one of the plurality of metal wires (102) includes a signal line interconnecting a plurality of semiconductor chips (206, 208). (See FIGs. 3-4). With respect to claim 19, the printed circuit substrate of HABA further comprises: the plurality of semiconductor chips (206, 208) disposed on the substrate. With respect to claim 20, the at least one metal wire (102) of HABA consecutively has a predetermined length, and is bent at at least one point. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over HABA ‘121 as applied to claim 1 above, and further in view of ECTON et al. (US. Pub. No. 2019/0304912). HABA teaches the printed circuit board as described in claim 1 above including: plurality of metal wire (102) disposed in the encapsulant. Thus, HABA is shown to teach all the features of the claim with the exception of explicitly disclosing the metal wires comprising gold. However, ECTON teaches a printed circuit board including: plurality of metal wire (111) disposed in the encapsulant, wherein the plurality of metal wires (111) comprising gold. (See FIG. 1). Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the interconnect structure of HABA utilizing metal wires comprising gold or any other metals as taught by ECTON for the same intended purpose of providing electrical connections between the chips. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416., 125 USPQ 416. Response to Arguments Applicant’s arguments with respect to amended claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue A Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANH D MAI/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Jul 27, 2023
Application Filed
Dec 31, 2025
Non-Final Rejection mailed — §102, §103, §112
Mar 17, 2026
Response Filed
Mar 31, 2026
Final Rejection mailed — §102, §103, §112
Jun 30, 2026
Response after Non-Final Action

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
38%
Grant Probability
48%
With Interview (+9.9%)
3y 8m (~8m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 701 resolved cases by this examiner. Grant probability derived from career allowance rate.

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