DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
IDS
The IDS document(s) filed on 04/22/2026 have been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 20 have been considered but are
moot in view of new grounds of rejection.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-7, 9-10, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2017/0365591 A1), hereafter “Chang”, in view of Ahn (US 2020/0118976 A1), hereafter “Ahn”, and further in view of Lee (US 2021/0028146 A1), hereafter “Lee”.
As to claim 1, Chang teaches a method of manufacturing a semiconductor package, the method comprising:
stacking, via an adhesive member (140, Fig. 2, ⁋ [0027]; 240, Fig. 6, ⁋ [0033]), a plurality of memory dies (120, Fig. 7, ⁋ [0023]; 220, Fig. 7, ⁋ [0032]; 320, Fig. 8, ⁋ [0038]) to form a memory die stack on a buffer die (100, Fig. 7, ⁋ [0021]);
forming a first molding member (500, Fig. 9, ⁋ [0047]) on the buffer die to cover the memory die stack;
polishing an upper surface of the first molding member (⁋⁋ [0053]-[0054], Fig. 12) to expose an upper surface of an uppermost memory die in the memory die stack, the uppermost memory die positioned in an uppermost layer in the memory die stack;
forming a second molding member (550, Fig. 11, ⁋ [0052]).
Chang fails to teach removing edge portions of the uppermost memory die together with at least a portion of the first molding member and at least a portion of the adhesive member to form a stepped portion, forming, after polishing the upper surface of the first molding member, a second molding member on the first molding member to cover the stepped portion of the uppermost memory die.
Ahn teaches a method of manufacturing a semiconductor package wherein an edge of a memory die (D1, Fig. 6, ⁋ [00416]) and a portion of molding member (140, Fig. 6, ⁋ [0033]) are removed (Fig. 7A) to form a step portion (110a, ⁋ [0079]) and a second molding member (140a, Figs. 9+10, ⁋ [0047]) to cover the step portion.
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the method of removing the edge portions of a die as taught by Ahn into the method of Chang because since memory die stacks may be disposed adjacent to each other, a distance between scribe lanes may be reduced, and more semiconductor memory apparatuses 100 may be manufactured using one wafer (⁋ [0117]).
Additionally, forming the second molding member as taught by Chang (550, Fig. 11) would cover the stepped portion as taught by Ahn (110a).
Chang modified by Ahn fail to teach the formation of the second molding member after polishing the upper surface of the first molding member.
Lee teaches a similar method of manufacturing a package (⁋ [0002]) wherein a first molding part (400, Fig. 9, ⁋ [0070]) is polished (⁋ [0071]) prior to forming a second molding part (600, Fig. 12, ⁋ [0081]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Lee’s polishing the upper surface of the first molding part to the method of Chang and Ahn for the benefit of the possibility of detachment and breakage of the semiconductor chips may be reduced or minimized along with a reduction in the size of the semiconductor package (⁋ [0073]).
As to claim 2, Chang in view of Ahn and Lee teach the method of claim 1, Chang teaches further comprising:
polishing an upper surface of the second molding member (⁋⁋ [0053]-[0054], Fig. 12) to expose the upper surface of the uppermost memory die in the memory stack.
As to claim 3, Chang in view of Ahn and Lee teach the method of claim 1, Chang teaches wherein stacking the plurality of memory dies to form the memory die stack includes allowing the adhesive member to overflow from between the memory dies (⁋⁋ [0028], [0035], Fig. 7, as1+as2).
As to claim 4, Chang in view of Ahn and Lee teach the method of claim 3, Chang teaches wherein forming the first molding member (500) to cover the memory die stack further includes covering the at least a portion of the adhesive member that is allowed to overflow (as1+as2) from between the plurality of memory dies in the memory die stack with the first molding member (Fig. 9).
As to claim 5, Chang in view of Ahn and Lee teach the method of claim 3, Chang teaches wherein removing the edge portions of the uppermost memory die in the memory die stack to form the stepped portion further includes removing the edge portions of the uppermost memory die in the memory die stack together with the portion of the first molding member and the overflowing adhesive member (see claim 1).
As to claim 6, Chang in view of Ahn and Lee teach the method of claim 1, Chang teaches wherein the adhesive member includes a non- conductive film (⁋⁋ [0027], [0033], “non-conductive film”).
As to claim 7, Chang in view of Ahn and Lee teach the method of claim 1, Chang teaches wherein the first molding member includes a first mold material, and the second molding member includes a second mold material different from the first mold material (⁋ [0052], “For example, the second molding layer 550 may include a material different from that of the first molding layer 500”).
As to claim 9, Chang in view of Ahn and Lee teach the method of claim 1, but fail to teach wherein a ratio of (i) a depth of the stepped portion from the upper surface of the uppermost memory die in the memory die stack to (ii) a horizontal portion of the stepped portion is within a range of 10μm to l00μm.
On the other hand, Examiner notes the Applicant has not specified a criticality to the dimensions.
If the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device: In re Gardner v. TEC Systems, Inc., 220 USPQ 777.
As to claim 10. Chang in view of Ahn and Lee teach the method of claim 1, but fail to teach wherein a distance from an outer surface of the uppermost memory die in the memory die stack to a vertical portion of the stepped portion is within a range of 10μm to 50μm.
On the other hand, Examiner notes the Applicant has not specified a criticality to the dimensions.
If the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device: In re Gardner v. TEC Systems, Inc., 220 USPQ 777.
As to claim 20, Chang teaches a method of manufacturing a semiconductor package, the method comprising:
stacking a plurality of memory dies (120, Fig. 7, ⁋ [0023]; 220, Fig. 7, ⁋ [0032]; 320, Fig. 8, ⁋ [0038]; ⁋ [0062], “the first to third semiconductor chips 120, 220 and 320 may each be memory chips”) to form a memory die stack on a buffer die (100, Fig. 7, ⁋ [0021]) via an adhesive member (140, Fig. 2, ⁋ [0027]; 240, Fig. 6, ⁋ [0033]);
forming a first molding member (500, Fig. 9, ⁋ [0047]) on the buffer die (100) to cover the memory die stack (120+220+320) and a portion of the adhesive member (⁋⁋ [0028], [0035], Fig. 7, as1+as2) that overflows from between the memory dies;
polishing an upper surface of the first molding member (⁋⁋ [0053]-[0054], Fig. 12) to expose an upper surface of an uppermost memory die (320) in the memory die stack, the uppermost memory die positioned in an uppermost layer in the memory die stack;
forming a second molding member (550, Fig. 11, ⁋ [0052]); and
polishing an upper surface of the second molding member (⁋⁋ [0053]-[0054], Fig. 12) to expose the upper surface of the uppermost memory die in the memory die stack.
Chang fails to teach removing edge portions of the uppermost memory die in the memory die stack together with at least a portion of the first molding member and at the portion of the adhesive member to form a stepped portion; and forming a second molding member on the first molding member to cover the stepped portion of the uppermost memory die in the memory die stack.
Ahn teaches a method of manufacturing a semiconductor package wherein an edge of a memory die (D1, Fig. 6, ⁋ [00416]) and a portion of molding member (140, Fig. 6, ⁋ [0033]) are removed (Fig. 7A) to form a step portion (110a, ⁋ [0079]) and a second molding member (140a, Figs. 9+10, ⁋ [0047]) to cover the step portion.
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the method of removing the edge portions of a die as taught by Ahn into the method of Chang because since memory die stacks may be disposed adjacent to each other, a distance between scribe lanes may be reduced, and more semiconductor memory apparatuses 100 may be manufactured using one wafer (⁋ [0117]).
Additionally, forming the second molding member as taught by Chang (550, Fig. 11) would cover the stepped portion as taught by Ahn (110a).
Chang modified by Ahn fail to teach the formation of the second molding member after polishing the upper surface of the first molding member.
Lee teaches a similar method of manufacturing a package (⁋ [0002]) wherein a first molding part (400, Fig. 9, ⁋ [0070]) is polished (⁋ [0071]) prior to forming a second molding part (600, Fig. 12, ⁋ [0081]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Lee’s polishing the upper surface of the first molding part to the method of Chang and Ahn for the benefit of the possibility of detachment and breakage of the semiconductor chips may be reduced or minimized along with a reduction in the size of the semiconductor package (⁋ [0073]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Ahn and Lee, as applied to claim 7, further in view of Moon et al. (US 2017/0154872 A1), hereafter “Moon”, and further in view of Chou et al. (US 2017/0243858 A1), hereafter “Chou”.
As to claim 8, Chang in view of Ahn and Lee teach the method of claim 7, but fail to teach wherein each of the first and second mold materials includes at least one of an epoxy mold compound (EMC), UV resin, polyurethane resin, silicone resin and silica filler.
Moon teaches a similar semiconductor package with a molding layer (Fig. 1, 190, ⁋ [0035]) which contains an epoxy mold compound material (⁋ [0046]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the EMC material as taught by Moon as the first or second mold material of Chang in view of Ahn and Lee since it has already been known in the art to use the material for a molding layer.
Chang in view of Ahn, Lee and Moon fail to teach a second/different material for the molding layer as is required by claim 7, from which claim 8 depends.
Chou teaches a chip stack (⁋ [0052], 100) with a molding compound (Fig.1, 30, ⁋ [0056]) which contains a mixture of epoxy and silica fillers (⁋ [0056]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the epoxy and silica filler material as taught by Chou as the first or second mold material of Chang in view of Ahn, Lee and Moon since it has already been known in the art to use the material for a molding layer.
Indication of Allowable Subject Matter
Claim 21 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 21, Chang in view of Ahn and Lee are the closest prior art and fail to teach wherein after removing the edge portions to form the stepped portion, at least a portion of the adhesive member covers a side surface of the stepped portion and is covered by the second molding member.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARNELL HUNTER whose telephone number is (571)270-1796. The examiner can normally be reached Monday - Friday 7:30 am - 4:30pm.
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/CARNELL HUNTER III/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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