Prosecution Insights
Last updated: April 19, 2026
Application No. 18/226,994

PRINTED CIRCUIT BOARD

Non-Final OA §102§103
Filed
Jul 27, 2023
Examiner
PHAM, LONG
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electro-Mechanics Co., Ltd.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
97%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allow Rate
1493 granted / 1633 resolved
+23.4% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
38 currently pending
Career history
1671
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
39.9%
-0.1% vs TC avg
§102
41.8%
+1.8% vs TC avg
§112
11.1%
-28.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1633 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-4 and 6-20 in the reply filed on 1/5/26 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2, and 12-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jang et al. (US pub 20220157730). With respect to claim 1, Jang et al. teach a printed circuit board, comprising (see figs. 1-12, particularly fig. 11 and associated text): a substrate portion 100 including a first insulating layer 112, a first wiring layer 122, 123 disposed on or within the first insulating layer, and a cavity (area where 200 occupies) penetrating through at least a portion of the first insulating layer; a connection structure 200 disposed within the cavity of the substrate portion, and including a second insulating layer 212, a second wiring layer 222 disposed on or within the second insulating layer, and a metal layer M disposed on a lower surface and a side surface of the second insulating layer, wherein the metal layer is disposed on an outermost side of the connection structure. With respect to claim 2, Jang et al. teach the connection structure further comprises a protective layer (insulating layer right under 223) disposed between the metal layer and the second insulating layer. See fig. 11 and associated text. With respect to claim 12, Jang et al. teach wiring density of the second wiring layer is greater than wiring density of the first wiring layer. See fig. 11 and associated text. With respect to claim 13, Jang et al. teach a thickness of any one of the second insulating layers is less than a thickness of any one of the first insulating layers. See fig. 11 and associated text. With respect to claim 14, Jang et al. teach the first insulating layer and the second insulating layer comprise an organic material, respectively. See fig. 11 and associated text. With respect to claim 15, Jang et al. teach a first semiconductor chip 310 disposed on a portion of the substrate portion and a portion of the connection structure, and connected to a portion of the substrate portion and a portion of the connection structure; and a second semiconductor chip 320 disposed on another portion of the substrate portion and another portion of the connection structure, and connected to another portion of the substrate portion and another portion of the connection structure and connected to the first semiconductor chip through the connection structure. See fig. 11 and associated text. With respect to claim 16, Jang et al. teach the connection structure includes first (top) and second (bottom) surfaces opposing each other in which the second surface faces a bottom surface of the cavity, and third (left) and fourth (right) surfaces opposing each other, and the metal layer provides only the second to fourth surfaces among the first to fourth surfaces of the connection structure. See fig. 11 and associated text. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US pub 20220157730). With respect to claim 4, Jang et al. fail to teach the metal layer is copper or al. However, the use of copper or al metal layer is well-known semiconductor art. Claim(s) 17 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jang et al. (US pub 20220157730). With respect to claim 17, Jang et al. teach a printed circuit board, comprising (see figs. 1-12, particularly fig. 11 and associated text): a substrate portion 100 including a first insulating layer 112, a first wiring layer 122, 123 disposed on or within the first insulating layer, and a cavity (area where 200 occupies) penetrating through at least a portion of the first insulating layer; and a connection structure 200 disposed within the cavity of the substrate portion, and including a second insulating layer 212, a second wiring layer 222 disposed on or within the second insulating layer, a protective layer (insulating layer right under 223) covering a lower surface and a side surface of the second insulating layer, and a metal layer M disposed on the protective layer. With respect to claim 20, Jang et al. teach the connection structure includes first (top) and second (bottom) surfaces opposing each other in which the second surface faces a bottom surface of the cavity, and third (left) and fourth (right) surfaces opposing each other, and the metal layer provides only the second to fourth surfaces among the first to fourth surfaces of the connection structure. See fig. 11 and associated text. Allowable Subject Matter Claims 3, 6-11, and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Examiner’s Cited References The cited references generally show the similar or related structure having a connecting wiring structure covered with a metal shielding layer partly embedded in another wiring structure as presently claimed by applicant. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG PHAM whose telephone number is (571)272-1714. The examiner can normally be reached Mon-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LONG . PHAM Examiner Art Unit 2823 /LONG PHAM/ Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Jul 27, 2023
Application Filed
Mar 20, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
97%
With Interview (+5.6%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 1633 resolved cases by this examiner. Grant probability derived from career allow rate.

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